On 6/13/2022 1:16 AM, Tvrtko Ursulin wrote:
On 10/06/2022 00:19, Daniele Ceraolo Spurio wrote:
On DG2, HuC loading is performed by the GSC, via a PXP command. The load
operation itself is relatively simple (just send a message to the GSC
with the physical address of the HuC in LMEM), but the
On 6/13/2022 9:31 AM, Tvrtko Ursulin wrote:
On 13/06/2022 16:39, Ceraolo Spurio, Daniele wrote:
On 6/13/2022 1:16 AM, Tvrtko Ursulin wrote:
On 10/06/2022 00:19, Daniele Ceraolo Spurio wrote:
On DG2, HuC loading is performed by the GSC, via a PXP command. The
load
operation itself is
On 6/13/2022 9:56 AM, Tvrtko Ursulin wrote:
On 13/06/2022 17:41, Ceraolo Spurio, Daniele wrote:
On 6/13/2022 9:31 AM, Tvrtko Ursulin wrote:
On 13/06/2022 16:39, Ceraolo Spurio, Daniele wrote:
On 6/13/2022 1:16 AM, Tvrtko Ursulin wrote:
On 10/06/2022 00:19, Daniele Ceraolo Spurio wrote
On 6/13/2022 10:39 AM, Tvrtko Ursulin wrote:
On 13/06/2022 18:06, Ceraolo Spurio, Daniele wrote:
On 6/13/2022 9:56 AM, Tvrtko Ursulin wrote:
On 13/06/2022 17:41, Ceraolo Spurio, Daniele wrote:
On 6/13/2022 9:31 AM, Tvrtko Ursulin wrote:
On 13/06/2022 16:39, Ceraolo Spurio, Daniele
On 6/14/2022 12:44 AM, Tvrtko Ursulin wrote:
On 13/06/2022 19:13, Ceraolo Spurio, Daniele wrote:
On 6/13/2022 10:39 AM, Tvrtko Ursulin wrote:
On 13/06/2022 18:06, Ceraolo Spurio, Daniele wrote:
On 6/13/2022 9:56 AM, Tvrtko Ursulin wrote:
On 13/06/2022 17:41, Ceraolo Spurio, Daniele wrote
On 6/15/2022 3:13 AM, Tvrtko Ursulin wrote:
On 15/06/2022 00:15, Ye, Tony wrote:
On 6/14/2022 8:30 AM, Ceraolo Spurio, Daniele wrote:
On 6/14/2022 12:44 AM, Tvrtko Ursulin wrote:
On 13/06/2022 19:13, Ceraolo Spurio, Daniele wrote:
On 6/13/2022 10:39 AM, Tvrtko Ursulin wrote:
On 13/06
On 6/21/2022 5:34 PM, Matt Roper wrote:
On Tue, Jun 21, 2022 at 04:30:05PM -0700, Daniele Ceraolo Spurio wrote:
The only difference between the ADL S and P GuC FWs is the HWConfig
support. ADL-N does not support HWConfig, so we should use the same
binary as ADL-S, otherwise the GuC might atte
On 6/15/2022 7:28 PM, Zhang, Carl wrote:
On From: Ye, Tony
Sent: Thursday, June 16, 2022 12:15 AM
On 6/15/2022 3:13 AM, Tvrtko Ursulin wrote:
On 15/06/2022 00:15, Ye, Tony wrote:
On 6/14/2022 8:30 AM, Ceraolo Spurio, Daniele wrote:
On 6/14/2022 12:44 AM, Tvrtko Ursulin wrote:
On 13/06
On 7/6/2022 10:26 AM, Ye, Tony wrote:
On 7/5/2022 4:30 PM, Ceraolo Spurio, Daniele wrote:
On 6/15/2022 7:28 PM, Zhang, Carl wrote:
On From: Ye, Tony
Sent: Thursday, June 16, 2022 12:15 AM
On 6/15/2022 3:13 AM, Tvrtko Ursulin wrote:
On 15/06/2022 00:15, Ye, Tony wrote:
On 6/14/2022 8
On 3/8/2022 8:36 AM, Alexander Usyskin wrote:
From: Tomas Winkler
GSC is a graphics system controller, it provides
a chassis controller for graphics discrete cards.
There are two MEI interfaces in GSC: HECI1 and HECI2.
Both interfaces are on the BAR0 at offsets 0x00258000 and 0x00259000.
G
On 3/8/2022 8:36 AM, Alexander Usyskin wrote:
From: Tomas Winkler
GSC is a graphics system controller, based on CSE, it provides
a chassis controller for graphics discrete cards, as well as it
supports media protection on selected devices.
mei_gsc binds to a auxiliary devices exposed by Inte
the logic to
fetch the FW version, as that is interesting info for sysfs. Not a blocker.
Signed-off-by: Alexander Usyskin
Signed-off-by: Tomas Winkler
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/misc/mei/gsc-me.c | 11 ++-
1 file changed, 6 insertions(+), 5
On 3/8/2022 8:36 AM, Alexander Usyskin wrote:
Add a hook to retrieve the firmware version of the
GSC devices to bus-fixup.
GSC has a different MKHI clients GUIDs but the same message structure
to retrieve the firmware version as MEI so mei_fwver() can be reused.
CC: Ashutosh Dixit
Signed-off
GEN12_COMPUTE3_RING_BASE 0x26000
#define BLT_RING_BASE 0x22000
+#define DG1_GSC_HECI1_BASE 0x00258000
+#define DG1_GSC_HECI2_BASE 0x00259000
You ended up keeping the HECI1 define. Not a blocker, so:
Reviewed-by: Daniele Ceraolo Spurio
Daniele
diff --git a/drivers/gpu/drm/i915
Intel discrete
driver i915.
Signed-off-by: Alexander Usyskin
Signed-off-by: Tomas Winkler
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
V4: drop debug prints
replace selects with depends on in Kconfig
V5: Rebase
V6: Rebase
V7: add Greg KH Reviewed-by
V8: Rebase
V9: Rebase
V11
Can you re-send this series with an added patch to force
CONFIG_INTEL_MEI_GSC to be selected for CI? we don't need to review or
merge that additional patch, but I want to make sure we get CI results
with the config turned on before we merge this series. I'm also going to
ping the CI team to see
On 3/25/2022 11:37 AM, Das, Nirmoy wrote:
On 3/25/2022 6:58 PM, Daniele Ceraolo Spurio wrote:
In intel_gt_wait_for_idle, we use the remaining timeout returned from
intel_gt_retire_requests_timeout to wait on the GuC being idle. However,
the returned variable can have a negative value if some
Hi,
Yes, the series doesn't need an update, but on the other hand I don't
think we can update the config repo before the new config option is
merged, which we can't do without first running CI with the config
enabled, so we have a catch-22 situation. That's why I suggested that
you resend the
On 5/6/2022 12:51 AM, Tvrtko Ursulin wrote:
On 05/05/2022 19:56, John Harrison wrote:
On 5/4/2022 16:46, Daniele Ceraolo Spurio wrote:
From: Matthew Brost
In GuC submission mode the EU priority must be updated by the GuC
rather
than the driver as the GuC owns the programming of the conte
On 3/18/2022 4:39 PM, Andi Shyti wrote:
From: Tvrtko Ursulin
On a multi-tile platform, each tile has its own registers + GGTT
space, and BAR 0 is extended to cover all of them.
Up to four GTs are supported in i915->gt[], with slot zero
shadowing the existing i915->gt0 to enable source compa
On 5/11/2022 12:11 PM, Ceraolo Spurio, Daniele wrote:
On 3/18/2022 4:39 PM, Andi Shyti wrote:
From: Tvrtko Ursulin
On a multi-tile platform, each tile has its own registers + GGTT
space, and BAR 0 is extended to cover all of them.
Up to four GTs are supported in i915->gt[], with s
12: In addition to stopping the cs, we need
+* to wait for any pending mi force wakeups
+*/
+ if (IS_GRAPHICS_VER(engine->i915, 11, 12))
+ intel_engine_wait_for_pending_mi_fw(engine);
+
Ringbuffer submission is not supported on gen 11 and 12, so no need for
this.
Wit
context switch out when their condition is not satisfied, which is not
something we currently allow (but we do plan to as you mentioned). Also,
the routing only happens when in GuC submission mode.
Reviewed-by: Daniele Ceraolo Spurio
Daniele
Signed-off-by: Michał Winiarski
---
drivers/gpu
On 7/15/2022 3:54 PM, Daniele Ceraolo Spurio wrote:
This patch re-introduces support for GuC v69 in parallel to v70. As this
is a quick fix, v69 has been re-introduced as the single "fallback" guc
version in case v70 is not available on disk. All v69 specific code has
been labeled as such for
On 7/18/2022 3:02 AM, Tvrtko Ursulin wrote:
Hi,
On 15/07/2022 23:54, Daniele Ceraolo Spurio wrote:
This patch re-introduces support for GuC v69 in parallel to v70. As this
is a quick fix, v69 has been re-introduced as the single "fallback" guc
version in case v70 is not available on disk. A
On 7/18/2022 4:26 AM, Tvrtko Ursulin wrote:
On 09/07/2022 00:48, Daniele Ceraolo Spurio wrote:
The current HuC status getparam return values are a bit confusing in
regards to what happens in some scenarios. In particular, most of the
error cases cause the ioctl to return an error, but a coup
On 7/18/2022 2:19 PM, John Harrison wrote:
On 7/15/2022 15:54, Daniele Ceraolo Spurio wrote:
This patch re-introduces support for GuC v69 in parallel to v70. As this
is a quick fix, v69 has been re-introduced as the single "fallback" guc
version in case v70 is not available on disk. All v69 s
On 7/19/2022 12:34 AM, Tvrtko Ursulin wrote:
On 18/07/2022 17:41, Ceraolo Spurio, Daniele wrote:
On 7/18/2022 3:02 AM, Tvrtko Ursulin wrote:
Hi,
On 15/07/2022 23:54, Daniele Ceraolo Spurio wrote:
This patch re-introduces support for GuC v69 in parallel to v70. As
this
is a quick fix
On 7/21/2022 2:29 AM, Tvrtko Ursulin wrote:
On 19/07/2022 16:29, Ceraolo Spurio, Daniele wrote:
On 7/19/2022 12:34 AM, Tvrtko Ursulin wrote:
On 18/07/2022 17:41, Ceraolo Spurio, Daniele wrote:
On 7/18/2022 3:02 AM, Tvrtko Ursulin wrote:
Hi,
On 15/07/2022 23:54, Daniele Ceraolo
On 7/27/2022 6:44 PM, John Harrison wrote:
On 7/27/2022 17:33, Daniele Ceraolo Spurio wrote:
The GuC FW applies the parent context policy to all the children,
so individual updates to the children are not supported and we
should not send them.
Note that sending the message did not have any f
stead make sure all CT messages
(if any) have been processed before the disable. Not a blocker for this
patch, can be done as a follow-up.
Reviewed-by: Daniele Ceraolo Spurio
Daniele
Signed-off-by: John Harrison
---
.../i915/gt/uc/abi/guc_communication_ctb_abi.h | 8 +---
drivers/gpu
still under force_probe. Don't need to
re-send, just add it on when merging.
Reviewed-by: Daniele Ceraolo Spurio
Daniele
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/
On 8/9/2022 3:57 PM, Juston Li wrote:
pxp will not start correctly until after mei_pxp bind completes and
intel_pxp_init_hw() is called.
Signed-off-by: Juston Li
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i9
On 8/9/2022 4:20 PM, Juston Li wrote:
On Tue, Aug 9, 2022 at 4:10 PM Ceraolo Spurio, Daniele
wrote:
On 8/9/2022 3:57 PM, Juston Li wrote:
pxp will not start correctly until after mei_pxp bind completes and
intel_pxp_init_hw() is called.
Signed-off-by: Juston Li
---
drivers/gpu/drm
On 8/12/2022 12:29 AM, Tvrtko Ursulin wrote:
On 11/08/2022 22:08, Daniele Ceraolo Spurio wrote:
If the GuC CTs are full and we need to stall the request submission
while waiting for space, we save the stalled request and where the stall
occurred; when the CTs have space again we pick up the
On 8/9/2022 5:42 PM, Juston Li wrote:
pxp will not start correctly until after mei_pxp bind completes and
intel_pxp_init_hw() is called.
This fixes a race condition during bootup where we observed a small
window for pxp commands to be sent before mei_pxp bind completed.
Changes since v1:
- c
On 8/19/2022 12:21 AM, Greg Kroah-Hartman wrote:
On Thu, Aug 18, 2022 at 04:02:28PM -0700, Daniele Ceraolo Spurio wrote:
Note that this series includes several mei patches that add support for
sending the HuC loading command via mei-gsc. These patches depend on the
GSC support for DG2 [1], wh
th the commit message updated:
Reviewed-by: Daniele Ceraolo Spurio
Daniele
+
intf->irq = irq_alloc_desc(0);
if (intf->irq < 0) {
drm_err(&i915->drm, "gsc irq error %d\n", intf->irq);
@@ -109,6 +114,7 @@ static void gsc_init_one(struct
On 4/7/2022 5:58 AM, Alexander Usyskin wrote:
Add slow_fw flag to the mei auxiliary device info
to inform the mei driver about slow underlying firmware.
Such firmware will require to use larger operation timeouts.
Signed-off-by: Alexander Usyskin
Signed-off-by: Tomas Winkler
Might be wort
On 4/7/2022 5:58 AM, Alexander Usyskin wrote:
Add slow_fw flag to the gsc device definition
and pass it to mei auxiliary device.
Signed-off-by: Alexander Usyskin
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/gt/intel_gsc.c | 2 ++
1 file changed, 2 insertions
* NB: GuC interface supports 64 bit LRCA even though i915
+* only supports 32 bit currently.
+*/
It's not i915 that only supports 32b, it's the HW.
Assuming that, as you said in the cover letter, this is going to be
squashed before merge and
igned-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
.../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 4 +-
drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h | 15 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 19 +-
.../gpu/drm/i915/gt/uc/intel_guc_submiss
On 4/8/2022 11:03 AM, john.c.harri...@intel.com wrote:
From: John Harrison
Update to the latest GuC firmware release.
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 32
1 file
On 3/21/2022 2:14 PM, Lucas De Marchi wrote:
On Thu, Mar 03, 2022 at 11:30:10PM +0530, Balasubramani Vivekanandan
wrote:
memcpy_from_wc functions in i915_memcpy.c will be removed and replaced
by the implementation in drm_cache.c.
Updated to use the functions provided by drm_cache.c.
v2: Chec
On 4/7/2022 5:58 AM, Alexander Usyskin wrote:
From: Tomas Winkler
DG2 uses different GSC offsets on memory bar
and uses PXP head (HECI1).
Signed-off-by: Alexander Usyskin
Signed-off-by: Tomas Winkler
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/gt
On 4/13/2022 3:57 PM, Ashutosh Dixit wrote:
Client busyness is not available when GuC submission is used. Don't show it
in fdinfo till this is supported by GuC.
GuC does support this, but we don't yet have code in place in i915 to
fetch the data, so this commit message needs a slightly rewo
d as FIXME since the code
isn't working around a bug, just returning early due to a non-supported
feature. IMO better to drop the FIXME tag, but anyway:
Reviewed-by: Daniele Ceraolo Spurio
Daniele
+* till fetching engine busyness is implemented in the GuC submission
backend
On 4/13/2022 12:27 PM, Umesh Nerlige Ramappa wrote:
From: John Harrison
There are some workarounds for DG2 that are implemented in the GuC
firmware. However, the KMD is required to enable these by setting the
appropriate flag as GuC does not know what platform it is running on.
Wa_1601175
.
Wa_16011759253
Wa_14012630569
Wa_14013746162
Signed-off-by: John Harrison
CC: Matt Roper
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 14 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 2 ++
2 files changed, 16 insertions
given that gen11 defaults to execlists submission and that we'd need to
specially enable GuC in CI to cover, I can see how making it a follow-up
makes things simpler, so not a blocker.
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gp
On 4/18/2022 5:07 PM, Daniele Ceraolo Spurio wrote:
From: Tomas Winkler
GSC is a graphics system controller, based on CSE, it provides
a chassis controller for graphics discrete cards, as well as it
supports media protection on selected devices.
mei_gsc binds to a auxiliary devices exposed
On 4/19/2022 6:17 PM, Patchwork wrote:
Project List - Patchwork *Patch Details*
*Series:* GSC support (rev7)
*URL:* https://patchwork.freedesktop.org/series/102160/
*State:*failure
*Details:*
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102160v7/index.html
CI Bug Log
On 4/26/2022 5:26 PM, Daniele Ceraolo Spurio wrote:
The huc_is_authenticated function return is based on our SW tracking of
the HuC auth status. However, around suspend/resume and reset this can
go out of sync with the actual HW state, which is why we use
huc_check_state() to look at the actua
On 4/27/2022 9:55 AM, john.c.harri...@intel.com wrote:
From: John Harrison
First release of GuC for DG2.
Reviewed-by: Daniele Ceraolo Spurio
Daniele
Signed-off-by: John Harrison
CC: Tomasz Mistat
CC: Ramalingam C
CC: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc
On 5/3/2022 5:44 PM, Daniele Ceraolo Spurio wrote:
From: Matthew Brost
The EU priority register must be updated by the GuC rather than the
driver as it is context specific and only the GuC knows which context
is currently executing.
Cc: John Harrison
Cc: Matt Roper
Signed-off-by: Matthew
On 2/15/2022 1:09 AM, Tvrtko Ursulin wrote:
On 15/02/2022 01:11, Daniele Ceraolo Spurio wrote:
Move initialization of submission-related spinlock, lists and workers to
init_early. This fixes an issue where if the GuC init fails we might
still try to get the lock in the context cleanup code.
On 2/18/2022 10:47 AM, Ramalingam C wrote:
From: John Harrison
First release of GuC for DG2.
Signed-off-by: John Harrison
CC: Tomasz Mistat
CC: Ramalingam C
CC: Daniele Ceraolo Spurio
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1
helper functions for context id
mappings to better reflect their purpose and to differentiate from
other registration related helper functions.
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 69
way, so:
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 2 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 8 +---
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers
d in the GuC interface. If I'm
correct, IMO we need to ask the GuC team to add them in, because it
shouldn't be our responsibility to convert from ms to GuC clocks,
considering that the interface is in ms. Not a blocker for this patch.
Reviewed-by: Daniele Ceraolo Spurio
Daniele
+
struct guc_policies {
u32 submission_queue_depth[GUC_MAX_ENGINE_CLASSES];
/* In micro seconds. How much time to allow before DPC processing is
something like "the desc pool is
sized based on the maximum numbers of contexts supported by the GuC, so
define that limit directly".
While at it, also update a kzalloc(sizeof()*count) to be a
kcalloc(count,size).
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
the place where
the return values are actually ignored.
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 45 ---
1 file changed, 28 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/
On 2/17/2022 3:52 PM, john.c.harri...@intel.com wrote:
From: John Harrison
The LRC descriptor was being initialised early on in the context
registration sequence. It could then be determined that the actual
registration needs to be delayed and the descriptor would be wiped
out. This is ineff
: Daniele Ceraolo Spurio
Daniele
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 56 +--
1 file changed, 28 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index aa74ec74194a
and
they're being removed entirely in v70, so:
Reviewed-by: Daniele Ceraolo Spurio
Daniele
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
b/driver
On 2/17/2022 3:52 PM, john.c.harri...@intel.com wrote:
From: John Harrison
Some G2H handlers were reading the context id field from the payload
before checking the payload met the minimum length required.
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
While double-che
:
banned = %d, blocked = %d",
The if statement above checks for !banned, so if we're here we're banned
for sure, no need to print it as if it was conditional. I'd reword it as
something like: "Ignoring reset notification for banned context 0x%04X
...". With that
On 2/23/2022 12:23 PM, John Harrison wrote:
On 2/22/2022 17:12, Ceraolo Spurio, Daniele wrote:
On 2/17/2022 3:52 PM, john.c.harri...@intel.com wrote:
From: John Harrison
The LRC descriptor was being initialised early on in the context
registration sequence. It could then be determined
the place where
the return values are actually ignored.
v2: Move some more splitting from a later patch (and do it correctly).
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 54 +++
1 file c
inefficient, so move the setup to later in the process
after the point of no return.
v2: Move some split changes into the split patch (and do them
correctly).
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 6
: John Harrison
|Reviewed-by: Daniele Ceraolo Spurio
Daniele|
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_sub
ed-off-by: John Harrison
I seem to have confused patchwork by doing a cut & paste of my r-b from
a different review, so here it is again:
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletio
On 2/28/2022 9:42 AM, Matt Roper wrote:
From: Daniele Ceraolo Spurio
Tell GuC that CCS is enabled by setting a bit in its ADS.
Cc: Vinay Belgaumkar
Original-author: Michel Thierry
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_regs.
On 2/28/2022 9:42 AM, Matt Roper wrote:
From: Matthew Brost
A different emit breadcrumbs ring programming is required for compute /
render and we don't have UMD user so just reject parallel submission for
these engine classes.
Signed-off-by: Matthew Brost
Signed-off-by: Matt Roper
Exclu
wa_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE);
These 2 WAs are also implemented for DG2 (with different IDs). Are you
planning to move them over to this function as a follow up?
All the WA implementations match the specs, so as long as there is a
plan for D
esets are happening even if they are being ignored).
v2: Better wording for the message (review feedback from Tvrtko).
v3: Fix rebase issue (review feedback from Daniele).
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/
On 3/1/2022 3:15 PM, Matt Roper wrote:
From: Daniele Ceraolo Spurio
Tell GuC that CCS is enabled by setting a bit in its ADS.
It's a mask, not a bit.
Reviewed-by: Daniele Ceraolo Spurio
Daniele
Cc: Vinay Belgaumkar
Original-author: Michel Thierry
Signed-off-by: Daniele Ce
On 8/16/2022 1:28 PM, john.c.harri...@intel.com wrote:
From: John Harrison
There was a misunderstanding in how firmware file compatibility should
be managed within i915. This has been clarified as:
i915 must support all existing firmware releases forever
new minor firmware releases sho
On 8/23/2022 2:15 PM, Juston Li wrote:
On Fri, Aug 19, 2022 at 4:53 AM Andrzej Hajda wrote:
On 18.08.2022 19:42, Juston Li wrote:
pxp will not start correctly until after mei_pxp bind completes and
intel_pxp_init_hw() is called.
Wait for the bind to complete before proceeding with startup.
On 8/25/2022 8:05 PM, john.c.harri...@intel.com wrote:
From: John Harrison
There was a misunderstanding in how firmware file compatibility should
be managed within i915. This has been clarified as:
i915 must support all existing firmware releases forever
new minor firmware releases sho
On 8/26/2022 9:40 AM, John Harrison wrote:
On 8/26/2022 09:35, Ceraolo Spurio, Daniele wrote:
On 8/25/2022 8:05 PM, john.c.harri...@intel.com wrote:
From: John Harrison
There was a misunderstanding in how firmware file compatibility should
be managed within i915. This has been clarified
On 8/25/2022 8:05 PM, john.c.harri...@intel.com wrote:
From: John Harrison
With the move to un-versioned filenames, it becomes more difficult to
know exactly what version of a given firmware is being used. So add
the patch level version number to the debugfs output.
Also, support matching b
On 8/6/2022 5:26 AM, Tomas Winkler wrote:
struct mei_aux_device is an interface structure
requires proper documenation.
Signed-off-by: Tomas Winkler
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
include/linux/mei_aux.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a
: Vitaly Lubart
Signed-off-by: Tomas Winkler
Signed-off-by: Alexander Usyskin
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/gt/intel_gsc.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c
b/drivers/gpu/drm/i915
}
+
+
schedule_timeout_interruptible(msecs_to_jiffies(polling_timeout));
+ }
IMO this loop could have used a couple of comments to make it easier to
understand what's going on with the various waits and timeouts. Not a
blocker.
Reviewed-by: Daniele Ceraolo S
On 8/6/2022 5:26 AM, Tomas Winkler wrote:
From: Alexander Usyskin
Wait for reset work to complete before initiating
stop reset flow sequence.
Signed-off-by: Alexander Usyskin
Signed-off-by: Tomas Winkler
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/misc/mei/init.c | 2
NT_INTR_RECEIVED,
+ dev->timeouts.pgi);
Shouldn't this be timeouts.d0i3, given that it replaces
mei_secs_to_jiffies(MEI_D0I3_TIMEOUT)?
Apart from this, all the other replacements look ok, so with this fixed:
Reviewed-by: Daniele Ceraolo Spurio
Daniele
mutex_lock(&dev-
On 8/6/2022 5:26 AM, Tomas Winkler wrote:
From: Vitaly Lubart
Exported common mkhi definitions from bus-fixup.c into a separate
header file mkhi.h for other driver usage.
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
Signed-off-by: Alexander Usyskin
---
drivers/misc/mei/bus
date aside, this is:
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/misc/mei/mkhi.h | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/misc/mei/mkhi.h b/drivers/misc/mei/mkhi.h
index 27a9b476904e..056b76e73d40 100644
--- a/drivers/misc/mei
On 8/6/2022 5:26 AM, Tomas Winkler wrote:
1. Retrieve extended operational memory physical pointers from the
auxiliary device info.
2. Setup memory registers.
3. Notify firmware that the memory is ready by sending the memory
ready command.
4. Disable PXP device if GSC is not in PXP mod
On 8/6/2022 5:26 AM, Tomas Winkler wrote:
From: Vitaly Lubart
Added transition to PXP mode in resume flow.
CC: Daniele Ceraolo Spurio
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
Signed-off-by: Alexander Usyskin
Reviewed-by: Daniele Ceraolo Spurio
Daniele
could be monitored
to ensure that pxp is in the ready state.
CC: Vitaly Lubart
Signed-off-by: Tomas Winkler
Signed-off-by: Alexander Usyskin
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/misc/mei/debugfs.c | 17 +
1 file changed, 17 insertions(+)
diff --git a
On 8/29/2022 10:02 AM, Matt Roper wrote:
Xe_LPM+ platforms have "standalone media." I.e., the media unit is
designed as an additional GT with its own engine list, GuC, forcewake,
etc. Let's allow platforms to include media GTs in their device info.
Cc: Aravind Iddamsetty
Signed-off-by: Mat
On 8/29/2022 10:02 AM, Matt Roper wrote:
When we hook up interrupts (in the next patch), interrupts for the media
GT are still processed as part of the primary GT's interrupt flow. As
such, we should share the same IRQ lock with the primary GT. Let's
convert gt->irq_lock into a pointer and j
media GT instance as well.
Bspec: 45605
Cc: Anusha Srivatsa
Signed-off-by: Matt Roper
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 19 +++
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++
drivers/gpu/drm/i915/gt/intel_sa_media.c |
solution that uses the same
firmware client
and have no need in special initialization.
makes sense. Could use a comment, but anyway:
Reviewed-by: Daniele Ceraolo Spurio
Daniele
On 8/26/2022 6:17 PM, john.c.harri...@intel.com wrote:
From: John Harrison
With the move to un-versioned filenames, it becomes more difficult to
know exactly what version of a given firmware is being used. So add
the patch level version number to the debugfs output.
Also, support matching b
On 8/26/2022 6:17 PM, john.c.harri...@intel.com wrote:
From: John Harrison
Going forwards, the intention is for GuC firmware files to be named
for their major version only and HuC firmware files to have no version
number in the name at all. This patch adds those entries for DG1/2 and
ADL-P/S
On 9/6/2022 1:29 PM, Ceraolo Spurio, Daniele wrote:
On 8/26/2022 6:17 PM, john.c.harri...@intel.com wrote:
From: John Harrison
Going forwards, the intention is for GuC firmware files to be named
for their major version only and HuC firmware files to have no version
number in the name at
On 9/7/2022 8:57 AM, Tomas Winkler wrote:
struct mei_aux_device is an interface structure
requires proper documenation.
Signed-off-by: Tomas Winkler
This is unchanged from the previously reviewed rev, so this still applies:
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
include
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