the ability to configure the GPU "idle" frequecy
using the same method that already exists for minimum and maximum
frequencies.
In addition, parking the idle frequency may reduce spool up latencies
on GPU workloads.
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/i915_sy
nal code"). What got merged fails to do cdclk init/uninit on
> ehl.
Good catch!
Reviewed-by: Bob Paauwe
>
> Fixes: 39564ae86d51 ("drm/i915/ehl: Inherit Ice Lake conditional code")
> Cc: José Roberto de Souza
> Cc: Lucas De Marchi
> Cc: Bob Paauwe
> Cc: Rodri
On Mon, 15 Apr 2019 17:33:30 -0700
Vanshidhar Konda wrote:
> On Mon, Apr 15, 2019 at 04:05:26PM -0700, Bob Paauwe wrote:
> >There are real-time use cases where having deterministic CPU processes
> >can be more important than GPU power/performance. Parking the GPU at a
> >
t; (combo port A external usage).
>
> - DPLL4 cannot be enabled when DC5 or DC6 are enabled.
>
> - The DPLL4 enable, lock, power enabled, and power state are connected
> to the MGPLL1_ENABLE register.
>
> v2: (suggestions from Bob Paauwe)
> - Rework ehl_get_dpll() fun
On Tue, 16 Apr 2019 16:56:26 +0100
Chris Wilson wrote:
> Quoting Bob Paauwe (2019-04-16 00:05:26)
> > There are real-time use cases where having deterministic CPU processes
> > can be more important than GPU power/performance. Parking the GPU at a
> > specific freqency by
On Fri, 15 Jul 2016 14:59:02 +0100
Lionel Landwerlin wrote:
> From: Bob Paauwe
>
> The i915 driver is now using atomic properties and atomic commit
> to handle the legacy set gamma IOCTL. However, if the driver is
> configured without atomic (nuclear_pageflip = false), it won
On Mon, 18 Jul 2016 09:14:56 +0200
Maarten Lankhorst wrote:
> Hey,
>
> Op 15-07-16 om 12:51 schreef Lionel Landwerlin:
> > From: Bob Paauwe
> >
> > The i915 driver is now using atomic properties and atomic commit
> > to handle the legacy set gamma
gt_plane, v2.")
> Cc: Maarten Lankhorst
> Signed-off-by: Matt Roper
Reviewed-by: Bob Paauwe
> ---
> lib/igt_kms.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/lib/igt_kms.c b/lib/igt_kms.c
> index 7d7a53c..ed91688 100644
> --- a/lib/ig
7353c
Author: Daniel Vetter
Date: Wed Jul 27 13:17:38 2016 +0200
lib/debugs: nuke igt_crc_equal again
for this test only and makes the igt_crc_equal function a local
function.
Signed-off-by: Bob Paauwe
---
tests/kms_pipe_color.c | 13 -
1 file changed, 12 insertions(
and power up the DSI regulator when initializing a MIPI display.
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/i915_reg.h | 8
drivers/gpu/drm/i915/intel_dsi.c | 13 +
2 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm
se on current drm-tip
Signed-off-by: Bob Paauwe
CC: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c | 7 ++-
drivers/gpu/drm/i915/i915_drv.h | 8 +---
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c
ppgtt (both 3-lvl and 4-lvl) so name cap
define appropriately (Chris)
v9: rebase on latest
v10: fix missed vgpu change of FULL_48BIT to FULL in CAPS define (Bob)
v11: rebase on current drm-tip
Signed-off-by: Bob Paauwe
CC: Rodrigo Vivi
CC: Michel Thierry
CC: Chris Wilson
---
drivers/g
We no longer need to differentiate between 4LVL and FULL ppgtt as
the number of bits in the address range provides that information now.
Signed-off-by: Bob Paauwe
CC: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 2 --
drivers/gpu/drm/i915/i915_pci.c | 4
On Thu, 7 Feb 2019 16:41:58 +
Chris Wilson wrote:
> Quoting Bob Paauwe (2019-02-07 16:29:53)
> > With the address range being specified for each platform, we can use
> > that instead of the .ppgtt enum to handle the differences between
> > 3 level and 4 level PPGTT. In
It's not just GEN9 platforms that allow for pipes to be disabled via
the DFSM register, but all later platforms as well.
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/intel_device_info.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm
It's not just GEN9 platforms that allow for pipes to be disabled via
the DFSM register, but all later platforms as well.
v2: drop pointless parentheses (Ville)
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/intel_device_info.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
3: Rebased.
v12:
Reviewed-by: Ville Syrjälä
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +
drivers/gpu/drm/i915/display/intel_sprite.c | 3 +++
drivers/gpu/drm/i915/i915_reg.h | 2 +-
3 files changed, 9
Chris,
Any thoughts on how I can best address your comment on this patch?
Bob
On Thu, 7 Feb 2019 11:13:15 -0800
Bob Paauwe wrote:
> On Thu, 7 Feb 2019 16:41:58 +
> Chris Wilson wrote:
>
> > Quoting Bob Paauwe (2019-02-07 16:29:53)
> > > With the address range
that into a common routine.
> > >
> > > Signed-off-by: Chris Wilson
> > > Cc: Bob Paauwe
> > > Cc: Matthew Auld
> > > Cc: Joonas Lahtinen
> >
> > Reviewed-by: Rodrigo Vivi
>
> I've pushed this series so that 36 bits should be
On Fri, 15 Mar 2019 10:01:51 -0700
Rodrigo Vivi wrote:
> On Fri, Mar 15, 2019 at 09:55:47AM -0700, Bob Paauwe wrote:
> > On Fri, 15 Mar 2019 09:09:11 +
> > Chris Wilson wrote:
> >
> > > Quoting Rodrigo Vivi (2019-03-14 22:53:44)
> > > > On Th
patch cc'ing the appropriated list and maintainers for
> > proper ack.
> > v3: (Rodrigo): - Removed .num_pipes = 3 that is coming since
> > GEN&_FEATURES.
> > - Added ppgtt type and size after rework from Bob and
>
On Fri, 15 Mar 2019 10:57:11 -0700
Rodrigo Vivi wrote:
> From: Anusha Srivatsa
>
> EHL uses the same firmware as ICL.
Reviewed-by: Bob Paauwe
>
> Cc: Bob Paauwe
> Signed-off-by: Anusha Srivatsa
> Signed-off-by: Rodrigo Vivi
> Reviewed-by: Lucas De
Unlike ICL, all of the output ports are combo phys so just return
true in intel_port_is_combophy for all EHL ports to indicate that.
v2: Return false in intel_port_is_tc since no EHL ports are TC. (Jose)
Cc: Jose Souza
Signed-off-by: Bob Paauwe
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm
Add XYUV to the list of DRM Formats to test.
Also fix the byte order for the format.
Signed-off-by: Bob Paauwe
---
lib/igt_color_encoding.c | 1 +
lib/igt_fb.c | 6 +++---
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/lib/igt_color_encoding.c b/lib
3: Rebased.
Added format to ICL format lists.
v12:
Reviewed-by: Ville Syrjälä
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Bob Paauwe
---
This has been updated to support GEN11 along with rebasing it to
the latest drm-tip. A patch to igt has also been posted that gives
igt the
d-by: Matt Roper
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +
drivers/gpu/drm/i915/display/intel_sprite.c | 8
drivers/gpu/drm/i915/i915_reg.h | 2 +-
3 files changed, 14 insertions(+), 1 deletio
Test-with: <20200407215146.5331-1-bob.j.paa...@intel.com>
Stanislav Lisovskiy (1):
drm/i915: Adding YUV444 packed format support for skl+ (V15)
drivers/gpu/drm/i915/display/intel_display.c | 5 +
drivers/gpu/drm/i915/display/intel_sprite.c | 8
drivers/gpu/drm/i915/i915_reg.h
3: Rebased.
Added format to ICL format lists.
v12:
Reviewed-by: Ville Syrjälä
Reviewed-by: Matt Roper
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +
drivers/gpu/drm/i915/display/intel_sprite.c | 5 +
drivers/gp
Add XYUV to the list of DRM Formats to test.
Also fix the byte order for the format.
Signed-off-by: Bob Paauwe
Reviewed-by: Uma Shankar
---
lib/igt_color_encoding.c | 1 +
lib/igt_fb.c | 6 +++---
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/lib
Test-with: 20200127192859.20029-1-bob.j.paa...@intel.com
Stanislav Lisovskiy (1):
drm/i915: Adding YUV444 packed format support for skl+ (V14)
drivers/gpu/drm/i915/display/intel_display.c | 5 +
drivers/gpu/drm/i915/display/intel_sprite.c | 6 ++
drivers/gpu/drm/i915/i915_reg.h
3: Rebased.
Added format to ICL format lists.
V14: Added format to TGL format lists.
Rebased.
v12:
Reviewed-by: Ville Syrjälä
Reviewed-by: Matt Roper
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +
drivers/gp
Test-with: 20200127192859.20029-1-bob.j.paa...@intel.com
Stanislav Lisovskiy (1):
drm/i915: Adding YUV444 packed format support for skl+ (V15)
drivers/gpu/drm/i915/display/intel_display.c | 5 +
drivers/gpu/drm/i915/display/intel_sprite.c | 8
drivers/gpu/drm/i915/i915_reg.h
d-by: Matt Roper
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +
drivers/gpu/drm/i915/display/intel_sprite.c | 8
drivers/gpu/drm/i915/i915_reg.h | 2 +-
3 files changed, 14 insertions(+), 1 deletio
sues/454
> [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46
> [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
> [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
> [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
> [i915#677]: https
and power up the DSI regulator when initializing a MIPI display.
v2: rebase on current drm-intel-nightly
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/i915_reg.h | 8
drivers/gpu/drm/i915/intel_dsi.c | 15 +++
2 files changed, 23 insertions(+)
diff --git a/drivers
e, Bob J
> Sent: Thursday, August 4, 2016 11:16 AM
> To: isg-gms ; intel-gfx
>
> Cc: Paauwe, Bob J
> Subject: [isg-gms] [PATCH] drm/i915/bxt: Bring MIPI out of reset
>
> and power up the DSI regulator when initializing a MIPI display.
>
> Signed-off-by: Bob Pa
On Fri, 19 Aug 2016 13:04:54 +0300
Jani Nikula wrote:
> On Sat, 06 Aug 2016, Bob Paauwe wrote:
> > On Fri, 5 Aug 2016 15:23:23 -0700
> > "Xiong, James" wrote:
> >
> >> Reviewed-by James Xiong
> >
> > Merged to gold. Thanks for the re
explised in setting vm.total to 1ULL << 32 (Rodrigo)
Gen 7 is 31 bits, not 32 (Chris)
v5: Mock device is 64b(63b) not 48b (Chris)
v6: Rebase to latest drm-tip (Bob)
v7: Combine common code for gen6/gen8 ppgtt create (Chris)
Improve comment on device info field (Chris)
Signed-off-by: Bob Paau
We no longer need to differentiate between 4LVL and FULL ppgtt as
the number of bits in the address range provides that information now.
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/i915_drv.h | 2 --
drivers/gpu/drm/i915/i915_pci.c | 4 ++--
drivers/gpu/drm/i915
n now remove the HAS_FULL_PPGTT macro and the devcie
info ppgtt type.
However, there are still a few places where GEN 6's aliasing ppgtt
differences matter. For those cases, it makes just as much sense to
check if we're running on GEN 6 as it does to check a device info flag.
Signed-off
We no longer need to differentiate between 4LVL and FULL ppgtt as
the number of bits in the address range provides that information now.
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/i915_drv.h | 2 --
drivers/gpu/drm/i915/i915_pci.c | 4 ++--
drivers/gpu/drm/i915
ppgtt (both 3-lvl and 4-lvl) so name cap
define appropriately (Chris)
Signed-off-by: Bob Paauwe
CC: Rodrigo Vivi
CC: Michel Thierry
CC: Chris Wilson
---
drivers/gpu/drm/i915/gvt/vgpu.c | 2 +-
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/dr
ff-by: Bob Paauwe
CC: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c | 7 ++-
drivers/gpu/drm/i915/i915_drv.h | 8 +---
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm
We no longer need to differentiate between 4LVL and FULL ppgtt as
the number of bits in the address range provides that information now.
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/i915_drv.h | 2 --
drivers/gpu/drm/i915/i915_pci.c | 4 ++--
drivers/gpu/drm/i915
ppgtt (both 3-lvl and 4-lvl) so name cap
define appropriately (Chris)
v9: rebase on latest
Signed-off-by: Bob Paauwe
CC: Rodrigo Vivi
CC: Michel Thierry
CC: Chris Wilson
---
drivers/gpu/drm/i915/gvt/vgpu.c | 2 +-
drivers/gpu/drm/i915/i915_drv.c | 2 +-
d
ff-by: Bob Paauwe
CC: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c | 7 ++-
drivers/gpu/drm/i915/i915_drv.h | 8 +---
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm
ff-by: Bob Paauwe
CC: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c | 7 ++-
drivers/gpu/drm/i915/i915_drv.h | 8 +---
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm
We no longer need to differentiate between 4LVL and FULL ppgtt as
the number of bits in the address range provides that information now.
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/i915_drv.h | 2 --
drivers/gpu/drm/i915/i915_pci.c | 4 ++--
drivers/gpu/drm/i915
ppgtt (both 3-lvl and 4-lvl) so name cap
define appropriately (Chris)
v9: rebase on latest
v10: fix missed vgpu change of FULL_48BIT to FULL in CAPS define (Bob)
Signed-off-by: Bob Paauwe
CC: Rodrigo Vivi
CC: Michel Thierry
CC: Chris Wilson
---
drivers/gpu/drm/i915/gvt/
We no longer need to differentiate between 4LVL and FULL ppgtt as
the number of bits in the address range provides that information now.
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/i915_drv.h | 2 --
drivers/gpu/drm/i915/i915_pci.c | 4 ++--
drivers/gpu/drm/i915
ppgtt (both 3-lvl and 4-lvl) so name cap
define appropriately (Chris)
v9: rebase on latest
v10: fix missed vgpu change of FULL_48BIT to FULL in CAPS define (Bob)
Signed-off-by: Bob Paauwe
CC: Rodrigo Vivi
CC: Michel Thierry
CC: Chris Wilson
---
drivers/gpu/drm/i915/gvt/
ff-by: Bob Paauwe
CC: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c | 7 ++-
drivers/gpu/drm/i915/i915_drv.h | 8 +---
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm
rm-tip (Bob)
Signed-off-by: Bob Paauwe
CC: Rodrigo Vivi
CC: Michel Thierry
CC: Chris Wilson
---
drivers/gpu/drm/i915/gvt/vgpu.c | 2 +-
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/dr
explised in setting vm.total to 1ULL << 32 (Rodrigo)
Gen 7 is 31 bits, not 32 (Chris)
v5: Mock device is 64b(63b) not 48b (Chris)
v6: Rebase to latest drm-tip (Bob)
v7: Combine common code for gen6/gen8 ppgtt create (Chris)
Improve comment on device info field (Chris)
Signed-off-by: Bob Paau
the actual
address range. This gives us more flexibility and will work for
cases where we have platforms with different address ranges but
share the same page walk levels.
Signed-off-by: Bob Paauwe
CC: Rodrigo Vivi
CC: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.h | 4 +
On Fri, 31 Aug 2018 16:51:29 +0100
Chris Wilson wrote:
> Quoting Bob Paauwe (2018-08-31 16:47:04)
> > For ppgtt, what we're really interested in is the number of page
> > walk levels for each platform. Rename the device info fields to
> > reflect this:
&g
On Fri, 31 Aug 2018 13:21:40 -0700
Rodrigo Vivi wrote:
> On Fri, Aug 31, 2018 at 04:51:29PM +0100, Chris Wilson wrote:
> > Quoting Bob Paauwe (2018-08-31 16:47:04)
> > > For ppgtt, what we're really interested in is the number of page
> > > walk levels for each
field that specifies the number of
bits to prepare for cases where the range is not 32 or 48 bits.
v2: keep USES_FULL_PPGTT() unchanged (Chris)
Signed-off-by: Bob Paauwe
CC: Rodrigo Vivi
CC: Michel Thierry
CC: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu
On Thu, 6 Sep 2018 21:08:33 +0100
Chris Wilson wrote:
> Quoting Bob Paauwe (2018-09-06 21:04:09)
> > @@ -1647,9 +1647,10 @@ static struct i915_hw_ppgtt
> > *gen8_ppgtt_create(struct drm_i915_private *i915)
> > ppgtt->vm.i915 = i915;
> > ppgtt-
On Thu, 6 Sep 2018 14:10:35 -0700
Rodrigo Vivi wrote:
> On Thu, Sep 06, 2018 at 01:04:09PM -0700, Bob Paauwe wrote:
> > 48 bit ppgtt device configuration is really just extended address
> > range full ppgtt and may actually be something other than 48 bits.
> >
> > C
(Rodrigo/Bob)
Signed-off-by: Bob Paauwe
CC: Rodrigo Vivi
CC: Michel Thierry
CC: Chris Wilson
Additional work to rename 48bit to 4 level
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/gvt/vgpu.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu
On Mon, 10 Sep 2018 10:32:42 -0700
Rodrigo Vivi wrote:
> On Mon, Sep 10, 2018 at 10:12:25AM -0700, Bob Paauwe wrote:
> 1;5202;0c> 48 bit ppgtt device configuration is really just extended address
> > range full ppgtt and may actually be something other than 48 bits.
On Mon, 10 Sep 2018 20:56:51 +0100
Chris Wilson wrote:
> Quoting Bob Paauwe (2018-09-10 18:12:25)
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c
> > b/drivers/gpu/drm/i915/i915_pci.c
> > index d6f7b9fe1d26..e0619952ff52 100644
> > --- a/drivers/gpu/drm/i915/i915_
)
Rename functions/defines/comments from 48bit to 4lvl (Rodrigo/Bob)
v4: Rename FULL_4LVL_PPGTT to simply 4LVL_PPGTT (Rodrigo)
Be explised in setting vm.total to 1ULL << 32 (Rodrigo)
Gen 7 is 31 bits, not 32 (Chris)
Signed-off-by: Bob Paauwe
CC: Rodrigo Vivi
CC: Michel Thier
On Wed, 12 Sep 2018 17:10:58 +0100
Chris Wilson wrote:
> Quoting Bob Paauwe (2018-09-12 17:04:30)
> > diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> > b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> > index 43ed8b28aeaa..33d7225edbbb 100644
> >
On Thu, 13 Sep 2018 20:05:54 +0300
Ville Syrjälä wrote:
> On Thu, Sep 13, 2018 at 10:02:57AM -0700, Bob Paauwe wrote:
> > On Wed, 12 Sep 2018 17:10:58 +0100
> > Chris Wilson wrote:
> >
> > > Quoting Bob Paauwe (2018-09-12 17:04:30)
> > > > d
On Thu, 13 Sep 2018 20:22:14 +0300
Ville Syrjälä wrote:
> On Thu, Sep 13, 2018 at 10:12:06AM -0700, Bob Paauwe wrote:
> > On Thu, 13 Sep 2018 20:05:54 +0300
> > Ville Syrjälä wrote:
> >
> > > On Thu, Sep 13, 2018 at 10:02:57AM -0700, Bob Paauwe wrote:
> &
s null.
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/intel_fbdev.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c
b/drivers/gpu/drm/i915/intel_fbdev.c
index b75484a..9b14c13 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drive
On Tue, 28 Jun 2016 16:47:28 +0100
Chris Wilson wrote:
> On Tue, Jun 28, 2016 at 08:42:01AM -0700, Bob Paauwe wrote:
> > When fbdev emulation is disabled it is not a good idea to call into
> > the core fb_set_suspend() function as this will cause suspend and
> > resume to
h but didn't want to re-write the entire test program
to make handle these cases more elegantly. Other ideas welcome.
Bob Paauwe (2):
igt/pm_rps: current freq < user specified min is not a fail (v2)
igt/pm_rps: Add checks for freq = idle (RPn) in specific cases.
tests/
to the "idle" or RPn frequency. Update the
pm_rps tests to reflect that droping below the user specified minimum
is no longer considered a failure.
v2: Add check RPn <= current freq. (Me)
Signed-off-by: Bob Paauwe
---
tests/pm_rps.c | 8
1 file changed, 4 insertions(+)
config-min-max-idle subtest make
use of the second check routine to verify that the frequency drops
to RPn instead of simply <= user min frequency. For all other
subtests, use the original check routines for both checks.
Signed-off-by: Bob Paauwe
---
tests/
On Tue, 1 Dec 2015 15:56:55 +0200
Imre Deak wrote:
> On ma, 2015-11-30 at 16:23 -0800, Bob Paauwe wrote:
> > Now that the frequency can drop below the user specified minimum when
> > the gpu is idle, add some checking to verify that it really does drop
> > down to the RPn
to the "idle" or RPn frequency. Update the
pm_rps tests to reflect that droping below the user specified minimum
is no longer considered a failure.
v2: Add check RPn <= current freq. (Me)
v3: Use RPn instead of MIN frequency in idle check (Imre)
Signed-off-by: Bob Paauwe
---
tests
On Tue, 1 Dec 2015 19:43:05 +0200
Imre Deak wrote:
> On ti, 2015-12-01 at 09:22 -0800, Bob Paauwe wrote:
> > On Tue, 1 Dec 2015 15:56:55 +0200
> > Imre Deak wrote:
> >
> > > On ma, 2015-11-30 at 16:23 -0800, Bob Paauwe wrote:
> > > > Now that the f
On Fri, 4 Dec 2015 17:22:11 +0200
Imre Deak wrote:
> On to, 2015-12-03 at 16:43 -0800, Bob Paauwe wrote:
> > On Tue, 1 Dec 2015 19:43:05 +0200
> > Imre Deak wrote:
> >
> > > On ti, 2015-12-01 at 09:22 -0800, Bob Paauwe wrote:
> > > > On Tue, 1 Dec 20
On Fri, 4 Dec 2015 22:58:50 +0200
Imre Deak wrote:
> On Fri, 2015-12-04 at 10:37 -0800, Bob Paauwe wrote:
> > On Fri, 4 Dec 2015 17:22:11 +0200
> > Imre Deak wrote:
> > [...]
> > > > With the BIOS setting corrected, the driver started disabling the
> > &g
On Mon, 7 Dec 2015 17:00:20 +0200
Imre Deak wrote:
> On pe, 2015-12-04 at 14:41 -0800, Bob Paauwe wrote:
> > On Fri, 4 Dec 2015 22:58:50 +0200
> > Imre Deak wrote:
> > [...]
> > So we want the policy to be that we'll only drop below min to idle
> > when
&g
uency.
Signed-off-by: Bob Paauwe
---
tests/pm_rps.c | 4
1 file changed, 4 insertions(+)
diff --git a/tests/pm_rps.c b/tests/pm_rps.c
index 9d054fd..9f752f8 100644
--- a/tests/pm_rps.c
+++ b/tests/pm_rps.c
@@ -388,10 +388,14 @@ static void min_max_config(void (*check)(void), bool
loa
) for either DBI/command mode or
when using dual link.
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/intel_dsi_pll.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c
b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 56eff60..9edc57e 1
On Sat, 19 Nov 2016 11:20:56 +0100
David Weinehall wrote:
> On Fri, Nov 18, 2016 at 02:11:56PM -0800, Bob Paauwe wrote:
> > For a single link (channel) DSI panel we want to use a larger divider
> > and keep the clock rate down to save power when in DPI/video mode. However
> &
For BXT, there is only one bit that enables/disables dual-link mode
and not different bits depending on which pipe is being used.
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/intel_dsi.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915
I currently have this same patch in my tree (well with the two changes
below) and have been testing it so with the changes.
Reviewed-by: Bob Paauwe
Tested-by: Bob Paauwe
On Wed, 7 Dec 2016 20:32:18 +0530 Vidya Srinivas
wrote:
> Currently the backlight controller is taken as 0. It needs
if the crtc has audio is enabled. Otherwise, when the first atomic
modeset happens it will warn when trying to drop the audio power
domain.
v2: move this to get_crtc_power_domains to be consistent with other
power domain setup (Ville)
Signed-off-by: Bob Paauwe
Cc: Ville Syrjälä
On Wed, 13 Apr 2016 21:27:17 +0300
Ville Syrjälä wrote:
> On Wed, Apr 13, 2016 at 11:19:20AM -0700, Bob Paauwe wrote:
> > On Wed, 13 Apr 2016 11:59:43 +0300
> > Ville Syrjälä wrote:
> >
> > > On Tue, Apr 12, 2016 at 03:52:48PM -0700, Bob Paauwe wrote:
&g
that removes a redundant
> uninit/init call during system suspend/resume on BXT.
>
> No functional change.
Reviewed-by: Bob Paauwe
>
> CC: Paulo Zanoni
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/i915_drv.c | 83
> ++
> +}
> +
> +void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv)
> +{
> + u32 val;
> +
> + val = I915_READ(DC_STATE_EN) & gen9_dc_mask(dev_priv);
> +
> + DRM_DEBUG_KMS("Resetting DC state tracking from %02x to %02x\n",
> +
ed-off-by: Imre Deak
Reviewed-by: Bob Paauwe
> ---
> drivers/gpu/drm/i915/i915_drv.c | 3 +++
> drivers/gpu/drm/i915/intel_drv.h| 1 +
> drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
> 3 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drive
On Wed, 20 Apr 2016 20:27:55 +0300
Imre Deak wrote:
> Atm, we run the BSpec display core uninit/init sequences twice during
> system suspend/resume. While this shouldn't cause any problem, it's
> redundant, so get rid of the duplicate call.
>
> Signed-off-by: Imre Deak
t;
> /* init WOPCM */
> - I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);
> + if (IS_BROXTON(dev))
> + I915_WRITE(GUC_WOPCM_SIZE, BXT_GUC_WOPCM_SIZE_VALUE);
> + else
> + I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE
ities are needed to set a
mode.
The solution is to add a call to intel_dp_detect_dpcd() in the code
path for forced on DP connectors.
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/intel_dp.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gp
ail:0 fail:0 skip:34
> snb-x220ttotal:196 pass:161 dwarn:0 dfail:0 fail:2 skip:33
>
> Results at /archive/results/CI_IGT_test/Patchwork_1778/
>
> 38b47023a604068e2a222ac166f5f8ef7d56e352 drm-intel-nightly:
> 2016y-04m-01d-12h-04m-08s UTC integration mani
tomic version of the properties.
Until the driver is full atomic, make sure we update the non-atomic
version of the properties.
igt-testcase: kms_pipe_color / legacy-gamma-reset-pipeX
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/intel_display.c | 38 +++-
1
same way and have two code paths for querying the
properties.
This patch is really a temporary fix until we move to
nuclear_pageflip=true as the default/only mode for the i915 driver.
Bob
>
> On 08/04/16 17:26, Bob Paauwe wrote:
> > The i915 driver is now using atomic properties a
ues stored in the crtc object.
>
> Cc: Maarten Lankhorst
> Cc: Bob Paauwe
> Cc:
> Signed-off-by: Lionel Landwerlin
> ---
> drivers/gpu/drm/drm_atomic_helper.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_atomic_helper.c
>
ues stored in the crtc object.
>
> v2: Update non atomic values only if commit succeeds (Bob Paauwe)
>
> v3: Do not access crtc_state after commit, use crtc->state (Maarten
> Lankhorst)
>
Reviewed-by: Bob Paauwe
Tested-by; Bob Paauwe
> Cc: Maarten Lankhorst
&g
When testing multple outputs, make sure to set the gamma values before
testing the output. Otherwise we're testing using the gamma values
that were reset after last output was tested. Without this, the first
output passes, but each output after that will fail.
Signed-off-by: Bob P
if the crtc has audio is enabled. Otherwise, when the first atomic
modeset happens it will warn when trying to drop the audio power
domain.
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/intel_display.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915
On Wed, 13 Apr 2016 11:59:43 +0300
Ville Syrjälä wrote:
> On Tue, Apr 12, 2016 at 03:52:48PM -0700, Bob Paauwe wrote:
> > if the crtc has audio is enabled. Otherwise, when the first atomic
> > modeset happens it will warn when trying to drop the audio power
> > domain.
&
igned-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/intel_display.c | 39 +++-
1 file changed, 38 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 5155efb6..a97bbff 100644
--- a/drivers/gpu/drm
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