On Mon, Feb 17, 2014 at 12:04:19PM -0800, Ben Widawsky wrote:
> On Thu, Feb 06, 2014 at 11:54:44AM -0200, Rodrigo Vivi wrote:
> > On Wed, Jan 29, 2014 at 2:25 AM, Ben Widawsky
> > wrote:
> > > It is tested and looking fairly stable now, so turn it on. It wasn't
&
Introduced:
commit b8a5ff8d7c676a04e0da5ec16bb068dd39459042
Author: Jeff McGee
Date: Tue Feb 4 11:37:01 2014 -0600
drm/i915: Update rps interrupt limits
Cc: Jeff McGee
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_sysfs.c | 20 ++--
1 file changed, 10
fails, the later is likely invalid.
Having a bit more confidence in my understanding of how things work, I
now feel it's better to have clear, readable, code than to try to skip
over this one operation in an unusual case.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_pm.c
of "hw_max" required a bit of interactivity.
Cc: Jeff McGee
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_debugfs.c | 26
drivers/gpu/drm/i915/i915_drv.h | 31 +++---
drivers/gpu/drm/i915/i915_irq.c | 24
drivers/gpu/drm/i915/
, I wanted to make it a separate patch for
the bisectable 'just-in-case'
Cc: Jeff McGee
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_sysfs.c | 20 +---
1 file changed, 9 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c
b/drive
s earlier fix around reset into gen8 with a cleanup
8-9: Enable RPS
10-11: Enable RC6
Thanks to Ken for giving this a quick test and allowing me to work from
home :-)
Ben Widawsky (11):
drm/i915: Reorganize the overclock code
drm/i915: Fix coding style for RPS
drm/i915: Rename and comment all t
x
Cc: Kristen Carlson Accardi
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem.c | 12
drivers/gpu/drm/i915/intel_display.c | 5 +
drivers/gpu/drm/i915/intel_pm.c | 2 +-
3 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i91
It is tested and looking fairly stable now, so turn it on. It wasn't
intentionally turned off originally :P
Reviewed-by: Rodrigo Vivi
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm
McGee
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_sysfs.c | 37 -
drivers/gpu/drm/i915/intel_pm.c | 29 +++--
2 files changed, 27 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c
b/driver
dling the interrupts. Since the code is
currently disabled (and broken) I think the patch stands better by
itself.
v2: Move the commit about not touching the ringbuffer interrupt to the
snb_* function where it belongs (Rodrigo)
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_irq.c
ommit dd0a1aa19bd3d7203e58157b84cea78bbac605ac
Author: Jeff McGee
Date: Tue Feb 4 11:32:31 2014 -0600
drm/i915: Restore rps/rc6 on reset
Note with the above change the fix for gen8 is also handled (which was
not the case in Jeff's original patch).
Signed-off-by: Ben Widawsky
---
drivers/gp
Programming it outside of the rp0-rp1 range is considered a programming
error. Since we do not know that the previous value would actually be in
the range, program something we've read from the hardware, and therefore
know will work.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm
Reviewed-by: Rodrigo Vivi
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ac8419d..6259e47 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
ested-by: Kenneth Graunke
Cc: David E. Box
Cc: Kristen Carlson Accardi
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem.c | 12
drivers/gpu/drm/i915/intel_display.c | 5 +
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers
a hang on BDW silicon has been:
Tested-by: Kenneth Graunke
Cc: David E. Box
Cc: Kristen Carlson Accardi
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem.c | 12
drivers/gpu/drm/i915/intel_display.c | 5 +
2 files changed, 17 insertions(+)
diff --git a/dri
x27;t care about shadowed registers,
> Remove __needs_put funkiness from gen8_write. (Ville)
> Improved commit message.
>
> References: https://bugs.freedesktop.org/show_bug.cgi?id=74007
> Signed-off-by: Mika Kuoppala
> Cc: Ben Widawsky
> Cc: Ville Syrjälä
> Signe
of "hw_max" required a bit of interactivity.
v2: Updated code comments to be less repetitive and more informative
(Ben)
Cc: Jeff McGee
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_debugfs.c | 26
drivers/gpu/drm/i915/i915_drv.h | 31 +++---
drivers/gpu
ight thing. It'd at
least be a bit easier for review.
Anyway, having not actually looked at the code, the idea is solid:
Acked-by: Ben Widawsky
> ---
> drivers/gpu/drm/i915/i915_gpu_error.c | 50
> ++-
> 1 file changed, 31 insertions(+), 19 deletions(-
On Thu, Feb 13, 2014 at 01:47:57PM +0200, Ville Syrjälä wrote:
> On Wed, Feb 12, 2014 at 02:28:43PM -0800, Ben Widawsky wrote:
> > Rebased series from what I submitted a while ago:
> > http://lists.freedesktop.org/archives/intel-gfx/2013-December/037815.html
> >
> > I
es. I can't
remember why I did it in the first place. This addresses one of Imre's
other issues.
Fix error path leak of page tables.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 114
1 file changed, 64 insertions(+), 50 de
gfixes found in the previous patch by Imre
Moved number of pd pages assertion to the proper place (Imre)
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 172 ++--
1 file changed, 124 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i9
On Wed, Feb 19, 2014 at 09:11:46PM +0200, Imre Deak wrote:
> On Wed, 2014-02-12 at 14:28 -0800, Ben Widawsky wrote:
> > The previous allocation mechanism would get 2 contiguous allocations,
> > one for the page directories, and one for the page tables. As each page
> > table
On Wed, Feb 19, 2014 at 11:00:17PM +0200, Imre Deak wrote:
> On Wed, 2014-02-19 at 12:06 -0800, Ben Widawsky wrote:
> > Create 3 clear stages in PPGTT init. This will help with upcoming
> > changes be more readable. The 3 stages are, allocation, dma mapping, and
> >
On Wed, Feb 19, 2014 at 11:20:51PM +0200, Imre Deak wrote:
> On Wed, 2014-02-19 at 13:06 -0800, Ben Widawsky wrote:
> > On Wed, Feb 19, 2014 at 09:11:46PM +0200, Imre Deak wrote:
> > > On Wed, 2014-02-12 at 14:28 -0800, Ben Widawsky wrote:
> > > > The previous al
On Wed, Feb 19, 2014 at 11:50:51PM +0200, Imre Deak wrote:
> On Wed, 2014-02-19 at 12:09 -0800, Ben Widawsky wrote:
> > Like cleanup in an earlier patch, the code becomes much more readable,
> > and easier to extend if we extract out helper functions for the various
>
This got lost when we shuffled around our internal branch and
GEN7_FEATURES macro. There were no HW changes to support FBC, so we just
need to set the flag.
Cc: Daisy Sun
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_drv.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a
th series it's the second
iteration.
Ben Widawsky (9):
drm/i915/bdw: Free PPGTT struct
drm/i915/bdw: Reorganize PPGTT init
drm/i915/bdw: Split ppgtt initialization up
drm/i915: Make clear/insert vfuncs args absolute
drm/i915/bdw: Reorganize PT allocations
Revert "drm/i915/b
es. I can't
remember why I did it in the first place. This addresses one of Imre's
other issues.
Fix error path leak of page tables.
v4: Fix the fix of the error path leak. Original fix still leaked page
tables. (Imre)
Reviewed-by: Imre Deak
Signed-off-by: Ben Widawsky
---
drive
age (Imre)
Plug leaking gen8_pt_pages in both the error path, as well as general
free case (Imre)
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_drv.h | 5 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 130
2 files changed, 106 insertions(+), 29 del
/map/etc. or use a common
helper, similar to the ringbuffer code. I don't see a benefit to doing
this just yet, but who knows...
Reviewed-by: Chris Wilson
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 141 +++-
1 file changed, 91 inser
GEN8 never freed the PPGTT struct. As GEN8 doesn't use full PPGTT, the
leak is small and only found on a module reload. ie. I don't think this
needs to go to stable.
Reported-by: Ville Syrjälä
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 1 +
1 file
nt we need
a significant amount more memory simply for the page tables. To address
this, the allocations will be split up in finer amounts.
v2: Replace size_t with uint64_t (Chris, Imre)
Reviewed-by: Imre Deak
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_drv.h | 6 +--
driver
patches fixed/merged:
Reviewed-by: Imre Deak
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index fcde3c7..7245166 100644
--- a/drivers/gpu/drm/i915
I keep meaning to do this... by now almost the entire file has been
written by an Intel employee (including Daniel post-2010).
Reviewed-by: Imre Deak
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915
This cleanup is similar to the GEN8 cleanup (though less necessary).
Having everything split will make cleaning the initialization path error
paths easier to understand.
Reviewed-by: Chris Wilson
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 26
gfixes found in the previous patch by Imre
Moved number of pd pages assertion to the proper place (Imre)
v4:
Allocate dma address space for num_pd_pages, not num_pd_entries (Ben)
Don't use gen8_pt_dma_addr after free on error path (Imre)
With new fix from v4 of the previous patch.
Signed-off-b
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 3d5dd4a..5f7bee8 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers
emit (Ville)
Conditionally set .sync_to when semaphores are enabled (Ville)
Reviewed-by: Ville Syrjälä
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 119 +---
1 file changed, 62 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm
.
v2: v1 had a stale commit message
v3: Move everything in the is_semaphore_enabled() check
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 142 ++--
1 file changed, 97 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_
shared #define
On a related not, gen8 will use a different number of dwords for
semaphores, but not for add request.
v2: Make number of dwords an explicit part of signalling (via function
argument). (Chris)
v3: very slight comment change
Reviewed-by: Ville Syrjälä
Signed-off-by: Ben Widawsky
)
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_ringbuffer.c | 33 +
drivers/gpu/drm/i915/intel_ringbuffer.h | 4 ++--
3 files changed, 34 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i9
Syrjälä
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 42 -
drivers/gpu/drm/i915/intel_ringbuffer.h | 11 +
2 files changed, 32 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm
This will be helpful in abstracting some of the code in preparation for
gen8 semaphores.
v2: Move mbox stuff to a separate struct
Reviewed-by: Ville Syrjälä (v1)
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem.c | 10 ++--
drivers/gpu/drm/i915/i915_gpu_error.c | 6
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gpu_error.c | 29 +
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index bcab114..2b64493 100644
--- a/drivers/gpu
14 14:01:11 2014 +0100
drm/i915: Consolidate binding parameters into flags
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 5 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 153 +++
: Don't print signal, and wait (they should be the same). Instead,
print sync_seqno (Chris)
v3: Free the semaphore error object (Chris)
v4: Fix semaphore offset calculation during error state collection
(Ville)
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_drv.h
Simple debugfs file to display the current state of semaphores. This is
useful if you want to see the state without hanging the GPU.
NOTE: This patch is optional to the series.
NOTE2: Like the GPU error state collection, the reads are currently
incoherent.
Signed-off-by: Ben Widawsky
Everything should be lined up now to make gen8 semaphores work like they
did on previous generations, so just do it.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_drv.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915
This appears to not actually be needed on the current code. Just putting
it on the ML so we can point bug reports at it later.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_context.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915
work properly, which is broken in v3.
Disable rc6 on reset, and defer re-enabling until the first batch.
The fact that RC6 residency continues to increment, and that this patch
prevents a hang on BDW silicon has been:
Tested-by: Kenneth Graunke (v1)
Cc: David E. Box
Cc: Kristen Carlson Accard
On Thu, Feb 20, 2014 at 12:37:19PM +0200, Imre Deak wrote:
> On Wed, 2014-02-19 at 22:05 -0800, Ben Widawsky wrote:
> > This patch converts insert_entries and clear_range, both functions which
> > are specific to the VM. These functions tend to encapsulate the gen
> > specifi
At one time it was expected to be called in multiple places by kref_put.
At the current time however, it is all contained within
i915_gem_context.c.
This patch makes an upcoming required addition a bit nicer since it too
doesn't need to be defined in a header file.
Signed-off-by: Ben Wid
ed by Imre). Instead this
patch pulls the ppgtt struct freeing out of the cleanup and leaves it to
the allocators/callers or the one doing the last kref_put as in standard
convention
Reported-by: Ville Syrjälä
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_context.c | 12 ++-
Deak (v2)
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_drv.h | 6 +--
drivers/gpu/drm/i915/i915_gem_gtt.c | 90 +
2 files changed, 54 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_
age (Imre)
Plug leaking gen8_pt_pages in both the error path, as well as general
free case (Imre)
v5: Rename leftover "which_" variables (Imre)
Add the pde = 0 wrap that was missed from v3 (Imre)
Reviewed-by: Imre Deak
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_drv.h
This got lost when we shuffled around our internal branch and
GEN7_FEATURES macro. There were no HW changes to support FBC, so we just
need to set the flag.
v2: Don't allow FBC for any pipe but A on platforms with DDI. (Paulo)
Cc: Daisy Sun
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm
ned-off-by: Mika Kuoppala
Either way:
Reviewed-by: Ben Widawsky
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> b/drivers/gpu/drm/i915/intel_unc
Packard
Date: Fri Jan 6 11:44:11 2012 -0800
drm/i915: Hold gt_lock during reset
I for one would mind another patch with a WARN if it's non-zero... just
saying, and in such a case we could make the WARN gen specific, and the
dev_priv->uncore.fifo_count = 0 for all platforms.
Re
gen8_write
>
> v2: Read side doesn't care about shadowed registers,
> Remove __needs_put funkiness from gen8_write. (Ville)
> Improved commit message.
>
> References: https://bugs.freedesktop.org/show_bug.cgi?id=74007
> Cc: Ben Widawsky
> Cc: Ville Syrjälä
> S
On Fri, Feb 21, 2014 at 11:38:48AM -0800, Ben Widawsky wrote:
> On Fri, Feb 21, 2014 at 05:31:59PM +0200, mika.kuopp...@intel.com wrote:
> > From: Mika Kuoppala
> >
> > Sometimes generic driver code gets forcewake explicitly by
> > gen6_gt_force_wake_get(), which c
de/HW..
With the rework of the page table allocations, there is no longer a
distinction between number of page table pages, and number of page
directory entries. To avoid confusion, kill the redundant (and newer)
struct member.
Cc: Imre Deak
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm
On Sat, Feb 22, 2014 at 01:37:16PM +, Chris Wilson wrote:
> On Mon, Feb 17, 2014 at 07:01:44PM -0800, Ben Widawsky wrote:
> > The names of the struct members for RPS are stupid. Every time I need to
> > do anything in this code I have to spend a significant amount of time to
&g
On Sat, Feb 22, 2014 at 11:34:16AM -0800, Ben Widawsky wrote:
> On Sat, Feb 22, 2014 at 01:37:16PM +, Chris Wilson wrote:
> > On Mon, Feb 17, 2014 at 07:01:44PM -0800, Ben Widawsky wrote:
> > > The names of the struct members for RPS are stupid. Every time I need to
> &g
On Sat, Feb 22, 2014 at 07:37:04PM +, Chris Wilson wrote:
> On Sat, Feb 22, 2014 at 11:34:16AM -0800, Ben Widawsky wrote:
> > On Sat, Feb 22, 2014 at 01:37:16PM +, Chris Wilson wrote:
> > > On Mon, Feb 17, 2014 at 07:01:44PM -0800, Ben Widawsky wrote:
> > >
\
> __raw_i915_write##x(dev_priv, reg, val); \
> if (__needs_put) { \
> dev_priv->uncore.funcs.force_wake_put(dev_priv, \
> FORCEWAKE_ALL); \
> } \
> + hsw_unclaimed_reg_check(dev_priv, reg); \
> REG_WRITE_FOO
== 0)
> - dev_priv->uncore.funcs.force_wake_put(dev_priv);
> + if (--dev_priv->uncore.forcewake_count == 0) {
> + dev_priv->uncore.forcewake_count++;
> + mod_delayed_work(dev_priv->wq,
> + &dev_priv-&
On Thu, Jan 02, 2014 at 07:50:35PM -1000, Ben Widawsky wrote:
> Will full PPGTT support it can be assumed that every file descriptor
> gets its own hardware context. As such, there is no need to allocate
> anew context in order to use the features provided by hardware contexts.
> Elim
On Mon, Feb 24, 2014 at 01:27:09PM +0200, Ville Syrjälä wrote:
> On Fri, Feb 21, 2014 at 11:38:48AM -0800, Ben Widawsky wrote:
> > On Fri, Feb 21, 2014 at 05:31:59PM +0200, mika.kuopp...@intel.com wrote:
> > > From: Mika Kuoppala
> > >
> > > Sometime
On Mon, Feb 24, 2014 at 08:30:22AM +, Chris Wilson wrote:
> On Sun, Feb 23, 2014 at 12:12:25PM -0800, Ben Widawsky wrote:
> > On Mon, Aug 26, 2013 at 12:06:43PM +0100, Chris Wilson wrote:
> > > Obtaining the forcwake requires expensive and time consuming
> > > seri
On Mon, Feb 24, 2014 at 07:03:12PM +0200, Imre Deak wrote:
> On Thu, 2014-02-20 at 11:51 -0800, Ben Widawsky wrote:
> > The previous allocation mechanism would get 2 contiguous allocations,
> > one for the page directories, and one for the page tables. As each page
> > table
On Sat, Feb 22, 2014 at 08:08:23PM +, Chris Wilson wrote:
> On Sat, Feb 22, 2014 at 11:40:43AM -0800, Ben Widawsky wrote:
> > On Sat, Feb 22, 2014 at 07:37:04PM +, Chris Wilson wrote:
> > > On Sat, Feb 22, 2014 at 11:34:16AM -0800, Ben Widawsky wrote:
> > > >
:
Runtime PM support for Broadwell from Paulo
http://cgit.freedesktop.org/~bwidawsk/drm-intel/log/?h=broadwell
Thanks for your attention.
--
Ben Widawsky, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http
This should already be included in the latest upstream libdrm.
commit a254cb50414a5def5c872a765c0dd1295a550c6b
Author: Ben Widawsky
Date: Thu Jan 2 11:36:59 2014 -0800
intel: Merge latest i915_drm.h
> ---
> include/drm/i915_drm.h | 6 ++
> 1 file changed, 6 insertions(+)
e reading this
whomever you were, my apoligies.
>
> Signed-off-by: Chris Wilson
> Cc: Ben Widawsky
I think Cc: stable too
Reviewed-by: Ben Widawsky
> ---
> drivers/gpu/drm/i915/i915_gem.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drive
ength was introduced in the API, the num_entries
calculation should have been (length - start) as opposed to just length.
As this is only a bug on clearing entries, it wasn't easily apparent.
(Ben)
Reviewed-by: Imre Deak
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_drv.
These page table helpers make the code much cleaner. There is some
room to use the arch/x86 header files. The reason I've opted not to is
in several cases, the definitions are dictated by the CONFIG_ options
which do not always indicate the restrictions in the GPU.
Signed-off-by: Ben Wid
On Tue, Feb 25, 2014 at 06:13:44PM -0800, Ben Widawsky wrote:
> This patch converts insert_entries and clear_range, both functions which
> are specific to the VM. These functions tend to encapsulate the gen
> specific PTE writes. Passing absolute addresses to the insert_entries,
> and
On Tue, Feb 25, 2014 at 11:27:15PM -0800, Ben Widawsky wrote:
> On Tue, Feb 25, 2014 at 06:13:44PM -0800, Ben Widawsky wrote:
> > This patch converts insert_entries and clear_range, both functions which
> > are specific to the VM. These functions tend to encapsulate the gen
> >
similar paranoia could be applied to GGTT via making sure
all entries are invalid ASAP. I think the extra work required to fix
such a BIOS bug is unwarranted until proven necessary.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 16 +---
1 file changed, 9
; if (INTEL_INFO(dev)->gen >= 6)
> I915_WRITE(MI_MODE,
> _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
Patch 2, and 3 are:
Reviewed-by: Ben Widawsky
--
Ben Widawsky, Intel Open Source Technology Center
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vers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4838,6 +4838,10 @@ static void gen8_init_clock_gating(struct drm_device
> > *dev)
> > /* FIXME(BDW): Check all the w/a, some might only apply to
> > * pre-production hw. */
> >
similar paranoia could be applied to GGTT via making sure
all entries are invalid ASAP. I think the extra work required to fix
such a BIOS bug is unwarranted until proven necessary.
v2: Remove useless GFP_ZERO in the kcallocs
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 7
t_ctx);
> - idr_destroy(&file_priv->context_idr);
> }
I don't see too much harm in just initializing the idr regardless to
keep the close path simpler. Then stick a WARN in context_idr_cleanup if
it actually does anything, fake_context_idr_cleanup();
I have some recollection of hitting a really tricky thing while
developing PPGTT where the order of the unref in the above sequence
really mattered. Looking again though, I don't see anything familiar
- but my suggestion would put me completely at ease.
In either case:
Reviewed-by: Ben Widawsky
>
> struct i915_hw_context *
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today, and
Daniel made it a 3.14-rc4 based thing today. It was still present on
3.13.0. Actually, i915_gem_retire_work_handler is the only one even
showing up in powertop, which is how it should be IMO.
Therefore I'm not sure what we should do with this.
>
> Signed-off-by: Chris Wils
;t be easily
applied, I'd guess.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 94 +
1 file changed, 73 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index
On Tue, Mar 04, 2014 at 03:45:56PM +0100, Daniel Vetter wrote:
> On Tue, Feb 18, 2014 at 11:18:04AM -0800, Ben Widawsky wrote:
> > On Wed, Feb 12, 2014 at 07:18:40PM +, Chris Wilson wrote:
> > > For stolen pages, since it is verboten to access them directly on many
> >
The PDE needs to wrap after writing all the PTEs. Quite a small/silly
bug to find in the massive change. It was introduced:
commit 307dc4f99f6d3a74a78b0e776838f35b2004f14d
Author: Ben Widawsky
Date: Thu Feb 20 11:51:21 2014 -0800
drm/i915/bdw: Reorganize PT allocations
I can't act
incrementing)
>
> Thanks
> Kiran
>
> -Original Message-
> From: intel-gfx-boun...@lists.freedesktop.org
> [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of Ben Widawsky
> Sent: Tuesday, November 05, 2013 12:15 PM
> To: Intel GFX
> Cc: Nikula, Jan
broken IMO (and it was broken for me, but I had assumed it never
worked).
Regression from:
commit ed8546ac1f99b850879f07b1e9b06b42fb0a36d9
Author: Ben Widawsky
Date: Mon Nov 4 22:45:05 2013 -0800
drm/i915/bdw: Support eDP PSR
I am pretty certain PSR is disabled by default, so no CC s
On Wed, Mar 05, 2014 at 11:13:12AM +0200, Jani Nikula wrote:
> On Wed, 05 Mar 2014, Ben Widawsky wrote:
> > The PDE needs to wrap after writing all the PTEs. Quite a small/silly
> > bug to find in the massive change. It was introduced:
> > commit 307dc4f99f6d3a74a78
On Wed, Mar 05, 2014 at 06:32:06PM +0200, Imre Deak wrote:
> On Thu, 2014-02-27 at 19:47 -0800, Ben Widawsky wrote:
> > We normally clear the page tables as one of the first things during
> > initialization. They are however wired up (and potentially valid) before
> > we cle
_get(dev_priv, fw_engine);
> +
> if (IS_GEN6(dev) || IS_GEN7(dev))
> dev_priv->uncore.fifo_count =
> __raw_i915_read32(dev_priv, GTFIFOCTL) &
I for one would not be opposed to a vlv_do_reset() and a
gen8_do_reset(). I implemented such
On Wed, Mar 05, 2014 at 06:08:19PM +0200, Mika Kuoppala wrote:
> There should not be a case where fifo count is other
> than zero after a successful reset. Always set
> count to zero, but be paranoid enough to warn.
>
> v2: rebased
>
> Suggested-by: Ben Widawsky
> Sign
On Wed, Mar 05, 2014 at 07:33:11PM +0100, Daniel Vetter wrote:
> On Wed, Mar 05, 2014 at 09:24:34AM +, Chris Wilson wrote:
> > On Tue, Mar 04, 2014 at 09:38:56AM -0800, Ben Widawsky wrote:
> > > The actual post sync op is "Write Immediate Data QWord." It is ther
On Wed, Mar 05, 2014 at 07:24:37AM -0800, Ben Widawsky wrote:
> On Wed, Mar 05, 2014 at 11:13:12AM +0200, Jani Nikula wrote:
> > On Wed, 05 Mar 2014, Ben Widawsky wrote:
> > > The PDE needs to wrap after writing all the PTEs. Quite a small/silly
> > > bug to find in
On Wed, Mar 05, 2014 at 12:00:18PM +0100, Daniel Vetter wrote:
> On Fri, Feb 21, 2014 at 04:06:47PM -0300, Paulo Zanoni wrote:
> > 2014-02-20 21:01 GMT-03:00 Ben Widawsky :
> > > This got lost when we shuffled around our internal branch and
> > > GEN7_FEATURES macro.
On Wed, Mar 05, 2014 at 10:30:21PM +, Chris Wilson wrote:
> On Wed, Mar 05, 2014 at 11:05:15AM -0800, Ben Widawsky wrote:
> > On Wed, Mar 05, 2014 at 07:33:11PM +0100, Daniel Vetter wrote:
> > > On Wed, Mar 05, 2014 at 09:24:34AM +, Chris Wilson wrote:
> > > >
ndow is approaching and I think we need to
> use the remaining time to ensure that our fallback option of using
> aliasing ppgtt is in solid shape. Hence I think it's time to throw the
> switch. While at it demote the helper from static inline status
> because really.
>
> Cc:
On Thu, Mar 06, 2014 at 09:30:01PM +0100, Daniel Vetter wrote:
> On Thu, Mar 06, 2014 at 10:17:12AM -0800, Ben Widawsky wrote:
> > On Thu, Mar 06, 2014 at 12:14:21PM +0100, Daniel Vetter wrote:
> > > There are too many oustanding issues:
> > >
> > > - Fence ha
x27;ve backed out Mika's original patch, this seems to be the wrong path.
> -Daniel
>
> > + }
> >
> > dev_priv->uncore.fifo_count = 0;
> >
I've seen this too. Though I think the WARN does coincide with what the
docs state - it doesn't seem
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