Upcoming patches will use the terms map and unmap in references to the
page table entries. Having this distinction will really help with code
clarity at that point.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 12 ++--
1 file changed, 6 insertions(+), 6
Split out single mappings which will help with upcoming work. Also while
here, rename the function because it is a better description - but this
function is going away soon.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 39 ++---
1 file
oes to him.
References: 20140320115742.ga4...@nuc-i3427.alporthouse.com
Cc: Mika Kuoppala
Cc: Chris Wilson
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_debugfs.c | 49 +++--
1 file changed, 30 insertions(+), 19 deletions(-)
diff --git a/drivers/gp
meliorated shortly.
NOTE: The pun in the subject was intentional.
Signed-off-by: Ben Widawsky
Conflicts:
drivers/gpu/drm/i915/i915_drv.h
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 175 ++--
drivers/gpu/drm/i915/i915_gem_gtt.h | 24 +++--
2 files ch
f future patches.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index d3c52b1..0869e54 100644
--- a/drivers/gpu/drm/
ing around with such things trivial.
v2: Updated commit message to explain why this patch exists
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 226 +++-
drivers/gpu/drm/i915/i915_gem_gtt.h | 4 +-
2 files changed, 147 insertions(+), 83
Therefore we can do it from our general init function. Eventually, I
hope to have a lot more commonality like this. It won't arrive yet, but
this was a nice easy one.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 5 +
1 file changed, 1 insertion(+), 4 dele
lt;<22) == 512);
assert(gen6_pde_count(base + 0x1000, 512<<22) == 512);
assert(gen6_pde_count(base + (1<<22), 512<<22) == 511);
}
int main()
{
test_pde(0);
while (1)
test_pte(rand() & ~((1<<22) - 1));
return 0;
}
Signe
It's useful to have it not as a macro for some upcoming work. Generally
since we try to avoid macros anyway, I think it doesn't hurt to put this
as its own patch.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 9 +++--
drivers/gpu/drm/i915/i915_gem_gtt.h
navoidable wart
throughout the series. (in other words, not extra flagrant).
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915
point I will try to
combine functionality.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 61 +++--
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 ++
2 files changed, 34 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915
;ll need a function for
that in the future as well.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 94 -
1 file changed, 52 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_g
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 43 ++---
1 file changed, 31 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 14aae05..10cfad8 100644
--- a/drivers
We have some fanciness coming up. This patch just breaks out the logic.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_context.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915
There is never a case where we don't want to do it. Since we've broken
up the allocations into nice clean helper functions, it's both easy and
obvious to do the dma mapping at the same time.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915
These values are never quite useful for dynamic allocations of the page
tables. Getting rid of them will help prevent later confusion.
TODO: this probably needs to be earlier in the series
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_debugfs.c | 11 -
drivers/gpu/drm/i915
The page directory freer is left here for now as it's still useful given
that GEN8 still preallocates. Once the allocation functions are broken
up into more discrete chunks, we'll follow suit and destroy this
leftover piece.
comments
Signed-off-by: Ben Widawsky
---
drivers/gp
d-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_debugfs.c | 19 -
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 118 +---
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 +-
drivers/gpu/drm/i915/i915_tr
The latter point only matters with full PPGTT. The former point would
only effect 32b platforms, or platforms with less than 4GB memory.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 32
drivers/gpu/drm/i915/i915_gem_gtt.h | 5 -
2 files c
scratch pages/tables will only be pointed to by page
tables which have less than all of the entries filled.
I wrote the patch while debugging so I figured why not put it in the
series.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 25 +++--
1 file
be a
discrete operation.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 147 +---
1 file changed, 85 insertions(+), 62 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index e396b89..e8
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_debugfs.c | 59 +++--
drivers/gpu/drm/i915/i915_gem_gtt.c | 32
drivers/gpu/drm/i915/i915_gem_gtt.h | 9 ++
3 files changed, 85 insertions(+), 15 deletions(-)
diff --git a/drivers
Like with gen6/7, we can enable bitmap tracking with all the
preallocations to make sure things actually don't blow up.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 101 +++-
drivers/gpu/drm/i915/i915_gem_gtt.h | 12 +
2
Similar to the patch a few back in the series, we can always map and
unmap page directories when we do their allocation and teardown. Page
directory pages only exist on gen8+, so this should only effect behavior
on those platforms.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915
quire newlines, or local
variables to make it fit cleanly.
Notice that even the page allocation shares this same attribute. For
now, I am leaving that code untouched because the macro version would be
a bit on the big side - but it's a nice cleanup as well (IMO)
Signed-off-by: Ben Widawsky
--
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 54 -
drivers/gpu/drm/i915/i915_gem_gtt.h | 10 +++
2 files changed, 39 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915
ther than a
few tidbits which lead me to believe there are some corner cases that
will require it. I'm mostly depending on the reload of DCLV to
invalidate the old TLBs. We can try to remove this patch and see what
happens.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i91
This finishes off the dynamic page tables allocations, in the legacy 3
level style that already exists. Most everything has already been setup
to this point, the patch finishes off the enabling by setting the
appropriate function pointers.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915
sing PPGTT is not managed here. The patch which actually
begins dynamic allocation/teardown explains the reasoning forthis.
v2: s/pdp.pagedir/pdp.pagedirs
Make a scratch page allocation helper
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_g
The code for 4lvl works just as one would expect, and nicely it is able
to call into the existing 3lvl page table code to handle all of the
lower levels.
PML4 has no special attributes.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 170
This transitional patch doesn't do much for the existing code. However,
it should make upcoming patches to use the full 48b address space a bit
easier to swallow. The patch also introduces the PML4, ie. the new top
level structure of the page tables.
Signed-off-by: Ben Widawsky
---
driver
I was getting unexplainable hangs with the last patch, even though I
think it should be correct. As the subject says, should this ever get
merged, it needs to be coordinated with the patch this reverts.
Revert "drm/i915/bdw: Optimize PDP loads"
This reverts commit 64053129b5cbd3a5f87dab27d026c17e
v2: 0 pad the new 8B fields or else intel_error_decode has a hard time.
Note, regardless we need an igt update.
v3: Make reloc_offset 64b also.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
drivers/gpu/drm/i915/i915_gpu_error.c | 18 ++
2
Don't do them if they're not necessary, which they're not, for the RCS,
in certain conditions.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 20
drivers/gpu/drm/i915/i915_gem_gtt.h | 1 +
2 files changed, 21 insertions(+)
diff --gi
This works the same as GEN6.
I was disappointed that I need to pass vm around now, but it's not so
much uglier than the drm_device, and having the vm in trace events is
hugely important.
v2: Consolidate pagetable/pagedirectory events
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm
Map is easy, it's the same register as the PDP descriptor 0, but it only
has one entry. Also, the mapping code is now trivial thanks to all of
the prep patches.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 53 +
drivers/gpu/drm
There is no need to preallocate the aliasing PPGTT. The code is properly
plubmed now to treat this address space like any other.
v2: Updated for CHV. Note CHV doesn't support 64b address space.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c
l4 for the top level, and the pdp is just one of the entries
being pointed to by a pml4e.
This patch addresses some carelessness done throughout development wrt
assumptions made of the root page tables.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_g
GGTT should really use these new functions as
well.
BISECT WARNING: This commit breaks aliasing PPGTT as is. If you see this
during bisect, please skip. There was no other way I could find to make
these changes remotely readable
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 3 ---
2 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b3b52cf..0848638 100644
--- a/drivers/gpu
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 33f9abd..15ede8e 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/
enabled.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_drv.h| 1 +
drivers/gpu/drm/i915/i915_gem.c| 22 +++---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 3 +++
drivers/gpu/drm/i915/i915_gem_gtt.h| 4
4 files changed, 27
This is needed for the proof of concept work that will allow mirrored
GPU addressing via the existing userptr interface. Part of the hack
involves passing the context ID to the ioctl in order to get a VM.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_userptr.c | 120
---
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index fec8114..a4ea50a 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/
From: Chris Wilson
By exporting the ability to map user address and inserting PTEs
representing their backing pages into the GTT, we can exploit UMA in order
to utilize normal application data as a texture source or even as a
render target (depending upon the capabilities of the chipset). This ha
ssion from a revert of the revert:
commit 7907f45bf9f67a1c5e5d4ae05bab428d7c2f43b2
Author: Ben Widawsky
Date: Wed Feb 19 22:05:46 2014 -0800
Revert "drm/i915/bdw: Limit GTT to 2GB"
v2: Change ifdef to 32b, instead of ifndef
update comment
v3. Update comment to not wrap (Daniel)
/show_bug.cgi?id=78935
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78936
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78937
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_context.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915
/show_bug.cgi?id=78934
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78935
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78936
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78937
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_context.c | 3 +++
1 file changed
://bugs.freedesktop.org/show_bug.cgi?id=78935
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78936
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78937
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78938
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915
On Wed, May 28, 2014 at 04:06:58PM -0700, Ben Widawsky wrote:
> The PDPs seem to get screwed up otherwise, specifically PDP0. I am not
> really clear why this is required, it just works with full PPGTT.
>
> v2: Only do it for gen8, to limit regression potential
>
> v3: Fix the
On Wed, May 28, 2014 at 10:54:21PM -0700, Ben Widawsky wrote:
> On Wed, May 28, 2014 at 04:06:58PM -0700, Ben Widawsky wrote:
> > The PDPs seem to get screwed up otherwise, specifically PDP0. I am not
> > really clear why this is required, it just works with full PPGTT.
> >
&
AS_DDI(dev)) {
For the love of god, can we please rename "bits X" in the
struct bdb_general_features? That caused me endless pain. It should be
"byte 0"
Also, I guess there is a problem when the VBT is missing, and we have a
dont have a CRT on non-ULT (since the default seems to be tru
ier fix of only marking the ctx as initialised after it is
> saved by the hardware during a SET_CONTEXT operation.
>
> Signed-off-by: Chris Wilson
> Cc: Ville Syrjälä
> Cc: Damien Lespiau
> Cc: Mika Kuoppala
> Cc: Ben Widawsky
> ---
> drivers/gpu/drm/i915/i915_gem_
/show_bug.cgi?id=78937
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78938
> Signed-off-by: Kenneth Graunke
> Cc: Ben Widawsky
I sat with Ken all day today (after a few days of debugging myself) and
it does what it purport to do, and fixes a bunch of tests.
Reviewed-by: Ben
makes sure the platform match what is expected.
Sample output:
bwidawsk@ironside ~/intel-gfx/intel-gpu-tools (master)$ sudo
./tests/gem_exec_nop
PCI ID: 0x0a16 IGT-Version: 1.6-g21bcc3f (x86_64) (Linux: 3.14.4-1-ARCH x86_64)
Signed-off-by: Ben Widawsky
---
lib/igt_core.c | 17
is only needed for BDW E,F step.
>
> Issue: APDEV-3096
> Signed-off-by: Michel Thierry
Docs say Gt3 only.
Otherwise, it's
Reviewed-by: Ben Widawsky
--
Ben Widawsky, Intel Open Source Technology Center
___
Intel-gfx mailing list
Inte
or the second pipe.
>
> Signed-off-by: Rodrigo Vivi
Reviewed-by: Ben Widawsky
Should be cc: stable IMO
[snip]
--
Ben Widawsky, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesk
mment to fopen
bad sign-off in mail
added unnecessary whitespace
replace assert with open coded abort
So I've merged it with all those warts (except I fixed the
signed-off-by). Please keep these things in mind next patch, and feel
free to submit patches to fix these issues as well.
[snip
On Tue, Jun 10, 2014 at 01:33:51PM +0800, Aaron Lu wrote:
> +Ben Widawsky & Daniel Vetter
>
> On 06/09/2014 03:38 PM, Lewis Toohey wrote:
> > On 3 June 2014 02:22, Aaron Lu wrote:
> >> On 05/30/2014 09:12 PM, Lewis Toohey wrote:
> >>> Aaron
> >&
On Tue, Jun 10, 2014 at 08:59:32PM +0100, Lewis Toohey wrote:
> On 10 June 2014 17:58, Ben Widawsky wrote:
> > On Tue, Jun 10, 2014 at 01:33:51PM +0800, Aaron Lu wrote:
> >> +Ben Widawsky & Daniel Vetter
> >>
> >> On 06/09/2014 03:38 PM, Lewis Toohey wrot
> - INTEL_BDW_GT3D_IDS(info)
> + INTEL_BDW_GT3D_IDS(info), \
> + INTEL_BDW_RSVDD_IDS(info)
>
> #define INTEL_CHV_IDS(info) \
> INTEL_VGA_DEVICE(0x22b0, info), \
> --
> 1.9.3
>
> _______
> Intel-gfx mailing l
hen user reported accelaration
> weren't
> enabled.
>
> v2: Reserved IDs doesn't have GT defined. So, creating a separated list. (Ben)
>
> Cc: Ben Widawsky
> Signed-off-by: Rodrigo Vivi
> ---
> include/drm/i915_pciids.h | 16 ++--
> 1 file ch
bar's context
// load foos PDPs
LRI PDPs 1
MI_SET_CONTEXT bar // save PDPs 1 to foo's context
It's all wacky. This should allow full PPGTT on Broadwell to work.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_context.c | 24 ++--
Broadwell is perfectly capable of full PPGTT. I've been using it for
some time, and seen no especially ill effects.
Signed-off-by: Ben Widawsky
Conflicts:
drivers/gpu/drm/i915/i915_drv.h
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
On Thu, Jun 12, 2014 at 07:16:48PM +0300, Ville Syrjälä wrote:
> On Thu, Jun 12, 2014 at 08:25:52AM -0700, Ben Widawsky wrote:
> > On GEN8 the PDPs are saved and restored with context, which means we
> > must set them after the context switch has occurred. If we do not do
>
15/intel_ringbuffer.h
> b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 38c757e..6c52d59 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -259,6 +259,7 @@ int intel_init_vebox_ring_buffer(struct
On Thu, Jan 30, 2014 at 01:25:42PM +0200, Ville Syrjälä wrote:
> On Wed, Jan 29, 2014 at 11:55:24AM -0800, Ben Widawsky wrote:
> > With the ring mask we now have an easy way to know the number of rings
> > in the system, and therefore can accurately predict the number of dwords
emit (Ville)
Conditionally set .sync_to when semaphores are enabled (Ville)
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 55 ++---
1 file changed, 30 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/dr
soon as the flush is complete - in parallel
> to the TLB invalidate. Adding CONTROL_FLUSH_ENABLE would then stall the
> CS until the post-sync operation completes. That still leaves the
> possibility that the TLB invalidate is being performed in parallel and
> is itself provid
On Tue, Feb 11, 2014 at 10:53:40PM +0200, Ville Syrjälä wrote:
> On Tue, Feb 11, 2014 at 12:20:42PM -0800, Ben Widawsky wrote:
> > With the ring mask we now have an easy way to know the number of rings
> > in the system, and therefore can accurately predict the number of dwords
On Thu, Jan 30, 2014 at 02:38:17PM +0200, Ville Syrjälä wrote:
> On Wed, Jan 29, 2014 at 11:55:26AM -0800, Ben Widawsky wrote:
> > Semaphore signalling works similarly to previous GENs with the exception
> > that the per ring mailboxes no longer exist. Instead you must define
>
On Tue, Feb 11, 2014 at 02:11:04PM -0800, Ben Widawsky wrote:
> On Thu, Jan 30, 2014 at 02:38:17PM +0200, Ville Syrjälä wrote:
> > On Wed, Jan 29, 2014 at 11:55:26AM -0800, Ben Widawsky wrote:
> > > Semaphore signalling works similarly to previous GENs with the exception
>
On Tue, Feb 11, 2014 at 10:23:38PM +, Chris Wilson wrote:
> On Tue, Feb 11, 2014 at 01:48:22PM -0800, Ben Widawsky wrote:
> > On Thu, Jan 30, 2014 at 01:35:41PM +, Chris Wilson wrote:
> > > On Thu, Jan 30, 2014 at 02:18:32PM +0100, Daniel Vetter wrote:
> > > >
On Tue, Feb 11, 2014 at 02:22:37PM -0800, Ben Widawsky wrote:
> On Tue, Feb 11, 2014 at 02:11:04PM -0800, Ben Widawsky wrote:
> > On Thu, Jan 30, 2014 at 02:38:17PM +0200, Ville Syrjälä wrote:
> > > On Wed, Jan 29, 2014 at 11:55:26AM -0800, Ben Widawsky wrote:
> > > &
On Thu, Jan 30, 2014 at 02:58:09PM +, Chris Wilson wrote:
> On Thu, Jan 30, 2014 at 04:53:32PM +0200, Ville Syrjälä wrote:
> > On Wed, Jan 29, 2014 at 11:55:31AM -0800, Ben Widawsky wrote:
> > > + obj = error->semaphore_obj;
> > > + if (obj) {
> >
> >
On Thu, Jan 30, 2014 at 04:53:32PM +0200, Ville Syrjälä wrote:
> On Wed, Jan 29, 2014 at 11:55:31AM -0800, Ben Widawsky wrote:
> > Since the semaphore information is in an object, just dump it, and let
> > the user parse it later.
> >
> > NOTE: The page being
ns that we then report the oldest incomplete batch on
> each ring, which can be useful for determining the state of userspace at
> the time of a hang.
>
> v2: Use i915_gem_find_active_request (Mika)
>
> Signed-off-by: Chris Wilson (v1)
> Signed-off-by: Mika Kuoppala (v2)
> C
an compare
> its contents against the intended batch for the active request.
>
> v3: Rebase (Mika)
>
> Link: http://lists.freedesktop.org/archives/intel-gfx/2013-August/032280.html
> Signed-off-by: Chris Wilson (v2)
> Signed-off-by: Mika Kuoppala (v3)
> Cc: Be
or(dev, false);
> + i915_handle_error(dev, false,
> + "Command parser error, iir 0x%08x",
> + iir);
>
> for_each_pipe(pipe) {
> int reg = PIPESTAT(pipe);
> @@ -341
On Wed, Feb 12, 2014 at 08:15:58AM +, Chris Wilson wrote:
> On Tue, Feb 11, 2014 at 06:07:09PM -0800, Ben Widawsky wrote:
> > I still like my solution which does the strcpy on context creation. Your
> > solution is deferred in the usual case since the hangcheck is
> > asyn
On Wed, Feb 12, 2014 at 08:25:58AM +, Chris Wilson wrote:
> On Tue, Feb 11, 2014 at 05:57:19PM -0800, Ben Widawsky wrote:
> > On Mon, Feb 10, 2014 at 04:30:49PM +0200, Mika Kuoppala wrote:
> > > -static struct drm_i915_gem_request *
> > > -i915_gem_fin
On Wed, Feb 12, 2014 at 08:13:50AM +, Chris Wilson wrote:
> On Tue, Feb 11, 2014 at 06:32:24PM -0800, Ben Widawsky wrote:
> > > @@ -3234,7 +3241,9 @@ static irqreturn_t i8xx_irq_handler(int irq, void
> > > *arg)
> > >*/
> > >
On Wed, Feb 12, 2014 at 07:18:19PM +, Chris Wilson wrote:
> On Wed, Feb 12, 2014 at 10:55:07AM -0800, Ben Widawsky wrote:
> > On Wed, Feb 12, 2014 at 08:15:58AM +, Chris Wilson wrote:
> > Are you opposed to doing anything at context creation? pid reference
> > works f
This reverts commit 3a2ffb65eec6dbda2fd8151894f51c18b42c8d41.
Now that the code is fixed to use smaller allocations, it should be safe
to let the full GGTT be used on DW.
The testcase for this is anything which uses more than half of the GTT,
thus eclipsing the old limit.
Signed-off-by: Ben
This cleanup is similar to the GEN8 cleanup (though less necessary).
Having everything split will make cleaning the initialization path error
paths easier to understand.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 26 +++---
1 file changed, 19
semantics. I've
kept the error path as similar as possible to the cleanup() function to
make sure cleanup is as robust as possible
v2: Remove comment "NB:From here on, ppgtt->base.cleanup() should
function properly"
Update commit message to reflect above
Signed-off-by: Ben Widawsk
nt we need
a significant amount more memory simply for the page tables. To address
this, the allocations will be split up in finer amounts.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_drv.h | 6 +--
drivers/gpu/drm/i915/i915_gem_gtt.c | 80 +--
optional.
Ben Widawsky (9):
drm/i915/bdw: Split up PPGTT cleanup
drm/i915/bdw: Reorganize PPGTT init
drm/i915/bdw: Split ppgtt initialization up
drm/i915: Make clear/insert vfuncs args absolute
drm/i915/bdw: Reorganize PT allocations
Revert "drm/i915/bdw: Limit GTT to 2GB"
I keep meaning to do this... by now almost the entire file has been
written by an Intel employee (including Daniel post-2010).
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers
This will make the code more readable, and extensible which is needed
for upcoming feature work. Eventually, we'll do the same for init.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 59 -
1 file changed, 38 insertions(+), 21 dele
/map/etc. or use a common
helper, similar to the ringbuffer code. I don't see a benefit to doing
this just yet, but who knows...
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 141 +++-
1 file changed, 91 insertions(+), 50 deletions(-)
we free.
v2: Don't call cleanup on the error path since that takes down the
drm_mm and list entry, which aren't setup at this point.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 124 +
mostly the same otherwise. I've
kept the convention Chris used for the pte wrap (I had something
slightly different, and broken - but fixable)
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_drv.h | 5 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 127 --
On Wed, Feb 12, 2014 at 11:19:24PM +, Damien Lespiau wrote:
> On Wed, Feb 12, 2014 at 02:28:50PM -0800, Ben Widawsky wrote:
> > I keep meaning to do this... by now almost the entire file has been
> > written by an Intel employee (including Daniel post-2010).
> >
&
On Wed, Feb 12, 2014 at 11:45:59PM +, Chris Wilson wrote:
> On Wed, Feb 12, 2014 at 02:28:48PM -0800, Ben Widawsky wrote:
> > - for (i = first_pte; i < last_pte; i++)
> > + for (i = which_pte; i < last_pte; i++) {
> >
On Thu, Feb 13, 2014 at 12:14:15AM +, Chris Wilson wrote:
> On Wed, Feb 12, 2014 at 02:28:47PM -0800, Ben Widawsky wrote:
> > This patch converts insert_entries and clear_range, both functions which
> > are specific to the VM. These functions tend to encapsulate the gen
> >
On Tue, Feb 11, 2014 at 05:12:17PM +0100, Daniel Vetter wrote:
> On Thu, Feb 06, 2014 at 11:42:39AM -0200, Rodrigo Vivi wrote:
> > Reviewed-by: Rodrigo Vivi
> >
> > On Wed, Jan 29, 2014 at 2:25 AM, Ben Widawsky
> > wrote:
> > > Signed-off-by: Ben Widawsky
&
On Fri, Feb 14, 2014 at 08:41:08PM +, Chris Wilson wrote:
> On Fri, Feb 14, 2014 at 12:34:22PM -0800, Ben Widawsky wrote:
> > On Tue, Feb 11, 2014 at 05:12:17PM +0100, Daniel Vetter wrote:
> > > - 6/9 lacks review ...
> > >
> >
> > 6/9 can be skipped
On Thu, Feb 06, 2014 at 12:15:12PM -0200, Rodrigo Vivi wrote:
> On Wed, Jan 29, 2014 at 2:25 AM, Ben Widawsky
> wrote:
> > Almost all of it is reusable from the existing code. The primary
> > difference is we need to do even less in the interrupt handler, since
> > inte
On Thu, Feb 06, 2014 at 11:54:44AM -0200, Rodrigo Vivi wrote:
> On Wed, Jan 29, 2014 at 2:25 AM, Ben Widawsky
> wrote:
> > It is tested and looking fairly stable now, so turn it on. It wasn't
> > intentionally turned off originally :P
> >
> > Signed-off-by: Ben
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