add a WARN_ON() if we find
> > > > ourselves with a device without any rings.
> > > >
> > > > Fixes: 73ae478cdf6a ("drm/i915: Replace has_bsd/blt/vebox with a mask")
> > > > Fixes: 88d2ba2e95c8 ("drm/i915: Unify engine init loop")
&g
-by: Ben Widawsky
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GLK for
pipe C (see bug 104096).
A relevant discussion is archived at:
https://lists.freedesktop.org/archives/intel-gfx/2017-December/150646.html
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104096
Signed-off-by: Gabriel Krisman Bertazi
Cc: Ben Widawsky
Reviewed-by: Ben Widawsky
On 17-12-17 22:45:13, Gabriel Krisman Bertazi wrote:
Hi Ben and list folks,
I've been investigating some CI failures with the kms_ccs testcase in
the GLK hardware. The original bug is linked below, but there are other
more basic tests failing when trying CCS on pipe C.
https://bugs.freedeskto
On 17-04-06 14:53:50, Ceraolo Spurio, Daniele wrote:
On 06/04/17 12:15, Rodrigo Vivi wrote:
From: Ben Widawsky
The docs are not yet correct, so I cannot provide a reference to it. In the
current docs, the size is actually smaller than SKL. This seems unlikely given
that in another part of
Updated blob layout (Rob, Daniel, Kristian, xerpi)
Cc: Rob Clark
Cc: Daniel Stone
Cc: Kristian H. Kristensen
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/drm_mode_config.c | 7 +++
drivers/gpu/drm/drm_plane.c | 119 ++
include/drm
v2: A minor addition from Daniel
Cc: Daniel Stone
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/arc/arcpgu_crtc.c | 1 +
drivers/gpu/drm/arm/hdlcd_crtc.c| 1 +
drivers/gpu/drm/arm/malidp_planes.c | 2 +-
drivers/gpu/drm/armada/armada_crtc.c
. Kristensen
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_display.c | 131 +--
drivers/gpu/drm/i915/intel_sprite.c | 76 +++-
2 files changed, 201 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b
On 17-05-03 14:45:26, Daniel Stone wrote:
Hi Liviu,
On 3 May 2017 at 11:34, Liviu Dudau wrote:
On Tue, May 02, 2017 at 10:14:26PM -0700, Ben Widawsky wrote:
v2: A minor addition from Daniel
You are *really* pushing your luck by not Cc-ing *any* of the maintainers of
the drivers you touch
s not the only IP capable of producing AFBC data, so there might be
another driver
in the making that will be open source.
Best regards,
Liviu
But besides that, it works
perfectly fine for arm render compression format too.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.c
On 17-05-10 18:24:52, Liviu Dudau wrote:
On Wed, May 10, 2017 at 09:34:40AM -0700, Ben Widawsky wrote:
On 17-05-03 18:30:07, Liviu Dudau wrote:
> On Wed, May 03, 2017 at 06:45:05PM +0200, Daniel Vetter wrote:
> > On Wed, May 03, 2017 at 03:52:23PM +0100, Liviu Dudau wrote:
> > &
On 17-05-03 14:15:15, Liviu Dudau wrote:
On Tue, May 02, 2017 at 10:14:27PM -0700, Ben Widawsky wrote:
Updated blob layout (Rob, Daniel, Kristian, xerpi)
Cc: Rob Clark
Cc: Daniel Stone
Cc: Kristian H. Kristensen
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/drm_mode_config.c | 7
attributes {
u8 slice_count;
u8 eu_total; /* This is sort of useless since if eu_total isn't
trivially
* eu_per_subslice * subslice_count * slice_count, then we
* need to know exactly which subslice is missing EUs. */
str
On Wed, Oct 21, 2015 at 06:40:32PM +0300, Imre Deak wrote:
> Move all slice/subslice/eu related properties to the sseu_dev_info
> struct.
>
> No functional change.
>
> Signed-off-by: Imre Deak
Reviewed-by: Ben Widawsky
> ---
> drivers/gpu/drm/i915
On Wed, Oct 21, 2015 at 06:40:33PM +0300, Imre Deak wrote:
> Signed-off-by: Imre Deak
Reviewed-by: Ben Widawsky
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 55
> +++--
> 1 file changed, 29 insertions(+), 26 deletions(-)
>
> diff --git a
44
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -783,7 +783,7 @@ struct intel_csr {
> #define SEP_SEMICOLON ;
>
> struct sseu_dev_info {
> - u8 slice_total;
> + u8 slice_mask;
> u8 subslice_total;
> u8 subslice_per_slice;
> u8 eu_total;
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> b/drivers/gpu/drm/i915/intel_lrc.c
> index 8a55f8a..4130ff1 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -2202,7 +2202,7 @@ make_rpcs(struct drm_device *dev)
> */
> if (INTEL_INFO(dev)->sseu.has_slice_pg) {
> rpcs |= GEN8_RPCS_S_CNT_ENABLE;
> - rpcs |= INTEL_INFO(dev)->sseu.slice_total <<
> + rpcs |= hweight32(INTEL_INFO(dev)->sseu.slice_mask) <<
^ hweight8?
> GEN8_RPCS_S_CNT_SHIFT;
> rpcs |= GEN8_RPCS_ENABLE;
> }
I'm not positive if hweight32 is actually okay on an 8bit type. I remember Ville
correcting me once on this, but I can't remember it's correct. Assuming
hweight32 is fine to use, with or without my recommendations, this is:
Reviewed-by: Ben Widawsky
--
Ben Widawsky, Intel Open Source Technology Center
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84,8 +784,7 @@ struct intel_csr {
>
> struct sseu_dev_info {
> u8 slice_mask;
> - u8 subslice_total;
> - u8 subslice_per_slice;
> + u8 subslice_mask;
I know we have situations for GT1 parts where the number of subslices per slice
is less than that of the same GEN of a different SKU. AFAIK, this never carries
over into higher GT (ie. GT2 would always have 3 subslices per slice, but GT1
may have 2 subslices per slice). However. I am not certain this is the case - I
hope you've double checked that.
> u8 eu_total;
> u8 eu_per_subslice;
> /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
> @@ -795,6 +794,11 @@ struct sseu_dev_info {
> u8 has_eu_pg:1;
> };
>
> +static inline unsigned int sseu_subslice_total(const struct sseu_dev_info
> *sseu)
> +{
> + return hweight32((sseu)->slice_mask) * hweight32((sseu)->subslice_mask);
hweight8
basically s/hweight32/hweight8 on the whole file
> +}
> +
> struct intel_device_info {
> u32 display_mmio_offset;
> u16 device_id;
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> b/drivers/gpu/drm/i915/intel_lrc.c
> index 4130ff1..158f008 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -2209,7 +2209,7 @@ make_rpcs(struct drm_device *dev)
>
> if (INTEL_INFO(dev)->sseu.has_subslice_pg) {
> rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
> - rpcs |= INTEL_INFO(dev)->sseu.subslice_per_slice <<
> + rpcs |= hweight32(INTEL_INFO(dev)->sseu.subslice_mask) <<
> GEN8_RPCS_SS_CNT_SHIFT;
> rpcs |= GEN8_RPCS_ENABLE;
> }
Reviewed-by: Ben Widawsky
--
Ben Widawsky, Intel Open Source Technology Center
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re too.
> u8 subslice_7eu = INTEL_INFO(dev)->sseu.subslice_7eu[s];
>
> stat->eu_total -= hweight8(subslice_7eu);
6 & 7 are:
Reviewed-by: Ben Widawsky
1-7 are also:
Tested-by: Ben Widawsky
--
Ben Widawsky, Intel Open Source Technology Cent
ars up the confusion.
NOTE: This patch was compile tested only.
NOTE2: The modern docs call it MI_STORE_DATA_INDEX not MI_STORE_DWORD_INDEX
Cc: Oscar Mateo
Cc: Damien Lespiau
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_lrc.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
di
On Wed, Dec 16, 2015 at 12:18:20AM +, Chris Wilson wrote:
> On Tue, Dec 15, 2015 at 04:13:49PM -0800, Ben Widawsky wrote:
> > This has been incorrect since the original commit from Oscar Mateo here:
> > commit 4da46e1e5bb7e7396fad172cdaffbe496562f3d8
> > Author: Oscar M
It is unclear if this is even required on BXT.
Cc: Imre Deak
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_lrc.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 519cea32
It is unclear if this is even required on BXT.
v2: Make sure to set the default value to false. Uncertain how my compiler
doesn't complain with v1.
Cc: Imre Deak
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_lrc.c | 16
1 file changed, 8 insertions(
On Thu, Dec 17, 2015 at 10:49:24PM +0200, Imre Deak wrote:
> On Thu, 2015-12-17 at 09:49 -0800, Ben Widawsky wrote:
> > It is unclear if this is even required on BXT.
>
> I'm not sure either, I only added it on the premise that it was marked
> as SKL+ originally in BSpec.
Compile tested only.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_lrc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 42a7be1..a9bc207 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
On Fri, Dec 18, 2015 at 10:17:49AM +0200, Mika Kuoppala wrote:
> Ben Widawsky writes:
>
> > Compile tested only.
> >
> > Signed-off-by: Ben Widawsky
> > ---
> > drivers/gpu/drm/i915/intel_lrc.c | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deleti
From: Ben Widawsky
Signed-off-by: Ben Widawsky
---
intel/intel_chipset.h | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 514f659..41fc0da 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
.
NOTE: I manually retyped this from a test machine. So I haven't even compiled
this exact patch.
Cc: Chris Wilson
Cc: Kristian Høgsberg
Cc: Jordan Justen
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/
On Tue, Feb 09, 2016 at 11:30:34AM +, Dave Gordon wrote:
> On 09/02/16 00:20, Kristian Høgsberg wrote:
> >On Fri, Feb 5, 2016 at 5:48 PM, Ben Widawsky
> > wrote:
> >>This behavior of checking for a shmem backed GEM object was introduced here:
> >>commit 4c914c0
: I manually retyped this from a test machine. So I haven't even compiled
this exact patch.
v2: Use same logic as from a2a4f916c2f (Kristian, Dave Gordon)
Cc: Chris Wilson
Cc: Kristian Høgsberg
Cc: Dave Gordon
Signed-off-by: Ben Widawsky
Tested-by: Jordan Justen (v1)
Reviewed-by: J
Do you guys get the CI mails? This version has regressions. v1 did not. I don't
know what to trust.
On Tue, Feb 09, 2016 at 11:44:12AM -0800, Ben Widawsky wrote:
> This behavior of checking for a shmem backed GEM object was introduced here:
> commit 4c914c0c7c787b8f730128a8cdcca
On Wed, Feb 10, 2016 at 04:23:08PM +, Chris Wilson wrote:
> On Wed, Feb 10, 2016 at 07:42:23AM -0800, Ben Widawsky wrote:
> > Do you guys get the CI mails? This version has regressions. v1 did not. I
> > don't
> > know what to trust.
>
> I didn't even
Signed-off-by: Ben Widawsky
---
src/i915_pciids.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/i915_pciids.h b/src/i915_pciids.h
index f970209..4d1c11d 100644
--- a/src/i915_pciids.h
+++ b/src/i915_pciids.h
@@ -279,7 +279,8 @@
#define INTEL_SKL_GT3_IDS(info
down by default on HSW, and prints a warning. An
upcoming patch will provide an override for the insane.
References:
https://lists.freedesktop.org/archives/mesa-dev/2013-July/041692.html
Signed-off-by: Ben Widawsky
---
man/intel_gpu_top.man | 2 ++
tools/intel_gpu_top.c | 28
Signed-off-by: Ben Widawsky
---
man/intel_gpu_top.man | 3 +++
tools/intel_gpu_top.c | 25 +
2 files changed, 20 insertions(+), 8 deletions(-)
diff --git a/man/intel_gpu_top.man b/man/intel_gpu_top.man
index d90a7ee..be0f1be 100644
--- a/man/intel_gpu_top.man
+++ b/man
appens with the non-CCS Y vs. Yf as well. If
desired, we could potentially return a unique pointer for each
pixel_format+tiling+ccs combination, in which case we immediately be
able to tell if any of that stuff changed by just comparing the
pointers. But that does sound a bit wasteful space wise.
Cc
; | ABS { $$ = 1; }
> > ;
> >
> > -execsize: /* empty */ %prec EMPTEXECSIZE
> > +execsize: %empty /* empty */ %prec EMPTEXECSIZE
> > {
> > $$ = ffs(program_defaults.execute_size) - 1;
> > }
> > @@ -2902,7 +2
On 16-09-15 17:30:10, Mika Kuoppala wrote:
Imre Deak writes:
From: Ben Widawsky
v2: (Imre)
- Access only subslices that are known to exist.
- Reset explictly the MCR selector to slice/sub-slice ID 0 after the
readout.
- Use the subslice INSTDONE bits for the hangcheck/subunits-stuck
his with this big
> blanket back then already, as E0 vs F0 discrepancy was suspicious
> enough.
>
> Previously the WaForceEnableNonCoherent has been tied to
> context non-coherence, atleast in relevant hsds. So keep this tie
> and extended this alongside.
>
> Cc: Abdiel
The two behavioral changes here are the correct detection of the eDRAM size on
gen9 (SKL + KBL), and unconditional printing of the eLLC size.
Cc: Eero Tamminen
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_uncore.c | 16 +---
1 file changed, 13 insertions(+), 3
For debug and development purposes only.
Cc: Mika Kuoppala
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_debugfs.c | 13 +
drivers/gpu/drm/i915/i915_gpu_error.c | 3 +++
drivers/gpu/drm/i915/i915_params.c | 6 ++
drivers/gpu/drm/i915/i915_params.h
On Wed, Apr 13, 2016 at 06:45:32PM +0100, Dave Gordon wrote:
> On 13/04/16 17:57, Ben Widawsky wrote:
> > For debug and development purposes only.
> >
> > Cc: Mika Kuoppala
> > Signed-off-by: Ben Widawsky
> > ---
> > drivers/gpu/drm/i915/i915_debugfs.c
On Thu, Apr 14, 2016 at 11:14:48AM +0300, Jani Nikula wrote:
> On Thu, 14 Apr 2016, Jani Nikula wrote:
> > On Wed, 13 Apr 2016, Ben Widawsky wrote:
> >> The two behavioral changes here are the correct detection of the eDRAM
> >> size on
> >> gen9 (SKL + KBL
On Thu, Apr 14, 2016 at 07:48:13AM -0700, Ben Widawsky wrote:
> On Thu, Apr 14, 2016 at 11:14:48AM +0300, Jani Nikula wrote:
> > On Thu, 14 Apr 2016, Jani Nikula wrote:
> > > On Wed, 13 Apr 2016, Ben Widawsky wrote:
> > >> The two behavioral changes here are the
On Thu, Apr 14, 2016 at 11:27:25AM +0300, Jani Nikula wrote:
> On Wed, 13 Apr 2016, Ben Widawsky wrote:
> > +module_param_named_unsafe(disable_firmware_loading,
> > i915.disable_firmware_loading, uint, 0400);
> > +MODULE_PARM_DESC(disable_firmware_loading,
> > +
ces: https://patchwork.kernel.org/patch/9482393/
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/arc/arcpgu_crtc.c | 1 +
drivers/gpu/drm/arm/hdlcd_crtc.c| 1 +
drivers/gpu/drm/arm/malidp_planes.c | 2 +-
drivers/gpu/drm/armada/armada_crtc.c
suspect on
this table let's provide a mechanism to disable these
cache leves on this private table (PPAT).
Cc: Ben Widawsky
Cc: Daniele Ceraolo Spurio
Signed-off-by: Rodrigo Vivi
I think this is a cool idea, it could equally be achieved by modifying the PTE
encoding function. In my
>
> v2: Drop the 'dev' argument from the hook
> v3: Include the description of the CCS surface layout
>
> Cc: Vandana Kannan
> Cc: Daniel Vetter
> Cc: Ben Widawsky
> Cc: Jason Ekstrand
> Reviewed-by: Ben Widawsky
> Signed-off-by: Ville Syrjälä
> ---
> dri
discretion, the contents of the error state. although
compressed, are allocated with GFP_ATOMIC (i.e. limited) and kept for all
eternity (until the error state is destroyed).
Based on an earlier patch by Ben Widawsky
Signed-off-by: Chris Wilson
Cc: Ben Widawsky
Cc: Matt Turner
Haven't test
On Tue, Oct 06, 2015 at 08:51:13PM +, Rodrigo Vivi wrote:
> cc'ing Ben to get his opinion...
>
Of course anything is possible wrt the delta of KBL features vs SKL. With the
knowledge we have, we can make a pretty educated guess that there will be no
changes, and with an equally high level of
This prevents the simulator from barfing when it sees commands from another
ring. I've been using this locally for a very long time.
Cc: Kristian Høgsberg
Signed-off-by: Ben Widawsky
---
tools/aubdump.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/aubdump.c b/
gt; >
> > tools/null_state/gen9: Send atleast one valid component in VF state
> >
> > to honor the Reviewed-by, send all four components as noted by
> > Ben in his review.
> >
> > Cc: Ben Widawsky
> > Cc: Arun Siluvery
> > Signed
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_lrc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index ca5c0e8..973487a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm
On Mon, Jan 04, 2016 at 09:12:11PM +0100, Pavel Machek wrote:
> Hi!
>
> > > I then ran a git bissect between v4.0 and v4.1 from Linus's tree and
> > > found the "guilty" commit was
> > >
> > > commit 317b4e903636305cfe702ab3e5b3d68547a69e7
Since we extracted it for use in error state, we may as well use it in debugfs
too.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_debugfs.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915
There is no point in emitting a WARN since the backtrace will always be the
same. Errors have actually become easier to spot given the large number of WARNs
which exist today in modesetting paths.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_lrc.c | 4 +++-
1 file changed, 3
This is a useful thing to have around as a function because the mechanism may
change in the future.
There is a net increase in LOC here, and it will continue to be the case on GEN8
and GEN9 - but future GENs may have an alternate mechanism for doing this.
Signed-off-by: Ben Widawsky
to land as much as possible - but
I'll live without it.
Ben Widawsky (5):
drm/i915: Cleanup some of the CSB handling
drm/i915: change WARN to ERROR in CSB count
drm/i915: Extract CSB status read
drm/i915: Add basic execlist info to error state
drm/i915: Use CSB helper in debugfs
drive
3 Status: 0x00010018
Context 4 Status: 0x0001
Context 5 Status: 0x009d0018
hangcheck: hung [40]
bsd command stream:
START: 0x00039000
HEAD: 0x0018
...
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_drv.h | 7 ++-
drivers/gpu
This is safe because right above this, we
already did a modulus operation.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 +++---
drivers/gpu/drm/i915/intel_lrc.c| 15 +--
drivers/gpu/drm/i915/intel_lrc.h| 18 --
3 files changed, 28 ins
15/intel_ringbuffer.h
> b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 566b0ae..62b4e1b 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -122,6 +122,8 @@ struct intel_ringbuffer {
>* we can detect new retirements.
>*/
> u32 last_retired_head;
> +
> + int wa_tail_dwords;
> };
>
> struct intel_context;
> --
> 2.4.3
>
--
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On 17-05-03 17:08:27, Daniel Vetter wrote:
On Tue, May 02, 2017 at 10:14:27PM -0700, Ben Widawsky wrote:
Updated blob layout (Rob, Daniel, Kristian, xerpi)
Cc: Rob Clark
Cc: Daniel Stone
Cc: Kristian H. Kristensen
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/drm_mode_config.c | 7
viu)
* Fix data types (Ben)
* Make the blob part of uapi (Daniel)
Cc: Rob Clark
Cc: Daniel Stone
Cc: Kristian H. Kristensen
Cc: Liviu Dudau
Signed-off-by: Ben Widawsky
Reviewed-by: Daniel Stone
---
drivers/gpu/drm/drm_mode_config.c | 7 +++
drivers/gpu/drm/drm_plane.c |
-by: Daniel Stone (v2)
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/arc/arcpgu_crtc.c | 1 +
drivers/gpu/drm/arm/hdlcd_crtc.c| 1 +
drivers/gpu/drm/arm/malidp_planes.c | 2 +-
drivers/gpu/drm/armada/armada_crtc.c| 1 +
drivers/gpu/drm/arm
. Kristensen
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_display.c | 131 +--
drivers/gpu/drm/i915/intel_sprite.c | 76 +++-
2 files changed, 201 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b
On 17-05-17 13:31:44, Daniel Vetter wrote:
On Tue, May 16, 2017 at 02:19:12PM -0700, Ben Widawsky wrote:
On 17-05-03 17:08:27, Daniel Vetter wrote:
> On Tue, May 02, 2017 at 10:14:27PM -0700, Ben Widawsky wrote:
> > +struct drm_format_modifier_blob {
> > +#define FORMAT
On 17-05-17 11:17:57, Liviu Dudau wrote:
On Tue, May 16, 2017 at 02:31:24PM -0700, Ben Widawsky wrote:
This is the plumbing for supporting fb modifiers on planes. Modifiers
have already been introduced to some extent, but this series will extend
this to allow querying modifiers per plane. Based
On 17-05-17 01:06:16, Emil Velikov wrote:
Hi Ben,
On 16 May 2017 at 22:31, Ben Widawsky wrote:
Updated blob layout (Rob, Daniel, Kristian, xerpi)
v2:
* Removed __packed, and alignment (.+)
* Fix indent in drm_format_modifier fields (Liviu)
* Remove duplicated modifier > 64 check (Li
On 17-05-17 01:20:50, Emil Velikov wrote:
Hi Ben,
A couple of small questions/suggestions that I hope you find useful.
Please don't block any of this work based on my comments.
On 16 May 2017 at 22:31, Ben Widawsky wrote:
+static bool intel_primary_plane_format_mod_supported(s
On 17-06-22 10:42:45, Srivatsa, Anusha wrote:
Coffee Lake has a gen9 graphics following KBL.
From 3D perspective, CFL is a clone of KBL/SKL features.
v2: Change commit message, correct alignment
v3: Update IDs.
v4: Initialize l3_banks, correct nomenclature
Cc: Anuj Phogat
Cc: Rodrigo Vivi
S
ent adjustments (Liviu)
v5: Some new platforms added due to rebase
v6: Add some missed plane inits (or maybe they're new - who knows at
this point) (Daniel)
Signed-off-by: Ben Widawsky
Reviewed-by: Daniel Stone (v2)
Reviewed-by: Liviu Dudau
---
drivers/gpu/drm/arc/arcpgu_crtc.c
v2:
Support sprite plane.
Support pipe C/D limitation on GEN9.
This requires rebase on the correct Ville patches
Cc: Daniel Stone
Cc: Kristian Høgsberg
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_display.c | 34 +--
drivers/gpu/drm/i915
viu)
* Fix data types (Ben)
* Make the blob part of uapi (Daniel)
v3:
Remove unused ret field.
Change i, and j to unsigned int (Emil)
v4:
Use plane->modifier_count instead of recounting (Daniel)
Cc: Rob Clark
Cc: Kristian H. Kristensen
Signed-off-by: Ben Widawsky
Reviewed-by: Daniel Ston
of things came
up and it took a while to spin this rev. Nothing was missing intentionally.
[1] The bitmask is used to show the connection between which modifiers are
supported by which formats.
Ben Widawsky (4):
drm: Plumb modifiers through plane init
drm: Create a format/modifier blob
drm
funcs (Emil)
- Use unreachable (Emil)
v7:
- Only allow Intel modifiers and LINEAR (Ben)
v8
- Fix spite assert introduced in v6 (Daniel)
Cc: Ville Syrjälä
Cc: Kristian H. Kristensen
Cc: Emil Velikov
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_display.c | 136
We don't yet have optimal MOCS settings, but we have enough to know how
to at least determine when we might have non-optimal settings within our
driver.
Signed-off-by: Ben Widawsky
---
src/intel/vulkan/anv_device.c | 12
src/intel/vulkan/anv_private.h
Signed-off-by: Ben Widawsky
---
src/intel/drm/i915_drm.h | 8
1 file changed, 8 insertions(+)
diff --git a/src/intel/drm/i915_drm.h b/src/intel/drm/i915_drm.h
index c26bf7c125..69e38ce89f 100644
--- a/src/intel/drm/i915_drm.h
+++ b/src/intel/drm/i915_drm.h
@@ -431,6 +431,14 @@ typedef
From: Ben Widawsky
Starting with GEN9, Memory Object Control State (MOCS) becomes an index
into a table as opposed to the direct programming within the command.
The table has 62 usable entries (ie 6 bits can represent all settings),
and each buffer type may use one of these 62 entries to
mmit c9b0481bce24af032386701de0266eb5bc24e988
Author: Ben Widawsky
Date: Fri Apr 8 10:21:16 2016 -0700
i965: Use PTE mocs
Signed-off-by: Ben Widawsky
diff --git a/src/mesa/drivers/dri/i965/brw_mocs.c
b/src/mesa/drivers/dri/i965/brw_mocs.c
index 5df154eb86..b7bfdab671 100644
--- a/s
On 17-07-06 14:06:24, Vivi, Rodrigo wrote:
No change on render context size is required for Gen10.
So this patch doesn't change the default behaviour,
but only avoid the missing_case message.
Cc: Ben Widawsky
Signed-off-by: Rodrigo Vivi
Reviewed-by: Ben Widawsky
[snip]
--
Ben Wid
On 17-07-07 11:34:48, Chris Wilson wrote:
Quoting Ben Widawsky (2017-07-07 00:27:01)
drivers/gpu/drm/i915/i915_drv.c | 3 +++
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 13 +
include/uapi/drm/i915_drm.h | 8
4 files changed, 22
On 17-07-07 09:23:26, Jason Ekstrand wrote:
On Fri, Jul 7, 2017 at 3:34 AM, Chris Wilson
wrote:
Quoting Ben Widawsky (2017-07-07 00:27:01)
> drivers/gpu/drm/i915/i915_drv.c | 3 +++
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 13 +
>
hanging this, but tell me what you want.
BUILD_BUG_ON sounds good to me regardless.
[snip]
--
Ben Widawsky, Intel Open Source Technology Center
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Marc, please file a bug on freedesktop.org.
We expect the modesetting driver to work well and if it's not, it should have a
bug associated with it.
Sorry for your frustration.
On 17-07-17 12:22:00, Marc MERLIN wrote:
Ok, there must be a problem, sent 5 messages to the list with clear details
o
On 17-07-14 22:10:15, Ville Syrjälä wrote:
On Fri, Jul 14, 2017 at 11:41:49AM -0700, Ben Widawsky wrote:
On 17-06-29 22:49:44, Ville Syrjälä wrote:
[snip]
>
>... but here it's ALIGN(formats_offset+formats_size). I think we should
>be aligning the same thing in both case
On 17-07-07 09:28:08, Jason Ekstrand wrote:
On Thu, Jul 6, 2017 at 4:27 PM, Ben Widawsky wrote:
We don't yet have optimal MOCS settings, but we have enough to know how
to at least determine when we might have non-optimal settings within our
driver.
Signed-off-by: Ben Widawsky
---
src/
On 17-06-29 23:02:08, Ville Syrjälä wrote:
On Fri, Jun 23, 2017 at 09:45:44AM -0700, Ben Widawsky wrote:
v2:
Support sprite plane.
Support pipe C/D limitation on GEN9.
This requires rebase on the correct Ville patches
Cc: Daniel Stone
Cc: Kristian Høgsberg
Signed-off-by: Ben Widawsky
(Ville)
Make BUILD_BUG_ON for blob header size
Cc: Rob Clark
Cc: Kristian H. Kristensen
Signed-off-by: Ben Widawsky
Reviewed-by: Daniel Stone (v2)
Reviewed-by: Liviu Dudau (v2)
Reviewed-by: Emil Velikov (v3)
---
drivers/gpu/drm/drm_mode_config.c | 7
drivers/gpu/drm/drm_plane.c
interface will allow clients to create buffers for
scanout with a good set of modifiers, and later import those buffers (through
EGL already, and Vulkan WSI later) into a graphics runtime. EGL/WSI will provide
similar interfaces for rendering - modifiers which can be used for rendering.
Ben Widawsky (4
ent adjustments (Liviu)
v5: Some new platforms added due to rebase
v6: Add some missed plane inits (or maybe they're new - who knows at
this point) (Daniel)
Signed-off-by: Ben Widawsky
Reviewed-by: Daniel Stone (v2)
Reviewed-by: Liviu Dudau
---
drivers/gpu/drm/arc/arcpgu_crtc.c
)
- rename local variable intel_format_modifiers to modifiers (Ville)
- actually use sprite modifiers
- split out modifier/formats by platform (Ville)
Cc: Ville Syrjälä
Cc: Kristian H. Kristensen
Reviewed-by: Emil Velikov (v8)
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915
v2:
Support sprite plane.
Support pipe C/D limitation on GEN9.
v3:
Rename structure (Ville)
Handle GLK (Ville)
This requires rebase on the correct Ville patches
Cc: Daniel Stone
Cc: Kristian Høgsberg
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_display.c | 30
IDENCY 40
+#define I915_PMU_RC6p_RESIDENCY41
+#define I915_PMU_RC6pp_RESIDENCY 42
+
/* Each region is a minimum of 16k, and there are at most 255 of them.
*/
#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
diff --git a/kernel/events/core.c b/kernel/events/core.c
index e46eba8cd1b7..7b8c6dce1078 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -7386,6 +7386,7 @@ int perf_event_overflow(struct perf_event *event,
{
return __perf_event_overflow(event, 1, data, regs);
}
+EXPORT_SYMBOL_GPL(perf_event_overflow);
/*
* Generic software event infrastructure
--
2.9.4
--
Ben Widawsky, Intel Open Source Technology Center
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othing */
+ } else {
+ engine = user_engine_map[engine];
+ val = i915->engine[engine]->pmu_sample[sample];
+ }
} else switch (event->attr.config) {
case I915_PMU_ACTUAL_FREQUENCY:
val = i915-&g
vent, &data, NULL);
+ perf_event_overflow(event, &data, regs);
period = max_t(u64, 1, event->hw.sample_period);
hrtimer_forward_now(hrtimer, ns_to_ktime(period));
--
2.9.4
--
Ben Widawsky, Intel Open Source Technology Center
___
Inte
TDP though,
it wouldn't need to actually be included, so we could perhaps leave room for
per-engine.
--
Ben Widawsky, Intel Open Source Technology Center
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that does sound a bit wasteful space wise.
v2: Drop the 'dev' argument from the hook
v3: Include the description of the CCS surface layout
v4: Pretend CCS tiles are regular 128 byte wide Y tiles (Jason)
Cc: Daniel Vetter
Cc: Ben Widawsky
Cc: Jason Ekstrand
Reviewed-by: Ben Widaw
ent adjustments (Liviu)
v5: Some new platforms added due to rebase
v6: Add some missed plane inits (or maybe they're new - who knows at
this point) (Daniel)
v7: Add sun8i (Daniel)
Signed-off-by: Ben Widawsky
Reviewed-by: Daniel Stone (v2)
Reviewed-by: Liviu Dudau
Acked-by: Philippe Cornu
rotation is not supported in combination
with
decompression either.
This patch may contain work from at least the following people:
* Vandana Kannan
* Daniel Vetter
* Ben Widawsky
v2: Deal with display workaro
v2:
Support sprite plane.
Support pipe C/D limitation on GEN9.
v3:
Rename structure (Ville)
Handle GLK (Ville)
This requires rebase on the correct Ville patches
Cc: Daniel Stone
Cc: Kristian Høgsberg
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_display.c | 30
(Ville)
Make BUILD_BUG_ON for blob header size
Cc: Rob Clark
Cc: Kristian H. Kristensen
Signed-off-by: Ben Widawsky
Reviewed-by: Daniel Stone (v2)
Reviewed-by: Liviu Dudau (v2)
Reviewed-by: Emil Velikov (v3)
---
drivers/gpu/drm/drm_mode_config.c | 7
drivers/gpu/drm/drm_plane.c
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