side as well.
[1] https://lists.freedesktop.org/archives/beignet/2016-June/007698.html
[2] https://lists.freedesktop.org/archives/beignet/2016-June/007699.html
Cc: Winiarski, Michal
Cc: Zou, Nanhai
Cc: Yang, Rong R
Cc: Tim Gore
Cc: Jeff McGee
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm
side as well.
v2: fix compile error
[1] https://lists.freedesktop.org/archives/beignet/2016-June/007698.html
[2] https://lists.freedesktop.org/archives/beignet/2016-June/007699.html
Cc: Winiarski, Michal
Cc: Zou, Nanhai
Cc: Yang, Rong R
Cc: Tim Gore
Cc: Jeff McGee
Signed-off-by: Arun Siluvery
On 01/07/2016 12:56, Chris Wilson wrote:
On Fri, Jul 01, 2016 at 11:43:02AM +0100, Arun Siluvery wrote:
Pooled EU is a bxt only feature and kernel changes are already merged. This
feature is not yet exposed to userspace as the support was not yet
available. Beignet team expressed interest and
On 30/06/2016 09:43, Song, Ruiling wrote:
LGTM
Ruiling
Could you please let me know whether these patches are merged/yet to be
merged?
I have submitted kernel patch which is ready to be merged but we would
like to know if userspace bits are merged or not?
https://lists.freedesktop.org/ar
dex % CACHELINE_DWORDS)
wa_ctx_emit(batch, index, MI_NOOP);
looks good to me,
Reviewed-by: Arun Siluvery
regards
Arun
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On 15/06/2016 09:19, Yang Rong wrote:
Update kernel interface with new I915_GETPARAM ioctl entries for
pooled EU and min no. of eus in a pool. Add a wrapping function
for each parameter. Userspace drivers need these values when decide
the thread count. This kernel enabled pooled eu by default for
.
Reviewed-by: Arun Siluvery
regards
Arun
drivers/gpu/drm/i915/intel_lrc.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 676b532..017b25c 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
On 15/07/2016 08:08, Yang Rong wrote:
Update kernel interface with new I915_GETPARAM ioctl entries for
pooled EU and min no. of eus in a pool. Add a wrapping function
for each parameter. Userspace drivers need these values when decide
the thread count. This kernel enabled pooled eu by default for
On 16/06/2016 15:44, Mika Kuoppala wrote:
Add WaDisableGatherAtSetShaderCommonSlice for all gen9 as stated
by bspec.
References: HSD#2135817
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_lrc.c | 7 +++
2 files changed, 8 insertions(+
r condition and we fallback to
full gpu reset.
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/intel_lrc.c | 116 +++
drivers/gpu/drm/i915/intel_lrc.h | 2 +
2 files changed, 118 insertions(+)
diff --git a/drive
that caused the hang
- reset itself failed for some reason
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Tomas Elf
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_drv.c | 55 +
drivers/gpu/drm/i915/i915_drv.h | 3 ++
drivers/gpu/drm
Now that we track reset progress using separate set of flags, update it to
account for engine reset as well.
A bit corresponding engine->id is set if reset is in progress for that
engine. Bit0 is for full gpu reset.
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_drv.h |
In preparation for engine reset work update this parameter to handle more
than one type of reset. Default at the moment is still full gpu reset.
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_params.c | 6 +++---
drivers/gpu/drm/i915/i915_params.h | 2 +-
2 files changed, 4
during reset
itself i.e. we no longer emit requests during reset, is that we can use
the atomic updates of the state flags to ensure that only one reset
worker is active.
Signed-off-by: Chris Wilson
Cc: Arun Siluvery
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_drv.c | 16
same
behaviour is adapted but reset event is only dispatched once even when
multiple engines are hung. Finally once reset is complete we send reset
done event as usual.
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Ian Lister
Signed-off-by: Tomas Elf
Signed-off-by: Arun Siluvery
---
driver
We stop the engine during reset and recovery so after a successful reset
the request that caused the hang would've been removed from the queue so we
can now restart submissions to elsp.
Cc: Mika Kuoppala
Signed-off-by: Tomas Elf
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm
.
Arun Siluvery (9):
drm/i915: Update i915.reset to handle engine resets
drm/i915/tdr: Update reset_in_progress to account for engine reset
drm/i915/tdr: Modify error handler for per engine hang recovery
drm/i915/tdr: Identify hung request and drop it
drm/i915/tdr: Restart submission after
A new variable is added to export the reset counts to debugfs, this
includes full gpu reset and engine reset count. This is useful for tests
where they areexpected to trigger reset; these counts are checked before
and after the test to ensure the same.
Signed-off-by: Arun Siluvery
---
drivers
Everything in place, flip the switch.
This feature is available only from Gen8, for previous gen devices driver
falls back to legacy full gpu reset.
Signed-off-by: Tomas Elf
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_params.c | 4 ++--
1 file changed, 2 insertions(+), 2
Driver maintains count of how many times a given engine is reset, useful to
capture this in error state also. It gives an idea of how engine is coping
up with the workloads it is executing before this error state.
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_drv.h | 7
unnecessary. To
avoid this we check if the engine is already prepared, if so we just exit
from that point.
Signed-off-by: Mika Kuoppala
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/intel_uncore.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm
On 26/07/2016 22:52, Chris Wilson wrote:
On Tue, Jul 26, 2016 at 05:40:49PM +0100, Arun Siluvery wrote:
Now that we track reset progress using separate set of flags, update it to
account for engine reset as well.
A bit corresponding engine->id is set if reset is in progress for that
eng
On 26/07/2016 22:51, Chris Wilson wrote:
On Tue, Jul 26, 2016 at 05:40:53PM +0100, Arun Siluvery wrote:
This change implements support for per-engine reset as an initial, less
intrusive hang recovery option to be attempted before falling back to the
legacy full GPU reset recovery mode if
On 27/07/2016 12:41, Chris Wilson wrote:
On Wed, Jul 27, 2016 at 12:16:04PM +0100, Arun Siluvery wrote:
On 26/07/2016 22:52, Chris Wilson wrote:
A totally unexplained change. If it is because you think to want to break
waiters on struct_mutex, try again.
So you don't want error->
On 26/07/2016 22:37, Chris Wilson wrote:
On Tue, Jul 26, 2016 at 05:40:51PM +0100, Arun Siluvery wrote:
The current active request is the one that caused the hang so this is
retrieved and removed from elsp queue, otherwise we cannot submit other
workloads to be processed by GPU.
A consistency
On 02/08/2016 07:20, Yang, Rong R wrote:
I sent a new version, could you check this and give comments/ACK?
Cc: Daniel, intel-gfx mailing list.
regards
Arun
Thanks,
Yang Rong
-Original Message-
From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of
Yang Rong
Sent:
E_CHICKEN2,
GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
Reviewed-by: Arun Siluvery
regards
Arun
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start of breadcrumb. This allows us to resume from where we left-off.
Since this request didn't complete normally we also need to cleanup elsp
queue manually.
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
Cc: Arun Siluvery
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c
queue from reset path we can examine these ports, fix
up ringbuffer pointers using the incomplete request and restart submissions
again after reset.
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
Cc: Arun Siluvery
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers
engine
- restart submissions to the engine
If engine reset fails then we fall back to heavy weight full gpu reset
which resets all engines and reinitiazes complete state of HW and SW.
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Tomas Elf
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm
.
v2: ELSP queue request tracking and reset path changes to handle incomplete
requests during reset. Thanks to Chris Wilson for providing these patches.
Arun Siluvery (6):
drm/i915: Update i915.reset to handle engine resets
drm/i915/tdr: Modify error handler for per engine hang recovery
drm
From: Chris Wilson
Not only does it make for good documentation and debugging aide, but it is
also vital for when we want to unwind requests - such as when throwing away
an incomplete request.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/
In preparation for engine reset work update this parameter to handle more
than one type of reset. Default at the moment is still full gpu reset.
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_params.c | 6 +++---
drivers/gpu/drm/i915/i915_params.h | 2 +-
2 files changed, 4
A new variable is added to export the reset counts to debugfs, this
includes full gpu reset and engine reset count. This is useful for tests
where they areexpected to trigger reset; these counts are checked before
and after the test to ensure the same.
Signed-off-by: Arun Siluvery
---
drivers
during reset
itself i.e. we no longer emit requests during reset, is that we can use
the atomic updates of the state flags to ensure that only one reset
worker is active.
Signed-off-by: Chris Wilson
Cc: Arun Siluvery
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_drv.c | 12 +---
drivers
This feature is made available only from Gen8, for previous gen devices
driver uses legacy full gpu reset.
Signed-off-by: Tomas Elf
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_params.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915
done event as usual.
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Ian Lister
Signed-off-by: Tomas Elf
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_drv.c | 26 +
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_irq.c
unnecessary. To
avoid this we check if the engine is already prepared, if so we just exit
from that point.
Signed-off-by: Mika Kuoppala
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/intel_uncore.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm
Driver maintains count of how many times a given engine is reset, useful to
capture this in error state also. It gives an idea of how engine is coping
up with the workloads it is executing before this error state.
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_drv.c | 1
ay of identifying the
context of interest in execlist mode.
For: VIZ-2021
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Dave Gordon
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_gpu_error.c | 46 +--
2
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index eecb870..3209f6a 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
and one other small change.
Arun Siluvery (1):
drm/i915/error: Use yesno() to report iommu enable status
Dave Gordon (1):
drm/i915/error: capture errored context based on request context-id
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_gpu_error.c | 48
ous
sequence of zeros are skipped in the output.
Cc: Mika Kuoppala
Cc: Chris Wilson
Signed-off-by: Armin Reese (v1)
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_debugfs.c | 70 ++---
1 file changed, 58 insertions(+), 12 deletions(-)
diff --git a/
On 26/05/2016 20:59, Mika Kuoppala wrote:
We need this crucial workaround from skl also to all kbl revisions.
Lack of it was causing system hangs on skl enabling so this is
a must have.
References: HSD#2126660
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 13 +
support.
Reviewed-by: Chris Wilson (v2)
Cc: Winiarski, Michal
Cc: Zou, Nanhai
Cc: Yang, Rong R
Cc: Mika Kuoppala
Cc: Chris Wilson
Cc: Armin Reese
Cc: Tim Gore
Signed-off-by: Jeff McGee
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_debugfs.c | 4
drivers/gpu/drm
This is a WA affecting pooled eu which is a bxt specific feature.
Cc: Winiarski, Michal
Cc: Zou, Nanhai
Cc: Yang, Rong R
Cc: Jeff McGee
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 6 ++
2 files changed, 7
related WA patches are also included in this series.
[1] https://lists.freedesktop.org/archives/intel-gfx/2016-May/095890.html
Arun Siluvery (3):
drm/i915:bxt: Enable Pooled EU support
drm/i915/bxt: Add WaEnablePooledEuFor2x6
drm/i915/bxt: Add WaDisablePooledEuLoadBalancingFix
drivers/gpu
ds to be exported
using getparam ioctls.
Cc: Winiarski, Michal
Cc: Zou, Nanhai
Cc: Yang, Rong R
Cc: Tim Gore
Cc: Jeff McGee
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_dma.c | 10 ++
drivers/gpu/drm/i915/i915_drv.c | 2 +-
2 files changed, 11 insertions(+), 1 del
ds to be exported
using getparam ioctls.
v2: s/subslice_total/subslice_per_slice as it is a more logical field (Mika)
Reviewed-by: Mika Kuoppala
Cc: Winiarski, Michal
Cc: Zou, Nanhai
Cc: Yang, Rong R
Cc: Tim Gore
Cc: Jeff McGee
Cc: Mika Kuoppala
Signed-off-by: Arun Siluvery
---
drivers/gp
This is a WA affecting pooled eu which is a bxt specific feature.
Reviewed-by: Mika Kuoppala
Cc: Winiarski, Michal
Cc: Zou, Nanhai
Cc: Yang, Rong R
Cc: Jeff McGee
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 6
Kernel only need to add a register to HW whitelist, required for a
preemption related issue.
Reference: HSD#2131039
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +
2 files changed, 6 insertions(+)
diff --git a
On 03/06/2016 21:31, Matthew Auld wrote:
What about skl, this also seems to need the WA until A0?
SKL:A0 is pre-production stepping, it can be ignored.
regards
Arun
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On 03/06/2016 16:28, Patchwork wrote:
== Series Details ==
Series: BXT Pooled EU kernel support and WA patches (rev3)
URL : https://patchwork.freedesktop.org/series/8200/
State : warning
== Summary ==
Series 8200v3 BXT Pooled EU kernel support and WA patches
http://patchwork.freedesktop.org/
Kernel only need to add a register to HW whitelist, required for a
preemption related issue.
Reference: HSD#2131039
Reviewed-by: Jeff McGee
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +
2 files changed, 6
On 06/06/2016 14:58, Patchwork wrote:
== Series Details ==
Series: drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear (rev2)
URL : https://patchwork.freedesktop.org/series/8218/
State : warning
== Summary ==
Series 8218v2 drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaSt
On 06/06/2016 18:30, Tvrtko Ursulin wrote:
On 03/06/16 17:08, Chris Wilson wrote:
Currently __i915_wait_request uses a per-engine wait_queue_t for the dual
purpose of waking after the GPU advances or for waking after an error.
In the future, we may add even more wake sources and require greater
On 03/06/2016 22:06, Chris Wilson wrote:
As we only ever keep the first error state around, we can avoid some
work that can be quite intrusive if we don't record the error the second
time around. This does move the race whereby the user could discard one
error state as the second is being capture
/drm/i915/intel_lrc.c| 3 ---
drivers/gpu/drm/i915/intel_ringbuffer.c | 8 --
drivers/gpu/drm/i915/intel_ringbuffer.h | 1 -
7 files changed, 15 insertions(+), 112 deletions(-)
looks good to me,
Reviewed-by: Arun Siluvery
regards
Arun
diff --git a/drivers/gpu/drm/i915
On 09/06/2016 13:48, tim.g...@intel.com wrote:
From: Tim Gore
This patch enables a workaround for a mid thread preemption
issue where a hardware timing problem can prevent the
context restore from happening, leading to a hang.
Signed-off-by: Tim Gore
---
drivers/gpu/drm/i915/i915_gem_gtt.c
On 09/06/2016 20:19, tim.g...@intel.com wrote:
From: Tim Gore
This patch enables a workaround for a mid thread preemption
issue where a hardware timing problem can prevent the
context restore from happening, leading to a hang.
v2: move to gen9_init_workarounds (Arun)
Signed-off-by: Tim Gore
On 10/06/2016 12:16, Gore, Tim wrote:
Tim Gore
Intel Corporation (UK) Ltd. - Co. Reg. #1134945 - Pipers Way, Swindon SN3 1RJ
-Original Message-
From: Arun Siluvery [mailto:arun.siluv...@linux.intel.com]
Sent: Friday, June 10, 2016 7:30 AM
To: Gore, Tim; intel-gfx
've been good to have correct spelling but to
match with existing documentation we have to use the same name.
Reviewed-by: Arun Siluvery
regards
Arun
/* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */
I915_WRITE(BDW_SCRATC
On 15/06/2016 13:49, Yang Rong wrote:
Update kernel interface with new I915_GETPARAM ioctl entries for
pooled EU and min no. of eus in a pool. Add a wrapping function
for each parameter. Userspace drivers need these values when decide
the thread count. This kernel enabled pooled eu by default for
In preparation for engine reset work update this parameter to handle more
than one type of reset. Default at the moment is still full gpu reset.
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_params.c | 6 +++---
drivers/gpu/drm/i915
need to do first at
the start of the hang recovery path, which might potentially sleep if the
struct_mutex is already held by another thread. Not good when you're in a
hard interrupt context.
Cc: Mika Kuoppala
Signed-off-by: Tomas Elf
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm
hang,
once this is done then we continue with the normally submission of two
contexts at a time. The intention is to restore the submission state at the
time of hang.
Signed-off-by: Tomas Elf
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/intel_lrc.c | 36
in execlist mode relies on the
context resubmission after reset. If the state is inconsistent,
resubmission can cause unforseen side-effects such as unexpected
preemptions.
Engine is restarted after reset with this state.
Signed-off-by: Tomas Elf
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm
unnecessary. To
avoid this we check if the engine is already prepared, if so we just exit
from that point.
Signed-off-by: Mika Kuoppala
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/intel_uncore.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu
.
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_drv.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9fa9698..8bb05b2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915
://lists.freedesktop.org/archives/intel-gfx/2016-April/092349.html
Arun Siluvery (13):
drm/i915: Update i915.reset to handle engine resets
drm/i915/tdr: Extend the idea of reset_counter to engine reset
drm/i915/tdr: Modify error handler for per engine hang recovery
drm/i915/tdr: Prepare
that it needs to back off.
Signed-off-by: Tomas Elf
Signed-off-by: Ian Lister
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Arun Siluvery
---
These changes are based on current nightly. I am aware of the changes being
done to wait_request patch in "thundering herd series&qu
Driver maintains count of how many times a given engine is reset, useful to
capture this in error state also. It gives an idea of how engine is coping
up with the workloads it is executing before this error state.
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_drv.h | 1
Engine reset implementation is currently supported with Execlist based
submission, GuC submission need to be disabled for BAT testing purpose.
Signed-off-by: Arun Siluvery
---
Current TDR implementation is only for Execlist submission, we need this
patch to enable BAT testing with Execlist
d the hang
- reset itself failed for some reason
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Tomas Elf
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_drv.c | 54 +++--
drivers/gpu/drm/i915/i915_drv.h | 4 +++
drivers/gpu/drm/i915/i915_
A new variable is added to export the reset counts to debugfs, this
includes full gpu reset and engine reset count. This is useful for tests
where they areexpected to trigger reset; these counts are checked before
and after the test to ensure the same.
Signed-off-by: Arun Siluvery
---
drivers
. The same
behaviour is adapted but reset event is only dispatched once even when
multiple engines are hung. Finally once reset is complete we send reset
done event as usual.
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Ian Lister
Signed-off-by: Tomas Elf
Signed-off-by: Arun Sil
_mutex should not be thrown out of __i915_wait_request during
TDR hang recovery. Therefore we need a way to determine which threads are
holding the mutex and which are not.
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Tomas Elf
Signed-off-by: John Harrison
Signed-off-by: Arun Siluvery
this request
is resubmitted to HW. The request that caused the hang would be at the
start of execlist queue, unless we resubmit and complete this request, it
cannot be removed from the queue.
Cc: Mika Kuoppala
Signed-off-by: Tomas Elf
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/intel_lr
Everything in place, flip the switch.
This feature is available only from Gen8, for previous gen devices driver
falls back to legacy full gpu reset.
Signed-off-by: Tomas Elf
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_params.c | 4 ++--
1 file changed, 2 insertions(+), 2
9_GAMT_ECO_REG_RW_IA,
+ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+
/* WaDisableLSQCROPERFforOCL:kbl */
ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
if (ret)
with the indentation fixed, it is,
Reviewed-by: Arun Siluvery
regards
Arun
___
Intel-gfx ma
ct the competed reset using the global gpu_error->reset_counter
s/competed/completed
anymore, we do not need to track the reset_counter epoch inside the
request.
Signed-off-by: Chris Wilson
Cc: Arun Siluvery
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/d
...@lists.freedesktop.org] On Behalf Of
Arun Siluvery
Sent: Wednesday, June 15, 2016 16:17
To: Yang, Rong R ; beig...@lists.freedesktop.org;
intel-gfx@lists.freedesktop.org
Subject: Re: [Beignet] [PATCH] intel: Export pooled EU and min no. of eus in a
pool.
On 15/06/2016 13:49, Yang Rong wrote:
Update
11 12:53:46 2015 +0100
drm/i915: Split alloc from init for lrc
lrc_setup_hardware_status_page() in the same function gen8_init_common_ring()
takes care of this.
Cc: Nick Hoath
Cc: Daniel Vetter
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/intel_lrc.c | 6 --
1 file changed, 6
s/prempt/preempt
Cc: Alex Dai
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/intel_guc_fwif.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 40b2ea5..11298af 100644
--- a/drivers
On 01/12/2015 12:17, Mika Kuoppala wrote:
If head seems stuck and engine in question is rcs,
inspect subunit state transitions before deciding that
this really is a hang instead of limited progress.
References: https://bugs.freedesktop.org/show_bug.cgi?id=93029
Cc: Chris Wilson
Cc: Dave Gordon
1 | I->A | | | |
| |
EXECLIST_CTX/CSB[5]: 0x000.00a33 / 0x0018 | | | | A->I |
DONE | |
v1: http://www.spinics.net/lists/intel-gfx/msg86671.html
Arun Siluvery (1):
drm/i915/error: Capture WA ctx batch in error state
Dave Gordon (8):
drm/i915/error: capture execlist st
From: Dave Gordon
For: VIZ-2021
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 36 +--
2 files changed, 27 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/driver
From: Dave Gordon
Also decode and output CSB entries, in time order
For: VIZ-2021
Signed-off-by: Dave Gordon
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gpu_error.c | 37 +++
2 files changed, 30
From: Dave Gordon
Record a few more things about the requests outstanding at the time of
capture ...
For: VIZ-2021
Signed-off-by: Dave Gordon
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_drv.h | 6 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 23
From: Dave Gordon
Context capture hasn't worked for a while now, probably since the
introduction of execlists; this patch makes it work again by using
a different way of identifying the context of interest.
For: VIZ-2021
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/i915_gpu_error.c | 7
From: Dave Gordon
For: VIZ-2021
Signed-off-by: Dave Gordon
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_debugfs.c| 17 ++---
drivers/gpu/drm/i915/i915_guc_submission.c | 20
drivers/gpu/drm/i915/intel_guc.h | 9 +++--
3
From: Dave Gordon
For: VIZ-2021
Signed-off-by: Dave Gordon
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++
drivers/gpu/drm/i915/i915_gpu_error.c | 107 ++
2 files changed, 111 insertions(+)
diff --git a/drivers/gpu/drm/i915
From Gen8 onwards we apply ctx workarounds using special batch buffers that
execute during save/restore, good to have them in error state.
v2: use wa_ctx->size and print only size values (Mika)
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i
From: Dave Gordon
At present, execlist status/ctx_id and CSBs, not the submission queue
v2: dump execlist details only when they are enabled (Mika)
For: VIZ-2021
Signed-off-by: Dave Gordon
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_drv.h | 9 +
drivers/gpu/drm
From: Dave Gordon
v2: add separators for readability
For: VIZ-2021
Signed-off-by: Dave Gordon
Signed-off-by: Arun Siluvery (v2)
---
drivers/gpu/drm/i915/i915_drv.h | 4 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 77 +--
2 files changed, 58 insertions
On 19/02/2016 14:58, Michel Thierry wrote:
The cache line offset for the Indirect CS context (0x21C8) varies from gen
to gen.
v2: Move it into a function (Arun), use MISSING_CASE (Chris)
Cc: Arun Siluvery
Cc: Chris Wilson
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_lrc.c
gt;mmio_base), 0);
/* Ring buffer start address is not known until the buffer is pinned.
looks good to me,
Reviewed-by: Arun Siluvery
regards
Arun
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/
_cs *ring)
int __intel_ring_space(int head, int tail, int size);
void intel_ring_update_space(struct intel_ringbuffer *ringbuf);
int intel_ring_space(struct intel_ringbuffer *ringbuf);
-bool intel_ring_stopped(struct intel_engine_cs *ring);
int __must_check intel_ring_idle(struct intel_engine_cs
On 11/01/2016 09:16, Chris Wilson wrote:
Remove some redundant kernel messages as we deduce a hung GPU and
capture the error state.
v2: Fix "hang" vs "no progress" message whilst I was there
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_irq.c | 21 +++--
1 file c
On 11/01/2016 09:16, Chris Wilson wrote:
Migrate the request operations out of the main body of i915_gem.c and
into their own C file for easier expansion.
v2: Move __i915_add_request() across as well
Signed-off-by: Chris Wilson
---
don't we lose the history in git blame when moved to a new f
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