el_runtime_pm.c.
v8: Rebased to drm-intel-nightly. (Animesh)
Issue: VIZ-2819
Signed-off-by: A.Sunil Kamath
Signed-off-by: Damien Lespiau
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_reg.h | 11
drivers/gpu/drm/i915/intel_runtime_pm.c | 47 ++
m Imre - added csr helper pointers to simplify the
code. (Imre)
v9: After adding dmc ver 1.0 support rebased on top of nightly. (Animesh)
Issue: VIZ-2819
Signed-off-by: A.Sunil Kamath
Signed-off-by: Suketu Shah
Signed-off-by: Damien Lespiau
Signed-off-by: Imre Deak
Signed-off-by: Animesh Manna
-
-off-by: Damien Lespiau
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 35 +
1 file changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index f62d42b..dae65e
intel_runtime_pm.c.
v7:
1) Refactored the code for removing the warning got from checkpatch.
2) After adding dmc ver 1.0 support rebased on top of nightly. (Animesh)
Issue: VIZ-2819
Signed-off-by: A.Sunil Kamath
Signed-off-by: Suketu Shah
Signed-off-by: Damien Lespiau
Signed-off-by: Animesh Ma
from Imre -
[PATCH] drm/i915/skl: avoid false CSR fw not loaded WARN during driver
load/resume
v9: After adding dmc ver 1.0 support rebased on top of nightly. (Animesh)
Issue: VIZ-2819
Signed-off-by: A.Sunil Kamath
Signed-off-by: Suketu Shah
Signed-off-by: Damien Lespiau
Signed-off-by: Ani
From: Suketu Shah
Enable runtime PM for Skylake platform
v2: After adding dmc ver 1.0 support rebased on top of nightly. (Animesh)
Issue: VIZ-2819
Signed-off-by: A.Sunil Kamath
Signed-off-by: Suketu Shah
Signed-off-by: Damien Lespiau
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915
amath
Signed-off-by: Suketu Shah
Signed-off-by: Damien Lespiau
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/intel_drv.h| 2 ++
drivers/gpu/drm/i915/intel_runtime_pm.c | 61 ++---
2 files changed, 58 insertions(+), 5 deletions(-)
diff --git a/driver
On 04/01/2015 04:08 PM, Damien Lespiau wrote:
On Wed, Apr 01, 2015 at 01:18:25PM +0530, Animesh Manna wrote:
+struct intel_css_header {
Just a small question, what does CSS mean in this context? that's the
first time I see it.
Taken the name from bspec, will explore and get back t
On 04/01/2015 04:08 PM, Damien Lespiau wrote:
On Wed, Apr 01, 2015 at 01:18:25PM +0530, Animesh Manna wrote:
+struct intel_css_header {
Just a small question, what does CSS mean in this context? that's the
first time I see it.
CSS stands for "Code signing service". In
tly for parsing the header info & memory allocation
only done separately for payload. (Animesh)
v16:
No need for out_regs label in i915_driver_load(), so removed it. (Animesh)
Issue: VIZ-2569
Signed-off-by: A.Sunil Kamath
Signed-off-by: Damien Lespiau
Signed-off-by: Animesh Manna
Signed-off-
m Imre - added csr helper pointers to simplify the
code. (Imre)
v9: After adding dmc ver 1.0 support rebased on top of nightly. (Animesh)
v10: Added a enum for different csr states, suggested by Imre. (Animesh)
Issue: VIZ-2819
Signed-off-by: A.Sunil Kamath
Signed-off-by: Suketu Shah
Signed-off-by:
On 04/13/2015 04:33 PM, Imre Deak wrote:
On ma, 2015-04-13 at 15:54 +0530, Animesh Manna wrote:
From: "A.Sunil Kamath"
Display Context Save and Restore support is needed for
various SKL Display C states like DC5, DC6.
This implementation is added based on first version of DMC C
On 04/13/2015 10:52 PM, Damien Lespiau wrote:
On Mon, Apr 13, 2015 at 08:15:29PM +0300, Imre Deak wrote:
Ok, I haven't seen that. One question is if we need to support multiple
interface versions or just the latest one. I would say only the latest
one (for each platform) and so I915_CSR_SKL sh
unloading.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_dma.c | 1 -
drivers/gpu/drm/i915/i915_drv.c | 10 +--
drivers/gpu/drm/i915/i915_drv.h | 13 ++-
drivers/gpu/drm/i915/intel_csr.c| 141 +++-
drivers/gpu/drm/i915
structure.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_dma.c | 1 -
drivers/gpu/drm/i915/i915_drv.c | 6
drivers/gpu/drm/i915/i915_drv.h | 10 ---
drivers/gpu/drm/i915/intel_csr.c| 52 -
drivers/gpu/drm/i915
.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 5
drivers/gpu/drm/i915/intel_csr.c| 3 ++
drivers/gpu/drm/i915/intel_runtime_pm.c | 51 ++---
4 files changed, 44 insertions
unloading.
- Corrected the sanity check for mmio address of csr (Requested by Imre).
- Removed assert call of csr during disabling dc6 (Requested by Damien).
Animesh Manna (6):
drm/i915/gen9: Removed csr-lock and csr-state
drm/i915/gen9: Added a async work for fw-loading and dc5/dc6
v1: As per review comments from Daniel, replaced async firmware
loading with request_firmware() which will load the dmc firmware and
once firmware is loaded, dc5/dc6 register programming can be done
in the same thread.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_drv.c
As during disabling dc6 no need to check for csr firmware
loading status, so removed the assert call.(Requested by Damien.)
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/intel_csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index d600640..f515d54 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm
Firmware loading can be optimized by setting the dmc_present flag
for the first time and later internallly stored firmware data
can be used.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_csr.c | 24 +++-
2 files changed
, changes made in the current version.
DMC redesign patch series has dependencies with current patch series. Need
to rework on few patches, planning to send after initial review feedback
of the current patch series.
http://lists.freedesktop.org/archives/intel-gfx/2015-August/072921.html
Animesh Manna (5
from Daniel added code commnent.
Cc: Daniel Vetter
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Animesh Manna
Signed-off-bt: Vathsala Nagaraju
Signed-off-by: Rajneesh Bhardwaj
---
drivers/gpu/drm/i915/intel_display.c | 14 ++
1 file changed, 10 insertions(+), 4
the same is not applicable for bxt. Display
engine can enter into dc9 without dmc, hence unblocking disable call.
v1: Initial version.
v2: Rebased as per current patch series.
Cc: Daniel Vetter
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Animesh Manna
Signed-off-by
-hibernation.
Cc: Daniel Vetter
Signed-off-by: Animesh Manna
Signed-off-by: Vathsala Nagaraju
---
drivers/gpu/drm/i915/i915_drv.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1d88745..478101c 100644
--- a/drivers/gpu
call.
Cc: Daniel Vetter
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Animesh Manna
Signed-off-by: Vathsala Nagaraju
Signed-off-by: Rajneesh Bhardwaj
---
drivers/gpu/drm/i915/i915_drv.c | 13 +
drivers/gpu/drm/i915/intel_drv.h| 2 ++
drivers/gpu
on review comments from Daniel,
- Added a check to know hardware status and load the firmware if not loaded.
Cc: Daniel Vetter
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Animesh Manna
Signed-off-by: Vathsala Nagaraju
---
drivers/gpu/drm/i915/intel_csr.c | 9 +
1
intel_csr_ucode_init call after runtime pm enable.
Cc: Daniel Vetter
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_dma.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm
power well. That's a bit too
much, but since the firmware loading task should completely fairly
quickly this won't be a real problem really.
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Daniel Vetter
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/intel
series.
http://lists.freedesktop.org/archives/intel-gfx/2015-August/072870.html
- Two more patches added in this patch series from older patch series.
http://lists.freedesktop.org/archives/intel-gfx/2015-July/071163.html
Animesh Manna (5):
drm/i915/gen9: csr_init after runtime pm enable
drm/i915
: Sunil Kamath
Signed-off-by: Daniel Vetter
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_csr.c | 42
2 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b
From: Daniel Vetter
Avoids non-static functions since all the callers are in intel_rpm.c.
Only thing we need for that is to move the register definitions into
i915_reg.h.
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Daniel Vetter
Signed-off-by: Animesh Manna
u
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Daniel Vetter
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_dma.c | 1 -
drivers/gpu/drm/i915/i915_drv.c | 13 ++
drivers/gpu/drm/i915/i915_drv.h | 10 ---
drivers/gpu/drm/i915/int
ath
Signed-off-by: Daniel Vetter
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/intel_csr.c | 48 +---
1 file changed, 30 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 9d4b37b..9971
the resume and unload code.
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Daniel Vetter
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_csr.c | 19 +++
2 files changed, 12 insertions(+), 8 deletions
Condition check for out of boundary for csr address space is corrected
(Thanks to David Binderman for suggestion).
Cc: Imre Deak
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/intel_csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915
Note that for bxt without dmc, display engine can go to lowest
possible state (dc9), so releasing the rpm reference.
Cc: Daniel Vetter
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/intel_csr.c | 2 +-
1 file changed, 1 insertion
From: Daniel Vetter
If we really want to we can be more verbose here, but we really don't
need an entire function for this.
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Daniel Vetter
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_drv.c
From: Daniel Vetter
We need to make sure we don't put garbage into the hw if dmc firmware
loading failed mid-thru.
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Daniel Vetter
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/intel_csr.c | 2 +-
1 file chang
From: Daniel Vetter
As all csr firmware related opertion are not using any
any data structures of drm framework level, so better to
use dev_priv instead of dev. it's a new style! :)
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Daniel Vetter
Signed-off-by: Animesh
by using display_power_domain_get/put - this will always
ensure rpm will be blocked if firmware is not loaded.
Cc: Daniel Vetter
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_drv.c | 2 --
drivers/gpu/drm/i915/intel_csr.c | 2
As during disabling dc6 no need to check for csr firmware
loading status, so removed the assert call (Requested by Damien).
Cc: Damien Lespiau
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915
On 8/26/2015 6:40 PM, Daniel Vetter wrote:
On Wed, Aug 26, 2015 at 01:36:05AM +0530, Animesh Manna wrote:
Dmc will restore the csr program except DC9, cold boot,
warm reset, PCI function level reset, and hibernate/suspend.
intel_csr_load_program() function is used to load the firmware
data
On 8/26/2015 6:41 PM, Daniel Vetter wrote:
On Wed, Aug 26, 2015 at 01:36:08AM +0530, Animesh Manna wrote:
While display engine entering into low power state no need to disable
cdclk pll as CSR firmware of dmc will take care. If pll is already
enabled firmware execution sequence will be
On 8/26/2015 4:58 PM, Animesh Manna wrote:
This patch series has the changes done to redesign the dmc firmware
loading flow. This is continuation of the below patch series after
addressing review comments from Daniel.
v1: http://lists.freedesktop.org/archives/intel-gfx/2015-August/072921.html
On 9/9/2015 9:00 PM, Daniel Vetter wrote:
On Wed, Sep 09, 2015 at 04:52:09PM +0200, Takashi Iwai wrote:
Fix a wrong logical AND (&&) used for the range check of CSR MMIO.
Spotted nicely by gcc -Wlogical-op flag:
drivers/gpu/drm/i915/intel_csr.c: In function ‘finish_csr_load’:
drivers/gp
On 9/2/2015 2:24 PM, Daniel Vetter wrote:
On Wed, Aug 26, 2015 at 07:40:54PM +0530, Animesh Manna wrote:
On 8/26/2015 6:40 PM, Daniel Vetter wrote:
On Wed, Aug 26, 2015 at 01:36:05AM +0530, Animesh Manna wrote:
Dmc will restore the csr program except DC9, cold boot,
warm reset, PCI
On 9/7/2015 9:52 PM, Daniel Vetter wrote:
On Mon, Sep 07, 2015 at 04:34:30PM +0530, Sunil Kamath wrote:
On Wednesday 26 August 2015 01:36 AM, Animesh Manna wrote:
Dmc will restore the csr program except DC9, cold boot,
warm reset, PCI function level reset, and hibernate/suspend
On 9/10/2015 8:15 PM, Daniel Vetter wrote:
On Thu, Sep 10, 2015 at 01:58:54AM +0530, Animesh Manna wrote:
On 9/2/2015 2:24 PM, Daniel Vetter wrote:
On Wed, Aug 26, 2015 at 07:40:54PM +0530, Animesh Manna wrote:
On 8/26/2015 6:40 PM, Daniel Vetter wrote:
On Wed, Aug 26, 2015 at 01:36:05AM
On 9/10/2015 8:15 PM, Daniel Vetter wrote:
On Thu, Sep 10, 2015 at 01:58:54AM +0530, Animesh Manna wrote:
On 9/2/2015 2:24 PM, Daniel Vetter wrote:
On Wed, Aug 26, 2015 at 07:40:54PM +0530, Animesh Manna wrote:
On 8/26/2015 6:40 PM, Daniel Vetter wrote:
On Wed, Aug 26, 2015 at 01:36:05AM
On 9/14/2015 1:16 PM, Daniel Vetter wrote:
On Fri, Sep 11, 2015 at 12:36:24AM +0530, Animesh Manna wrote:
On 9/10/2015 8:15 PM, Daniel Vetter wrote:
On Thu, Sep 10, 2015 at 01:58:54AM +0530, Animesh Manna wrote:
On 9/2/2015 2:24 PM, Daniel Vetter wrote:
On Wed, Aug 26, 2015 at 07:40:54PM
call.
v3: Rebased on top of latest code.
Cc: Daniel Vetter
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Animesh Manna
Signed-off-by: Vathsala Nagaraju
Signed-off-by: Rajneesh Bhardwaj
---
drivers/gpu/drm/i915/i915_drv.c | 13 +
drivers/gpu/drm/i915
On 09/28/2015 12:51 PM, Daniel Vetter wrote:
On Wed, Aug 26, 2015 at 01:36:07AM +0530, Animesh Manna wrote:
Mmio register access after dc6/dc5 entry is not allowed when
DC6 power states are enabled according to bspec (bspec-id 0527),
so enabling dc6 as the last call in suspend flow.
We
v4:
- Removed all warning by reordering the patchsets.
- Changed the dmc firmware file name skl_dmc_ver1.bin, followed naming
conventipon as _dmc_.bin
v3:
MOdified the code of patch 1 and 3 based on review commets.
v2:
Based on review comments modified the code.
v1:
Initial version send as RFC
f-by: A.Sunil Kamath
Signed-off-by: Damien Lespiau
Signed-off-by: Animesh Manna
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/Makefile| 3 +-
drivers/gpu/drm/i915/i915_dma.c | 11 +-
drivers/gpu/drm/i915/i915_drv.c | 20 +++
drivers/gpu/drm/i915/i915_drv.h | 17 ++
dri
name chnaged to csr_state (singular form).
- FW_UNINITIALIZED used as zeroth element in enum csr_state.
- Prototype changed for helper function(set/get csr status), using enum
csr_state instead of bool.
Issue: VIZ-2819
Signed-off-by: A.Sunil Kamath
Signed-off-by: Suketu Shah
Signed-off-by: Dam
el_runtime_pm.c.
v8: Rebased to drm-intel-nightly. (Animesh)
Issue: VIZ-2819
Signed-off-by: A.Sunil Kamath
Signed-off-by: Damien Lespiau
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_reg.h | 11 +
drivers/gpu/drm/i915/intel_runtime_pm.c | 41 ++
eview comments from Imre.
- Moved intel_display_power_well_is_enabled() to intel_runtime_pm.c.
- Removed mutex lock from assert_csr_loaded(). (Animesh)
Issue: VIZ-2819
Signed-off-by: A.Sunil Kamath
Signed-off-by: Suketu Shah
Signed-off-by: Damien Lespiau
Signed-off-by: Animesh Manna
---
drivers/gp
ed-off-by: A.Sunil Kamath
Signed-off-by: Suketu Shah
Signed-off-by: Damien Lespiau
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_drv.c | 30 +++
drivers/gpu/drm/i915/intel_runtime_pm.c | 43 +++--
2 files changed, 66 insertions(+), 7
From: Suketu Shah
Enable runtime PM for Skylake platform
v2: After adding dmc ver 1.0 support rebased on top of nightly. (Animesh)
Issue: VIZ-2819
Signed-off-by: A.Sunil Kamath
Signed-off-by: Suketu Shah
Signed-off-by: Damien Lespiau
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915
-off-by: Damien Lespiau
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 27 +--
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 7e6908e..b
ned-off-by: Suketu Shah
Signed-off-by: Damien Lespiau
Signed-off-by: Animesh Manna
Reviewed-by: Imre Deak
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 40 +
1 file changed, 36 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/d
+ Jesse, Rodrigo
On 04/16/2015 02:51 PM, Imre Deak wrote:
On to, 2015-04-16 at 14:22 +0530, Animesh Manna wrote:
[...]
+#include
+#include "i915_drv.h"
+#include "i915_reg.h"
+
+#define I915_CSR_SKL "i915/skl_dmc_ver1.bin"
The latest version on the FW downlo
On 4/16/2015 4:55 PM, Imre Deak wrote:
On to, 2015-04-16 at 17:29 +0530, Animesh Manna wrote:
+ Jesse, Rodrigo
On 04/16/2015 02:51 PM, Imre Deak wrote:
On to, 2015-04-16 at 14:22 +0530, Animesh Manna wrote:
[...]
+#include
+#include "i915_drv.h"
+#include "i915_re
On 4/16/2015 3:18 PM, Imre Deak wrote:
On to, 2015-04-16 at 12:25 +0300, Imre Deak wrote:
On to, 2015-04-16 at 14:22 +0530, Animesh Manna wrote:
[...]
@@ -223,11 +244,13 @@ static void finish_csr_load(const struct firmware *fw,
void *context)
if (!fw
hich helps
calling once to set the csr status. The same flag used to fail RPM if find any
issue during
firmware loading.
Issue: VIZ-2819
Signed-off-by: A.Sunil Kamath
Signed-off-by: Suketu Shah
Signed-off-by: Damien Lespiau
Signed-off-by: Imre Deak
Signed-off-by: Animesh Manna
---
f-by: A.Sunil Kamath
Signed-off-by: Damien Lespiau
Signed-off-by: Animesh Manna
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/Makefile| 3 +-
drivers/gpu/drm/i915/i915_dma.c | 11 +-
drivers/gpu/drm/i915/i915_drv.c | 20 +++
drivers/gpu/drm/i915/i915_drv.h | 17 ++
dri
Added docbook info regarding context save and restore (CSR)
firmware support added from gen9 onwards to drive newly added
DMC (Display microcontroller) in display engine.
Signed-off-by: Animesh Manna
Signed-off-by: A.Sunil Kamath
---
Documentation/DocBook/drm.tmpl | 22
Specifically csr mutex lock is to protect csr-related data structures
so declaration moved intel_csr structure.
Signed-off-by: Animesh Manna
Signed-off-by: A.Sunil Kamath
---
drivers/gpu/drm/i915/i915_dma.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 6 +++---
drivers/gpu/drm/i915
On 5/12/2015 1:59 PM, Daniel Vetter wrote:
On Tue, May 12, 2015 at 01:02:08PM +0530, Animesh Manna wrote:
Specifically csr mutex lock is to protect csr-related data structures
so declaration moved intel_csr structure.
Signed-off-by: Animesh Manna
Signed-off-by: A.Sunil Kamath
---
drivers
ned-off-by: Animesh Manna
Signed-off-by: A.Sunil Kamath
---
Documentation/DocBook/drm.tmpl | 7 +-
drivers/gpu/drm/i915/intel_csr.c | 53
2 files changed, 59 insertions(+), 1 deletion(-)
diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBoo
load. Will analyzing further and possibly send
as a incremental patch.
- Based on review comment from Damien, warning for firmware loading
failure is removed.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_dma.c | 1 -
drivers/gpu/drm/i915/i915_drv.c | 2 +-
driver
Naming convention of csr firmware will be -
_dmc__.bin
Accordingly updated the same in code.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/intel_csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
On 5/21/2015 5:41 PM, Daniel Vetter wrote:
On Thu, May 21, 2015 at 03:49:52PM +0530, Animesh Manna wrote:
Before enabling dc5/dc6, used wait for completion instead of busy waiting.
v1:
- Based on review comment from Daniel replaced mutex and related
implementation with completion. In current
grab the _INIT display power well. That's a bit too
much, but since the firmware loading task should completely fairly
quickly this won't be a real problem really.
Cc: Animesh Manna
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_csr.c | 4 ++--
1 file changed, 2 insert
old a rpm reference (and rpm
get/put is synchronized with its own locking already) there's no need
for any additional synchronization between the dmc loader and the rpm
entry/exit code.
Hence we can remove all dmc_load_status_get calls, they don't do
anything any more.
Cc: Animesh Manna
entry and will not work as expected.
- The above same applicable for cdclk pll as well.
- mmio read/write after dc6 trigger will cause display engine hang.
Based on Daniel's review comments and thiinking of above pointers
following patches is created.
Animesh Manna (10):
drm/i915/bxt: Path
Cc: Damien Lespiau
Cc: Rodrigo Vivi
Cc: Sunil Kamath
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/intel_csr.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 6d8a7bf..1866426 100644
--- a/drivers/gpu
Added stepping info in intel_csr.c which is required to extract
specific firmware from packaged dmc firmware.
Cc: Vetter, Daniel
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/intel_csr.c | 11 +++
1 file changed, 11
Modified HAS_CSR macro defination which earlier only supported
for skl, now added support for BXT.
Cc: Vetter, Daniel
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion
u
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Daniel Vetter
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_dma.c | 1 -
drivers/gpu/drm/i915/i915_drv.c | 6 -
drivers/gpu/drm/i915/i915_drv.h | 10 -
drivers/gpu/drm/i915/intel_csr.c | 48 +
r bxt without dmc, display engine can go to lowest
possible state (dc9), so releasing the rpm reference.
Cc: Daniel Vetter
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_dma.c | 6 +++---
drivers/gpu/drm/i915/intel_
: Sunil Kamath
Signed-off-by: Daniel Vetter
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_csr.c | 50
2 files changed, 26 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b
the resume and unload code.
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Daniel Vetter
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_csr.c | 22 +++---
2 files changed, 12 insertions(+), 11 deletions
Signed-off-by: Animesh Manna
Signed-off-bt: Vathsala Nagaraju
Signed-off-by: Rajneesh Bhardwaj
---
drivers/gpu/drm/i915/intel_display.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
As csr firmware is taking care of loading the firmware,
so no need for driver to load again.
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Animesh Manna
Signed-off-by: Vathsala Nagaraju
---
drivers/gpu/drm/i915/i915_drv.c | 1 -
1 file changed, 1 deletion(-)
diff --git a
ust one place.
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Daniel Vetter
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/intel_csr.c| 58 +++--
drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
2 files changed, 34 insertions(+),
From: Daniel Vetter
If we really want to we can be more verbose here, but we really don't
need an entire function for this.
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Daniel Vetter
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_drv.c
Mmio register access after dc6/dc5 entry is causing the
system hang, so enabling dc6 as the last call in suspend flow.
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Animesh Manna
Signed-off-by: Vathsala Nagaraju
Signed-off-by: Rajneesh Bhardwaj
---
drivers/gpu/drm/i915
(dc6) but the same is not applicable for bxt. Display
engine can enter into dc9 without dmc, hence unblocking disable call.
Cc: Daniel Vetter
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Animesh Manna
Signed-off-by: Vathsala Nagaraju
---
drivers/gpu/drm/i915
hile disabling pw2 which ensure that firmware will be
available before disabling pw1 in suspend flow.
Cc: Daniel Vetter
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_drv.c | 2 --
drivers/gpu/drm/i915/intel_csr.c
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Animesh Manna
Signed-off-by: Vatsala Nagaraju
---
drivers/gpu/drm/i915/intel_csr.c | 11 +--
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915
From: Daniel Vetter
As all csr firmware related opertion are not using any
any data structures of drm framework level, so better to
use dev_priv instead of dev. it's a new style! :)
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Daniel Vetter
Signed-off-by: Animesh
From: Daniel Vetter
Avoids non-static functions since all the callers are in intel_rpm.c.
Only thing we need for that is to move the register definitions into
i915_reg.h.
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Daniel Vetter
Signed-off-by: Animesh Manna
From: Daniel Vetter
We need to make sure we don't put garbage into the hw if dmc firmware
loading failed mid-thru.
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Daniel Vetter
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm
firmware size during memcpy(). (Suggested by Sunil)
Cc: Daniel Vetter
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Animesh Manna
Signed-off-by: Vathsala Nagaraju
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_csr.c | 16
2 files
Kamath
Signed-off-by: Animesh Manna
Signed-off-by: Vathsala Nagaraju
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index c660245
l specific bug-fixes are
seperated out and sending as seperate patch series to make it simple.
Animesh Manna (5):
drm/i915/gen9: Removed byte swapping for csr firmware
drm/i915/skl: Making DC6 entry is the last call in suspend flow.
drm/i915/skl: Do not disable cdclk PLL if csr firmware is pres
As csr firmware is taking care of loading the firmware,
so no need for driver to load again.
Cc: Daniel Vetter
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Animesh Manna
Signed-off-by: Vathsala Nagaraju
---
drivers/gpu/drm/i915/i915_drv.c | 3 ---
1 file changed, 3
Cc: Sunil Kamath
Signed-off-by: Animesh Manna
Signed-off-bt: Vathsala Nagaraju
Signed-off-by: Rajneesh Bhardwaj
---
drivers/gpu/drm/i915/intel_display.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915
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