[Why]:
Aligh with DP spec wanted to follow same naming convention.
[How]:
Changed the macro name of the dpcd address used for getting requested
test-pattern.
Cc: Harry Wentland
Cc: Alex Deucher
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
1 file
vswing/pre-emphasis adjustment calculation is needed in processing
of auto phy compliance request other than link training, so moved
the same function in intel_dp.c.
No functional change.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dp.c | 32
During DP phy compliance auto test mode, sink will request
combination of different test pattern with differnt level of
vswing, pre-emphasis. Function added to prepare for it.
Reviewed-by: Manasi Navare
Signed-off-by: Animesh Manna
---
.../drm/i915/display/intel_display_types.h| 1
As per request from DP phy compliance test few special
test pattern need to set by source. Added function
to set pattern in DP_COMP_CTL register. It will be
called along with other test parameters like vswing,
pre-emphasis programming in atomic_commit_tail path.
Signed-off-by: Animesh Manna
This patch process phy compliance request by programming requested
vswing, pre-emphasis and test pattern.
Note: FIXME tag added as design discusion is ongoing in previous patch
series. Some temporary fix added and the patch is under-development, not for
review.
Signed-off-by: Animesh Manna
DP_COMP_CTL and DP_COMP_PAT register used to program DP
compliance pattern.
Reviewed-by: Manasi Navare
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_reg.h | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm
These debugfs entry will help testapp to understand the test request
during dp phy compliance mode.
Acked-by: Manasi Navare
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_debugfs.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915
Send uevent to testapp and set test_active flag. To align with link
compliance design existing intel_dp_compliance tool will be used to
get the phy request in userspace through uevent.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dp.c | 10 --
1 file changed, 8
on instead pointer for link_status. (Ville)
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dp.c | 34 +++
drivers/gpu/drm/i915/display/intel_dp.h | 4 +++
.../drm/i915/display/intel_dp_link_training.c | 32 -
3 files changed, 38 inserti
on instead pointer for link_status. (Ville)
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dp.c | 34 +++
drivers/gpu/drm/i915/display/intel_dp.h | 4 +++
.../drm/i915/display/intel_dp_link_training.c | 32 -
3 files changed, 38 inserti
[Why]:
Aligh with DP spec wanted to follow same naming convention.
[How]:
Changed the macro name of the dpcd address used for getting requested
test-pattern.
Cc: Harry Wentland
Cc: Alex Deucher
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
include
revision as function argument in set_phy_pattern api.
- used int for link_rate and u8 for lane_count to align with existing code.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/drm_dp_helper.c | 93 +
include/drm/drm_dp_helper.h | 31 +++
2 files changed
Reviewed-by: Manasi Navare
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/drm_dp_helper.c | 94 +
include/drm/drm_dp_helper.h | 31 +++
2 files changed, 125 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index
[Why]:
Aligh with DP spec wanted to follow same naming convention.
[How]:
Changed the macro name of the dpcd address used for getting requested
test-pattern.
Cc: Harry Wentland
Cc: Alex Deucher
Reviewed-by: Harry Wentland
Reviewed-by: Manasi Navare
Signed-off-by: Animesh Manna
---
drivers
These debugfs entry will help testapp to understand the test request
during dp phy compliance mode.
Reviewed-by: Manasi Navare
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a
ointer for link_status. (Ville)
v3: Scrapped the initial patch, modified commit description accordingly.
- made non-static function and used intel_dp prefix. (Jani, Manasi)
Reviewed-by: Manasi Navare
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dp_link_trai
DP_COMP_CTL and DP_COMP_PAT register used to program DP
compliance pattern.
v1: Initial patch.
v2: used pipe instead of port in macro definition. [Manasi]
Reviewed-by: Manasi Navare
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_reg.h | 20
1 file changed, 20
Taylor
Cc: Manasi Navare
Signed-off-by: Animesh Manna
Signed-off-by: Khaled Almahallawy
---
drivers/gpu/drm/i915/display/intel_dp.c | 147
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
2 files changed, 148 insertions(+)
diff --git a/drivers/gpu/drm/i915/display
During DP phy compliance auto test mode, sink will request
combination of different test pattern with differnt level of
vswing, pre-emphasis. Function added to prepare for it.
Reviewed-by: Manasi Navare
Signed-off-by: Animesh Manna
---
.../drm/i915/display/intel_display_types.h| 1
for fixes and test execution)
v5: Fixed some nitpicks by Manasi.
Animesh Manna (7):
drm/amd/display: Align macro name as per DP spec
drm/dp: get/set phy compliance pattern
drm/i915/dp: Made intel_dp_adjust_train() non-static
drm/i915/dp: Preparation for DP phy compliance auto test
drm/i915
DP_COMP_CTL and DP_COMP_PAT register used to program DP
compliance pattern.
v1: Initial patch.
v2: used pipe instead of port in macro definition. [Manasi]
v3: used trans_offset for offset calculation. [Manasi]
Reviewed-by: Manasi Navare
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915
]
Reviewed-by: Manasi Navare
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_reg.h | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 309cb7d96b35..465862ed2cf8 100644
--- a/drivers/gpu/drm/i915
moved to intel_crtc_state from intel_crtc. [Maarten]
Cc: Maarten Lankhorst
Cc: Ville Syrjälä
Cc: Jani Nikula
Cc: Daniel Vetter
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_color.c| 19 +-
drivers/gpu/drm/i915/display/intel_display.c | 47 -
.../drm/i915
On 7/30/2019 7:20 PM, Anshuman Gupta wrote:
Adding following definition to i915_reg.h
1. DC_STATE_EN register DC3CO bit fields and masks.
2. Transcoder EXITLINE register and its bit fields and mask.
Cc: Nikula, Jani
Cc: Deak, Imre
Cc: Manna, Animesh
Should be like below,
Cc: Animesh
Hi,
On 7/30/2019 7:20 PM, Anshuman Gupta wrote:
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 296452f9efe4..7a46dc957660 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -46,7 +46,8 @@ i915_param_named(mode
On 8/9/2019 3:12 PM, Jani Nikula wrote:
On Mon, 01 Jul 2019, Animesh Manna wrote:
Display State Buffer (DSB) is hardware capability which allows
driver to batch submit HW programming.
As part of initial enablement common api created which currently used
to program gamma lut proramming
From gen12 onwards Display State Buffer(DSB) is hardware capability
added which allows driver to batch submit display HW programming.
Feature flag has_dsb added to identify the driver/platform support
at runtime.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu
DSB support single register write through opcode 0x1. Generic
api created which accumulate all single register write in a batch
buffer and once DSB is triggered, it will program all the registers
at the same time.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu
changes in I915_READ definition as DSB do not have support to
read any register.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 6 +-
2 files changed, 6 insertions(+), 2 deletions
DSB can program large set of data through indexed register write
(opcode 0x9) in one shot. Will be using for bulk register programming
e.g. gamma lut programming, HDR meta data programming.
Cc: Shashank Sharma
Cc: Imre Deak
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
Freed the gem object after completion of dsb workload.
Cc: Shashank Sharma
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 23 +++
drivers/gpu/drm/i915/display/intel_dsb.h | 1 +
2 files changed, 24 insertions
-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 40
1 file changed, 40 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index 4a38277dc4b1..f97d0c06a049 100644
--- a/drivers/gpu/drm/i915
Gamma lut programming can be programmed using DSB
where bulk register programming can be done using indexed
register write which takes number of data and the mmio offset
to be written.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_color.c
Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_reg.h | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c4a17034d4dc..a1a9d09b6420 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers
-off-by: Animesh Manna
Animesh Manna (15):
drm/i915/dsb: feature flag added for display state buffer.
drm/i915/dsb: DSB context creation.
drm/i915/dsb: single register write function for DSB.
drm/i915/dsb: Added enum for reg write capability.
drm/i915/dsb: Indexed register write function
The function will internally get the gem buffer from global GTT
which is mapped in cpu domain to feed the data + opcode for DSB engine.
Cc: Imre Deak
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/Makefile | 1
As per bspec check for DSB status before programming any
of its register. Inline function added to check the dsb status.
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 9 +
1 file changed, 9 insertions
: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 43
drivers/gpu/drm/i915/display/intel_dsb.h | 1 +
2 files changed, 44 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
DSB can access specific register, To identify those register
which can be written through DSB, enum reg_write_cap is added
to hold the capability.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_reg.h | 13 -
1 file changed, 12
Added docbook info regarding Display State Buffer(DSB) which
is added from gen12 onwards to batch submit display HW programming.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
Documentation/gpu/i915.rst | 9
drivers/gpu/drm/i915/display/intel_dsb.c | 54
The dsb get call added part of the prepare so that we don't
have things that can fail in the commit proper.
The allocated dsb-context will be tracked under intel_crtc_state
instead of intel_crtc per atomic-commit.
Cc: Ville Syrjälä
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh
DSB context destroyed using intel_dsb_put() in cleanup function.
Cc: Ville Syrjälä
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_display.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/display
Hi,
On 8/21/2019 11:41 PM, Chris Wilson wrote:
Quoting Animesh Manna (2019-08-21 07:32:22)
The function will internally get the gem buffer from global GTT
which is mapped in cpu domain to feed the data + opcode for DSB engine.
Cc: Imre Deak
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo
Hi,
On 8/21/2019 11:57 PM, Chris Wilson wrote:
Quoting Animesh Manna (2019-08-21 07:32:25)
DSB can program large set of data through indexed register write
(opcode 0x9) in one shot. Will be using for bulk register programming
e.g. gamma lut programming, HDR meta data programming.
Cc
Hi,
On 8/22/2019 12:13 AM, Chris Wilson wrote:
Quoting Animesh Manna (2019-08-21 07:32:30)
Batch buffer will be created through dsb-reg-write function which can have
single/multiple request based on usecase and once the buffer is ready
commit function will trigger the execution of the batch
On 8/22/2019 6:53 PM, Jani Nikula wrote:
On Wed, 21 Aug 2019, Animesh Manna wrote:
Gamma lut programming can be programmed using DSB
where bulk register programming can be done using indexed
register write which takes number of data and the mmio offset
to be written.
No. Please stick to
Added docbook info regarding Display State Buffer(DSB) which
is added from gen12 onwards to batch submit display HW programming.
v1: Initial version as RFC.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Acked-by: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
Documentation/gpu/i915.rst | 9
be derived through vma object. (Chris)
Cc: Imre Deak
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/Makefile | 1 +
.../drm/i915/display/intel_display_types.h| 3 +
drivers/gpu/drm/i915/display/intel_dsb.c
Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_reg.h | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 02e1ef10c47e..71c6c2380443 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers
DSB support single register write through opcode 0x1. Generic
api created which accumulate all single register write in a batch
buffer and once DSB is triggered, it will program all the registers
at the same time.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu
-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 40
1 file changed, 40 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index d36ee8244427..2d6e78868f2d 100644
--- a/drivers/gpu/drm/i915
As per bspec check for DSB status before programming any
of its register. Inline function added to check the dsb status.
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 9 +
1 file changed, 9 insertions
-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_color.c | 64 ++
drivers/gpu/drm/i915/i915_drv.h| 2 +
2 files changed, 43 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display
From gen12 onwards Display State Buffer(DSB) is hardware capability
added which allows driver to batch submit display HW programming.
Feature flag has_dsb added to identify the driver/platform support
at runtime.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu
Sharma
Cc: Swati Sharma
Cc: Lucas De Marchi
Signed-off-by: Animesh Manna
Animesh Manna (11):
drm/i915/dsb: feature flag added for display state buffer.
drm/i915/dsb: DSB context creation.
drm/i915/dsb: single register write function for DSB.
drm/i915/dsb: Indexed register write function
code few places. (Chris)
Cc: Imre Deak
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 42
drivers/gpu/drm/i915/display/intel_dsb.h | 1 +
2 files changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/i915
: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 48
drivers/gpu/drm/i915/display/intel_dsb.h | 8
2 files changed, 56 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm
Enabling DSB by setting 1 to has_dsb flag for gen12.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index
On 8/28/2019 7:31 PM, Sharma, Shashank wrote:
Hello Animesh
On 8/28/2019 12:40 AM, Animesh Manna wrote:
From gen12 onwards Display State Buffer(DSB) is hardware capability
added which allows driver to batch submit display HW programming.
Let's rephrase this line a bit, how about:
D
Hi,
On 8/28/2019 8:09 PM, Sharma, Shashank wrote:
On 8/28/2019 12:40 AM, Animesh Manna wrote:
The function will internally get the gem buffer from global GTT
This patch adds a function, which will internally get the gem buffer
for DSB engine.
which is mapped in cpu domain to feed the data
Hi,
On 8/28/2019 8:46 PM, Sharma, Shashank wrote:
On 8/28/2019 12:40 AM, Animesh Manna wrote:
DSB support single register write through opcode 0x1. Generic
api created which accumulate all single register write in a batch
buffer and once DSB is triggered, it will program all the registers
at
Hi,
On 8/28/2019 10:16 PM, Sharma, Shashank wrote:
On 8/28/2019 12:40 AM, Animesh Manna wrote:
DSB can program large set of data through indexed register write
(opcode 0x9) in one shot. Will be using for bulk register programming
Reshuffle-> This feature can be used for bulk regis
Hi,
On 8/28/2019 10:32 PM, Sharma, Shashank wrote:
On 8/28/2019 12:40 AM, Animesh Manna wrote:
Added key register definitions of DSB.
dsb-ctrl register is required to enable dsb-engine.
head-ptr register hold the head of buffer address from where the
execution will start.
Programming tail
Hi,
On 8/28/2019 10:37 PM, Sharma, Shashank wrote:
On 8/28/2019 12:40 AM, Animesh Manna wrote:
DSB will be used for performance improvement for some special scenario.
DSB engine will be enabled based on need and after completion of its
work
will be disabled. Api added for enable/disable
Hi,
On 8/28/2019 11:45 PM, Sharma, Shashank wrote:
On 8/28/2019 12:40 AM, Animesh Manna wrote:
Gamma lut programming can be programmed using DSB
where bulk register programming can be done using indexed
register write which takes number of data and the mmio offset
to be written.
v1: Initial
. Below dsb api added to do respective job
mentioned below.
intel_dsb_init - allocate the DSB buffer.
intel_dsb_prepare - pin and map the buffer.
intel_dsb_cleanup - Unpin and release the gem object.
RFC: Inital patch for design review.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display
patch.
Cc: Jani Nikula
Cc: Matthew Auld
Cc: Ramalingam C
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_atomic.c | 2 +
drivers/gpu/drm/i915/display/intel_display.c | 13 ++
drivers/gpu/drm/i915/display/intel_dsb.c | 132 ---
drivers/gpu/drm/i915/display/intel_dsb.h | 2 +
4 files changed, 101 insertions(+), 48 deletions
: Jani Nikula
Cc: Daniel Vetter
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_display.c | 36 -
drivers/gpu/drm/i915/display/intel_dsb.c | 132 ---
drivers/gpu/drm/i915/display/intel_dsb.h | 2 +
3 files changed, 116 insertions(+), 54
moved to intel_crtc_state from intel_crtc. [Maarten]
v5: dsb get/put/ref-count mechanism removed. [Maarten]
Cc: Maarten Lankhorst
Cc: Ville Syrjälä
Cc: Jani Nikula
Cc: Daniel Vetter
Acked-by: Daniel Vetter
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_color.c| 27
. [Maarten]
- few dsb functions prototype modified to simplify code.
Cc: Maarten Lankhorst
Cc: Ville Syrjälä
Cc: Jani Nikula
Cc: Daniel Vetter
Acked-by: Daniel Vetter
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_atomic.c | 3 +
drivers/gpu/drm/i915/display/intel_color.c
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_atomic.c | 3 +
drivers/gpu/drm/i915/display/intel_color.c| 51 ++--
drivers/gpu/drm/i915/display/intel_display.c | 58 -
.../drm/i915/display/intel_display_types.h| 6 +-
drivers/gpu/drm/i915/display/intel_dsb.c
]
Cc: Maarten Lankhorst
Cc: Ville Syrjälä
Cc: Jani Nikula
Cc: Daniel Vetter
Acked-by: Daniel Vetter
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_atomic.c | 3 +
drivers/gpu/drm/i915/display/intel_color.c| 66 ++---
drivers/gpu/drm/i915/display/intel_display.c
]
v9: error handling improved in _write() and prepare(). [Maarten]
Cc: Maarten Lankhorst
Cc: Ville Syrjälä
Cc: Jani Nikula
Cc: Daniel Vetter
Acked-by: Daniel Vetter
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_atomic.c | 3 +
drivers/gpu/drm/i915/display
]
v9: error handling improved in _write() and prepare(). [Maarten]
Cc: Maarten Lankhorst
Cc: Ville Syrjälä
Cc: Jani Nikula
Cc: Daniel Vetter
Acked-by: Daniel Vetter
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_atomic.c | 3 +
drivers/gpu/drm/i915/display
]
v9: error handling improved in _write() and prepare(). [Maarten]
Cc: Maarten Lankhorst
Cc: Ville Syrjälä
Cc: Jani Nikula
Cc: Daniel Vetter
Acked-by: Daniel Vetter
Reviewed-by: Maarten Lankhorst
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_atomic.c | 3 +
drivers
From: Maarten Lankhorst
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_frontbuffer.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.c
b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
index d898b370d7a4..0f1d7a
These debugfs entry will help testapp to understand the test request
during dp phy compliance mode.
Acked-by: Manasi Navare
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a
/enable as well during ddi disable/enable.
- harcoded PLTPAT 80 bit custom pattern as the DPR-100 does not set it
in the sink’s DPCDs
- TRANS_DDI_FUNC_CTL DDI_Select (Bits 27:30) need to reset/set during
disable/enable.
Cc: Clinton Taylor
Cc: Manasi Navare
Signed-off-by: Animesh Manna
Signed-off-by
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/drm_dp_helper.c | 94 +
include/drm/drm_dp_helper.h | 31 +++
2 files changed, 125 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index c6fbe6e6bc9d..28e59d1ffa93
During DP phy compliance auto test mode, sink will request
combination of different test pattern with differnt level of
vswing, pre-emphasis. Function added to prepare for it.
Reviewed-by: Manasi Navare
Signed-off-by: Animesh Manna
---
.../drm/i915/display/intel_display_types.h| 1
DP_COMP_CTL and DP_COMP_PAT register used to program DP
compliance pattern.
Reviewed-by: Manasi Navare
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_reg.h | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm
for fixes and test execution)
Animesh Manna (7):
drm/amd/display: Align macro name as per DP spec
drm/dp: get/set phy compliance pattern
drm/i915/dp: Made intel_dp_adjust_train() non-static.
drm/i915/dp: Preparation for DP phy compliance auto test
drm/i915/dp: Add debugfs entry for DP phy
[Why]:
Aligh with DP spec wanted to follow same naming convention.
[How]:
Changed the macro name of the dpcd address used for getting requested
test-pattern.
Cc: Harry Wentland
Cc: Alex Deucher
Reviewed-by: Harry Wentland
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/amd/display/dc/core
ointer for link_status. (Ville)
v3: Scrapped the initial patch, modified commit description accordingly.
- made non-static function and used intel_dp prefix. (Jani, Manasi)
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dp_link_training.c | 9 -
drivers/gpu/drm/i9
Changes done:
- Added identifier for Mipi transcoder A and C.
- Added power domain identifier for newly added mipi trancoder.
- Initialized transcoder for mipi during compute config.
v1: Initial RFC version.
v2: Rebased on tot.
Cc: Jani Nikula
Signed-off-by: Animesh Manna
---
drivers/gpu/drm
hotplug
interrupt as pcu_hpd_interrupt which will come via pmc. So
added the interrupt handling for pcu hpd interrupt.
Signed-off-by: Animesh Manna
Signed-off-by: A.Sunil Kamath
---
drivers/gpu/drm/i915/i915_irq.c | 56 ++---
drivers/gpu/drm/i915/i915_reg.h
Guid is changed for bxt platform, so corrected the guid for bxt.
v1: Initial version as RFC.
v2: Based on review comment from Jani and David,
have kept guid as binary format.
Signed-off-by: Ananth Krishna R
Signed-off-by: Bharath K Veera
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915
comments from Jani,
- Used bool instead of enum for hpd feature flag.
- Updating feature flag at the first place based on vbt
entry.
Signed-off-by: Animesh Manna
Signed-off-by: A.Sunil Kamath
---
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/intel_bios.c | 6
for hpd_wakeup_enabled is removed before
calling pci_restore_state.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_drv.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 4f0e56d..bc48642 100644
--- a
version after addressing review comments from Imre,David.
Animesh Manna (5):
drm/i915/bxt: Corrected the guid for bxt.
drm/i915/bxt: VBT changes for hpd as wakeup feature
drm/i915/bxt: Added _DSM call to set HPD_CTL.
drm/i915/bxt: Block D3 during suspend.
drm/i915: Enable HPD interrupts
_DSM is added to program HPD_CTL(0x1094) register
of PMC from i915 driver which will be called
based on driver feature flag. PMC hpd control register
programming will enable PMC to get hpd interrupt
during dc9.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/intel_acpi.c | 44
On 11/23/2016 10:02 PM, Chris Wilson wrote:
On Wed, Nov 23, 2016 at 09:48:23PM +0530, Animesh Manna wrote:
Guid is changed for bxt platform, so corrected the guid for bxt.
v1: Initial version as RFC.
v2: Based on review comment from Jani and David,
have kept guid as binary format.
Signed
On 11/23/2016 10:31 PM, Imre Deak wrote:
On Wed, 2016-11-23 at 21:48 +0530, Animesh Manna wrote:
While suspending the device hpd related interrupts are enabled
to get the interrupt when device is in suspend state.
Though display is in DC9 but system can be in S0 or S0i3 state.
Hot plug
On 11/23/2016 10:40 PM, Ville Syrjälä wrote:
On Wed, Nov 23, 2016 at 09:48:27PM +0530, Animesh Manna wrote:
While suspending the device hpd related interrupts are enabled
to get the interrupt when device is in suspend state.
Though display is in DC9 but system can be in S0 or S0i3 state.
Hot
On 11/23/2016 11:47 PM, Ville Syrjälä wrote:
On Wed, Nov 23, 2016 at 09:48:25PM +0530, Animesh Manna wrote:
_DSM is added to program HPD_CTL(0x1094) register
of PMC from i915 driver which will be called
based on driver feature flag. PMC hpd control register
programming will enable PMC to get
On 11/28/2016 4:54 PM, Jani Nikula wrote:
On Mon, 28 Nov 2016, Animesh Manna wrote:
On 11/23/2016 10:02 PM, Chris Wilson wrote:
On Wed, Nov 23, 2016 at 09:48:23PM +0530, Animesh Manna wrote:
Guid is changed for bxt platform, so corrected the guid for bxt.
v1: Initial version as RFC.
v2
_DSM is added to program HPD_CTL(0x1094) register
of PMC from i915 driver which will be called
based on driver feature flag. PMC hpd control register
programming will enable PMC to get hpd interrupt
during dc9.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/intel_acpi.c | 45
hotplug
interrupt as pcu_hpd_interrupt which will come via pmc. So
added the interrupt handling for pcu hpd interrupt.
Signed-off-by: Animesh Manna
Signed-off-by: A.Sunil Kamath
---
drivers/gpu/drm/i915/i915_irq.c | 56 ++---
drivers/gpu/drm/i915/i915_reg.h
To support hpd during sleep a new feature flag is
added in vbt and also in dev_priv for enabling/disabling
inside deiver. By default this feature will be
diabled and based on oem request this feature can
be enabled by changing vbt feature flag.
Signed-off-by: Animesh Manna
Signed-off-by: A.Sunil
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