Hi Nirmoy,
[...]
> +void intel_gt_mcr_lock_reset(struct intel_gt *gt)
> +{
> + unsigned long __flags;
> +
> + lockdep_assert_not_held(>->uncore->lock);
> +
> + spin_lock_irqsave(>->mcr_lock, __flags);
> +
> + if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))
> + intel
Hi Nirmoy,
> + /*
> + * For the media GT, this ring fault register is not replicated,
> + * so don't do multicast/replicated register read/write operation on it.
> + */
thanks!
Andi
From: Nirmoy Das
Commit f1530f912ed8 ("drm/i915/gt: Apply workaround 22016122933
correctly") adds the workaround only in non media GT's, which is
GT-0 in case of MTL. It turns out that we need to apply it in
both the GT's.
Signed-off-by: Nirmoy Das
Signed-off-by: Andi
Hi Nirmoy,
your client is still missing my e-mails? :)
> +void intel_gt_mcr_lock_reset(struct intel_gt *gt)
> +{
> + unsigned long __flags;
> +
> + lockdep_assert_not_held(>->uncore->lock);
> +
> + spin_lock_irqsave(>->mcr_lock, __flags);
> +
> + if (GRAPHICS_VER_FULL(gt->i915) >=
> process by other agents.
>
> v2: reset on resume not in intel_gt_init().
> v3: do the reset on intel_gt_resume_early()
>
> Signed-off-by: Nirmoy Das
In the previous version I added my r-b here. Please consider it
for the next version:
Reviewed-by: Andi Shyti
Even
Hi Nirmoy,
On Wed, Sep 27, 2023 at 11:03:55PM +0200, Nirmoy Das wrote:
> Move early resume functions of gt to a proper file.
>
> Signed-off-by: Nirmoy Das
> ---
> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 6 ++
> drivers/gpu/drm/i915/gt/intel_gt_pm.h | 1 +
> drivers/gpu/drm/i915/i915_driver.
> > >
> > > v2: reset on resume not in intel_gt_init().
> > > v3: do the reset on intel_gt_resume_early()
> > >
> > > Signed-off-by: Nirmoy Das
> > In the previous version I added my r-b here.
> I moved code to different function so wanted t
c(Matt)
> s/intel_gt_mcr_lock_clear/intel_gt_mcr_lock_sanitize
>
> Signed-off-by: Nirmoy Das
Reviewed-by: Andi Shyti
Andi
Hi,
> + do {
> + /*
> + * Starting with MTL, we need to coordinate not only with other
> + * driver threads, but also with hardware/firmware agents. A
> + * dedicated locking register is used.
> + */
> + if (GRAPHICS_
27;t release it?
Open for opinions or profligate rejections :-)
I'm also curious to see what CI has to say about.
[*] https://patchwork.freedesktop.org/series/124397/
Signed-off-by: Andi Shyti
Cc: Nirmoy Das
Cc: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 46 ++
Hi Nirmoy,
On Thu, Sep 28, 2023 at 03:00:13PM +0200, Nirmoy Das wrote:
> Move early resume functions of gt to a proper file.
>
> Signed-off-by: Nirmoy Das
Reviewed-by: Andi Shyti
Andi
Hi Matt,
> > While discussing with Nirmoy offline about this other way for
> > fixing lock contention, he was a bit sceptical about it.
> >
> > But why not? We know that if we fall into this case it's because
> > some hardware component has forgotten to release the lock within
> > 100ms. So that
Hi Nirmoy,
On Mon, Oct 02, 2023 at 02:20:32PM +0200, Nirmoy Das wrote:
> Don't return early if one of the GT doesn't require
> any flushing.
>
> Fixes: d6c531ab4820 ("drm/i915: Invalidate the TLBs on each GT")
> Cc: Chris Wilson
> Cc: Fei Yang
> Cc
Hi Jani,
adding a few folks in Cc for some extra eyes on this series.
On Mon, Oct 02, 2023 at 11:47:01AM +0300, Jani Nikula wrote:
> Chopping up [1] to more digestable pieces. Start off with nuking
> i915->gt0.
>
> [1] https://patchwork.freedesktop.org/series/124418/
>
> Jani Nikula (3):
> dr
;
> Signed-off-by: Chris Wilson
> Signed-off-by: Jonathan Cavitt
> CC: Matt Roper
> CC: Andi Shyti
Reviewed-by: Andi Shyti
As Nirmoy has been needing this on a different context, could you
please send just this one as a separate e-mail?
This should also fix d6c531ab4820 ("drm/i
Hi Jani,
> adding a few folks in Cc for some extra eyes on this series.
>
> On Mon, Oct 02, 2023 at 11:47:01AM +0300, Jani Nikula wrote:
> > Chopping up [1] to more digestable pieces. Start off with nuking
> > i915->gt0.
> >
> > [1] https://patchwork.freedesktop.org/series/124418/
> >
> > Jani
Hi Jani,
On Mon, Oct 02, 2023 at 11:47:02AM +0300, Jani Nikula wrote:
> Have to give up the const on i915 pointer, but it's not big of a deal
> considering non-const i915 gets passed all over the place.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Andi Shyti
Thanks,
Andi
Hi Jani,
On Mon, Oct 02, 2023 at 11:47:03AM +0300, Jani Nikula wrote:
> Convert i915->gt0 to a pointer, and allocate it dynamically.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Andi Shyti
Thanks,
Andi
Hi Jani,
On Mon, Oct 02, 2023 at 11:47:04AM +0300, Jani Nikula wrote:
> Since gt0 == i915->gt[0], just drop the former.
>
> Signed-off-by: Jani Nikula
Looks correct!
Reviewed-by: Andi Shyti
Thanks,
Andi
Hi,
> Possible regressions
>
> • igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a3:
> □ shard-dg2: PASS -> INCOMPLETE
I believe this is not caused by this patch. I'm going to push it.
Andi
Hi Jani,
> > Consider multi-gt support when cancelling all tlb invalidations on
> > suspend, and when submitting tlb invalidations on resume.
> >
> > Suggested-by: Tvrtko Ursulin
> > Signed-off-by: Fei Yang
> > Signed-off-by: Jonathan Cavitt
> > CC: John Harrison
>
> I guess I'm wondering why
Hi,
[...]
> > +static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
> > +{
> > + struct drm_i915_private *i915 = ggtt->vm.i915;
> > + struct intel_gt *gt;
> > +
> > + if (!IS_GEN9_LP(i915) && GRAPHICS_VER(i915) < 11)
> > + gen8_ggtt_invalidate(ggtt);
> > +
> > + list_for_each
tem.
>
> Fixes: d6c531ab4820 ("drm/i915: Invalidate the TLBs on each GT")
> Signed-off-by: Chris Wilson
> Signed-off-by: Jonathan Cavitt
> CC: Matt Roper
> CC: Andi Shyti
> Reviewed-by: Andi Shyti
pushed to drm-intel-gt-next.
Thank you,
Andi
Hi John,
> > > > - mmio_invalidate_full(gt);
> > > > + if (INTEL_GUC_SUPPORTS_TLB_INVALIDATION(guc)) {
> > > > + if (intel_guc_is_ready(guc))
> > > > + intel_guc_invalidate_tlb_full(guc);
> > > > + } else
From: Chris Wilson
Enforce that an mmap of a dmabuf is always using MAP_SHARED so that all
access (both read and writes) using the device memory and not a local
copy-on-write page in system memory.
Signed-off-by: Chris Wilson
Signed-off-by: Andi Shyti
---
drivers/dma-buf/dma-buf.c | 15
Hi Vivaik,
On Tue, Oct 03, 2023 at 08:40:12PM -0700, Vivaik Balasubrawmanian wrote:
> Due to a bug in GuC firmware, Mesa can't enable by default the usage of
> async compute engines feature in DG2 and newer. A new GuC firmware fixed the
> issue but
> until now there was no way for Mesa to know
supposed to do, ignoring the problem.
Do not consider this failure as an error, but just print a debug
message stating that the MCR locking has been skipped.
On the driver side we still have spinlocks that make sure that
the access to the resources is serialized.
Signed-off-by: Andi Shyti
Cc
river side we still have spinlocks that make sure that
> > the access to the resources is serialized.
> >
> > Signed-off-by: Andi Shyti
> > Cc: Jonathan Cavitt
> > Cc: Matt Roper
> > Cc: Nirmoy Das
> > ---
> > drivers/gpu/drm/i915/gt/intel
; Signed-off-by: Jonathan Cavitt
Jani was mentioning that the pci tags is not a proper title.
No need to resend, I think I will merge this series, so that, if
you agree, I can change /pci tags/pci flag/ before pushing.
In any case.
Reviewed-by: Andi Shyti
Andi
> ---
> drivers/gp
Hi John,
> > > Add pci (device info) tags for if GuC TLB Invalidation is enabled.
> > > Since GuC based TLB invalidation is only strictly necessary for MTL
> > > resently, only enable GuC based TLB invalidations for MTL.
> > >
> > > Signed-off-by: Jonathan Cavitt
> > Jani was mentioning that the
> > > message stating that the MCR locking has been skipped.
> > > >
> > > > On the driver side we still have spinlocks that make sure that
> > > > the access to the resources is serialized.
> > > >
> > > > Signed-off-by: Andi Shyti
> > > > Add pci (device info) tags for if GuC TLB Invalidation is enabled.
> > > > Since GuC based TLB invalidation is only strictly necessary for MTL
> > > > resently, only enable GuC based TLB invalidations for MTL.
> > > >
> > > > Signed-off-by: Jonathan Cavitt
> > > Jani was mentioning that t
> > > > > > Do not consider this failure as an error, but just print a debug
> > > > > > message stating that the MCR locking has been skipped.
> > > > > >
> > > > > > On the driver side we still have spinlock
> > > > > > Do not consider this failure as an error, but just print a debug
> > > > > > message stating that the MCR locking has been skipped.
> > > > > >
> > > > > > On the driver side we still have spinlock
the connector for NULL but dereference it before that.
>
> Fixes: e046d1562491 ("drm/i915/hdmi: Use connector->ddc everwhere")
>
> Signed-off-by: Suraj Kandpal
please don't leave a blank line in the tag section. No need to
resend, I guess whoever will merge this patc
static int intel_hdmi_reset_link(struct intel_encoder
> *encoder,
> u8 config;
> int ret;
>
> - if (!connector || connector->base.status != connector_status_connected)
> + if (connector->base.status != connector_status_connected)
based on Jani's an
Hi Jonathan,
> CI changes
>
> Possible regressions
>
> • boot:
> □ bat-dg1-5: PASS -> FAIL
>
> IGT changes
>
> Possible regressions
>
> • igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling:
>
> □ bat-adlm-1: PASS -> INCOMPLETE
> • igt@kms_busy@basic@flip:
>
> □ ba
Hi,
> > CI changes
> >
> > Possible regressions
> >
> > • boot:
> > □ bat-dg1-5: PASS -> FAIL
> >
> > IGT changes
> >
> > Possible regressions
> >
> > • igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling:
> >
> > □ bat-adlm-1: PASS -> INCOMPLETE
> > • igt@kms_busy@basic@
Hi Jonathan,
> - if (intel_uc_wants_guc(&ggtt->vm.gt->uc))
> + if (intel_uc_wants_guc_submission(&ggtt->vm.gt->uc))
I think the failures we see in CI come from here. I think you had
it right the first time, this should have both the checks:
if (intel_uc_wants_guc(&ggtt->vm.gt->uc
Given a reference to "guc", the guc_to_i915() returns the
pointer to "i915" private data.
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt.h| 5 +
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 2 +-
drivers/gpu/drm/i915/gt/uc/intel_g
f-by: Daniele Ceraolo Spurio
> Reviewed-by: Vinay Belgaumkar
Reviewed-by: Andi Shyti
Andi
Hi Tvrtko,
> A little bit of house keeping, trimming off some pre-production hardware and
> incomplete platform support.
>
> Tvrtko Ursulin (3):
> drm/i915: Remove early/pre-production Haswell code
> drm/i915: Remove incomplete PVC plumbing
> drm/i915: Remove xehpsdv support
That's a very
Hi Tvrtko,
On Fri, Oct 06, 2023 at 09:31:01AM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> It is not our policy to keep pre-production hardware support for this long
> so I guess this one was just forgotten.
>
> Signed-off-by: Tvrtko Ursulin
Reviewed-by: Andi Shyti
Andi
Hi Carl,
> > > besides this, ask a dumb question.
> > > How we retrieve the pat_index from a shared resource though dma_buf fd?
> > > maybe we need to know whether it could be CPU cached if we want map it.
> > > Of course, looks there are no real usage to access it though CPU.
> > > Just use it di
o fix by changing the #ifdef to
> an IS_ENABLED() check that the compiler can see through.
>
> Signed-off-by: Arnd Bergmann
Reviewed-by: Andi Shyti
Andi
> ---
> I saw this last week already, so it's likely that someone else already sent
> a fix for it.
>
>
Hi Arnd,
On Mon, Jun 12, 2023 at 02:43:59PM +0200, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> When CONFIG_PNP is disabled, the mchbar_addr variable is only written but
> not read:
>
> drivers/gpu/drm/i915/soc/intel_gmch.c: In function
> 'intel_alloc_mchbar_resource':
> drivers/gpu/drm/i915
struct
> i915_drm_client *client)
>
> struct i915_drm_client *i915_drm_client_alloc(void);
>
> -#ifdef CONFIG_PROC_FS
> void i915_drm_client_fdinfo(struct drm_printer *p, struct drm_file *file);
> -#endif
nice! This is becoming the new trend now.
Reviewed-by: Andi Shyti
Andi
Hi Tvrtko,
On Fri, Jun 16, 2023 at 12:17:50PM +0100, Tvrtko Ursulin wrote:
>
> On 16/06/2023 11:16, Andi Shyti wrote:
> > Hi Arnd,
> >
> > On Fri, Jun 16, 2023 at 11:31:47AM +0200, Arnd Bergmann wrote:
> > > From: Arnd Bergmann
> > >
> > >
Hi Tejas,
On Mon, Jun 19, 2023 at 02:33:26PM +0530, Tejas Upadhyay wrote:
> WA 14018778641 needs an update after recent
> performance data on MTL, aligning driver here with
> HW WA update.
>
> Signed-off-by: Tejas Upadhyay
Reviewed-by: Andi Shyti
Andi
Hi Tejas,
On Mon, Jun 19, 2023 at 02:33:26PM +0530, Tejas Upadhyay wrote:
> WA 14018778641 needs an update after recent
> performance data on MTL, aligning driver here with
> HW WA update.
>
> Signed-off-by: Tejas Upadhyay
pushed to drm-intel-gt-next.
Thanks,
Andi
or,-Wunused-but-set-variable]
>
> Change this to an IS_ENABLED() check to let the compiler see how
> it's used and no longer warn about it.
>
> Signed-off-by: Arnd Bergmann
Reviewed-by: Andi Shyti
Thanks,
Andi
Hi Thomas,
On Thu, Jun 22, 2023 at 12:14:11PM +0200, Thomas Hellström wrote:
> On eviction errors other than -EMULTIHOP we were leaking a resource.
> Fix.
>
> Fixes: 403797925768 ("drm/ttm: Fix multihop assert on eviction.")
> Cc: Andrey Grodzovsky
> Cc: Christian König
> Cc: Christian Koenig
tian König
> Cc: "Christian König"
> Cc: dri-de...@lists.freedesktop.org
> Cc: # v5.14+
> Signed-off-by: Thomas Hellström
Reviewed-by: Andi Shyti
Andi
egligible/
> removing them helps the display code reuse in the Xe driver.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Andi Shyti
Andi
Hi Christian and Thomas,
> > > > > diff --git a/drivers/gpu/drm/ttm/ttm_bo.c
> > > > > b/drivers/gpu/drm/ttm/ttm_bo.c
> > > > > index 615d30c4262d..89530f2a027f 100644
> > > > > --- a/drivers/gpu/drm/ttm/ttm_bo.c
> > > > > +++ b/drivers/gpu/drm/ttm/ttm_bo.c
> > > > > @@ -462,14 +462,14 @@ static i
Hi,
as there are new hardware directives, we need a little
adaptation for the AUX invalidation sequence.
This series was already proposed in the past but received no
comment. Respinning it again :)
Andi
Jonathan Cavitt (2):
drm/i915/gt: Ensure memory quiesced before invalidation
drm/i915/gt
From: Jonathan Cavitt
All memory traffic must be quiesced before requesting
an aux invalidation on platforms that use Aux CCS.
Signed-off-by: Jonathan Cavitt
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a
From: Jonathan Cavitt
For platforms that use Aux CCS, wait for aux invalidation to
complete by checking the aux invalidation register bit is
cleared.
Signed-off-by: Jonathan Cavitt
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 17 +
drivers/gpu
Hi Arnd,
On Thu, Jun 22, 2023 at 12:18:41PM +0200, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> The mchbar_addr variable is only used inside of an #ifdef:
>
> drivers/gpu/drm/i915/soc/intel_gmch.c:41:6: error: variable 'mchbar_addr' set
> but not used [-Werror,-Wunused-but-set-variable]
>
>
Hi Julia,
On Fri, Jun 23, 2023 at 11:14:47PM +0200, Julia Lawall wrote:
> Use array_size to protect against multiplication overflows.
>
> The changes were done using the following Coccinelle semantic patch:
>
> //
> @@
> expression E1, E2;
> constant C1, C2;
> identifier alloc = {vm
Hi Thomas,
On Mon, Jun 26, 2023 at 11:14:49AM +0200, Thomas Hellström wrote:
> On eviction errors other than -EMULTIHOP we were leaking a resource.
> Fix.
>
> v2:
> - Avoid yet another goto (Andi Shyti)
>
> Fixes: 403797925768 ("drm/ttm: Fix multihop assert o
.
Thanks,
Andi
Changelog:
=
v1 -> v2
- add a clean up preliminary patch for the existing registers
- add support for more engines
- add the Fixes tag
Andi Shyti (2):
drm/i915/gt: Cleanup aux invalidation registers
drm/i915/gt: Support aux invalidation on all engines
Jonathan Cav
on't exist.
Signed-off-by: Andi Shyti
Cc: # v5.8+
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 8
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 14 ++
drivers/gpu/drm/i915/gt/intel_lrc.c | 6 +++---
3 files changed, 13 insertions(+), 15 deletions(-)
diff --git a/
From: Jonathan Cavitt
All memory traffic must be quiesced before requesting
an aux invalidation on platforms that use Aux CCS.
Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
Signed-off-by: Jonathan Cavitt
Signed-off-by: Andi Shyti
Cc: # v5.8+
--
From: Jonathan Cavitt
For platforms that use Aux CCS, wait for aux invalidation to
complete by checking the aux invalidation register bit is
cleared.
Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
Signed-off-by: Jonathan Cavitt
Signed-off-by: Andi
gines")
Signed-off-by: Andi Shyti
Cc: Mika Kuoppala
Cc: # v5.8+
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 63 +++-
drivers/gpu/drm/i915/gt/gen8_engine_cs.h | 3 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 17 +--
3 files changed, 44 insertions(+), 39 deletions(-)
di
t; > >
> > > i915_gem_get_pat_index: function to convert cache_level to PAT index.
> > >
> > > obj_to_i915(obj): macro moved to header file for wider usage.
> > >
> > > I915_MAX_CACHE_LEVEL: upper bound of i915_cache_level for the
> > >
Hi Jani,
On Tue, Jun 27, 2023 at 10:53:01AM +0300, Jani Nikula wrote:
> On Thu, 22 Jun 2023, Andi Shyti wrote:
> > Hi Jani,
> >
> > On Wed, Jun 21, 2023 at 09:38:05PM +0300, Jani Nikula wrote:
> >> Convert the raw_reg_read() and raw_reg_write() calls in display GU
ta.
>
> Fixes: 5e352e32aec2 ("drm/i915: preparation for using PAT index")
> Suggested-by: Tvrtko Ursulin
> Cc: Fei Yang
> Cc: Andi Shyti
> Cc: Andrzej Hajda
> Cc: Matt Roper
> Signed-off-by: Jani Nikula
thanks for fixing this!
Reviewed-by: Andi Shyti
Andi
pat_index instead of cache_level")
> Cc: Fei Yang
> Cc: Andi Shyti
> Cc: Matt Roper
Reviewed-by: Andi Shyti
Andi
ksys_write+0x64/0xe0
> #1: 888136c7eab8 (&attr->mutex){+.+.}-{3:3}, at:
> simple_attr_write_xsigned.constprop.0+0x47/0x110
> #2: 88813e6cce90 (>->reset.mutex){+.+.}-{3:3}, at:
> intel_gt_reset+0x19e/0x470 [i915]
>
> v2: Add sync flag to guc_cancel_busyness_work
Hi Andrzej,
On Thu, Jul 06, 2023 at 05:16:11PM +0200, Andrzej Hajda wrote:
> GuC virtual engines can be removed before request removal. On the other
> side driver expects rq->engine to be a valid pointer for a whole life of
> request. Setting rq->engine to an always valid engine should solve
> the
6. unclaimed_reg_debug tries to assert non-taken lock (first WARN)
> 7. unclaimed_reg_debug tries to release non-taken lock (second WARN)
>
> Closes:https://gitlab.freedesktop.org/drm/intel/-/issues/8749
> Signed-off-by: Lee Shawn C
> Cc: Uma Shankar
> Cc: Matt Roper
&g
>> - return;
> >> -
> >
> > this is a very good catch! I'm fine with the change from my side:
> >
> > Reviewed-by: Andi Shyti
>
> Nope, there's a bug in the patch.
>
> https://lore.kernel.org/r/87ilb00zot@intel.com
OK, I missed your reply.
Thanks, Jani!
Andi
Hi Andrzej,
> drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 11 +++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index a0e3ef1c65d246..2
Hi Nirmoy,
On Fri, Jun 30, 2023 at 07:01:39PM +0200, Nirmoy Das wrote:
> Use smem on MTL due to a HW bug in MTL that prevents
> reading from stolen memory using LMEM BAR.
>
> Cc: Oak Zeng
> Cc: Jani Nikula
> Cc: Joonas Lahtinen
> Cc: Andi Shyti
> Cc: Andrzej Hajda
Hi Nirmoy,
On Fri, Jun 30, 2023 at 07:01:40PM +0200, Nirmoy Das wrote:
> Use smem on MTL due to a HW bug in MTL that prevents
> reading from stolen memory using LMEM BAR.
>
> Cc: Oak Zeng
> Cc: Jani Nikula
> Cc: Joonas Lahtinen
> Cc: Andi Shyti
> Cc: Andrzej Hajda
Sent: June 30, 2023 1:02 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Das, Nirmoy ; Zeng, Oak ; Jani
> > Nikula ; Joonas Lahtinen
> > ; Andi Shyti ;
> > Hajda, Andrzej
> > Subject: [PATCH 1/2] drm/i915/gt: Do not use stolen on MTL
> >
> > Use sme
311348 05/31/2023
> Call Trace:
>
> ...
> xehp_is_valid_b_counter_addr+0x2c7/0x350 [i915]
>
> Fixes: 0fa9349dda030f ("drm/i915/perf: complete programming whitelisting for
> XEHPSDV")
> Signed-off-by: Andrzej Hajda
Reviewed-by: Andi Shyti
Andi
Hi Nirmoy,
> > @@ -301,11 +336,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32
> > mode)
> > cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);
> > - if (!HAS_FLAT_CCS(rq->engine->i915)) {
> > - /* hsdes: 1809175790 */
>
> We shoul
Hi Nirmoy and Jonathan,
> > > > @@ -202,6 +202,13 @@ int gen12_emit_flush_rcs(struct i915_request *rq,
> > > > u32 mode)
> > > >{
> > > > struct intel_engine_cs *engine = rq->engine;
> > > > + /*
> > > > +* Aux invalidations on Aux CCS platforms require
> > > > +
tch 2 for enabling the EMIT_FLUSH flag.
v1 -> v2
- add a clean up preliminary patch for the existing registers
- add support for more engines
- add the Fixes tag
Andi Shyti (3):
drm/i915/gt: Cleanup aux invalidation registers
drm/i915/gt: Enable the CCS_FLUSH bit in the pipe control
dr
From: Jonathan Cavitt
All memory traffic must be quiesced before requesting
an aux invalidation on platforms that use Aux CCS.
Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
Signed-off-by: Jonathan Cavitt
Signed-off-by: Andi Shyti
Cc: # v5.8+
--
on't exist.
Signed-off-by: Andi Shyti
Cc: # v5.8+
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 8
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 14 ++
drivers/gpu/drm/i915/gt/intel_lrc.c | 6 +++---
3 files changed, 13 insertions(+), 15 del
Enable the CCS_FLUSH bit 13 in the control pipe for render and
compute engines in platforms starting from Meteor Lake (BSPEC
43904 and 47112).
Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
Signed-off-by: Andi Shyti
Cc: Jonathan Cavitt
Cc: Nirm
From: Jonathan Cavitt
For platforms that use Aux CCS, wait for aux invalidation to
complete by checking the aux invalidation register bit is
cleared.
Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
Signed-off-by: Jonathan Cavitt
Signed-off-by: Andi
gines")
Signed-off-by: Andi Shyti
Cc: # v5.8+
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 63 +++-
drivers/gpu/drm/i915/gt/gen8_engine_cs.h | 3 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 17 +--
3 files changed, 44 insertions(+), 39 deletions(-)
diff --git a/drive
ary patch for the existing registers
- add support for more engines
- add the Fixes tag
Andi Shyti (4):
drm/i915/gt: Cleanup aux invalidation registers
drm/i915/gt: Rename flags with bit_group_X according to the datasheet
drm/i915/gt: Enable the CCS_FLUSH bit in the pipe control
drm/i915/gt
on't exist.
Signed-off-by: Andi Shyti
Cc: # v5.8+
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 8
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 14 ++
drivers/gpu/drm/i915/gt/intel_lrc.c | 6 +++---
3 files changed, 13 insertions(+), 15 del
From: Jonathan Cavitt
All memory traffic must be quiesced before requesting
an aux invalidation on platforms that use Aux CCS.
Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
Signed-off-by: Jonathan Cavitt
Signed-off-by: Andi Shyti
Cc: # v5.8+
--
From: Jonathan Cavitt
For platforms that use Aux CCS, wait for aux invalidation to
complete by checking the aux invalidation register bit is
cleared.
Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
Signed-off-by: Jonathan Cavitt
Signed-off-by: Andi
ently only
PIPE_CONTROL0_HDC_PIPELINE_FLUSH bit is set.
Signed-off-by: Andi Shyti
Cc: # v5.8+
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 34 +---
1 file changed, 18 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
b/drivers/gpu/d
Enable the CCS_FLUSH bit 13 in the control pipe for render and
compute engines in platforms starting from Meteor Lake (BSPEC
43904 and 47112).
Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
Signed-off-by: Andi Shyti
Cc: Jonathan Cavitt
Cc: Nirm
gines")
Signed-off-by: Andi Shyti
Cc: # v5.8+
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 63 +++-
drivers/gpu/drm/i915/gt/gen8_engine_cs.h | 3 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 17 +--
3 files changed, 44 insertions(+), 39 deletions(-)
diff --git a/drive
Hi,
On Mon, Jul 17, 2023 at 07:30:56PM +0200, Andi Shyti wrote:
> In preparation of the next patch allign with the datasheet (BSPEC
> 47112) with the naming of the pipe control set of flag values.
> The variable "flags" in gen12_emit_flush_rcs() is applied as a
> set of fl
Hi Matt,
On Mon, Jul 17, 2023 at 01:31:03PM -0700, Matt Roper wrote:
> On Mon, Jul 17, 2023 at 10:54:37AM -0700, Matt Roper wrote:
> > On Mon, Jul 17, 2023 at 07:30:55PM +0200, Andi Shyti wrote:
> > > From: Jonathan Cavitt
> > >
> > > All memory traffi
Hi Andrzej,
On Mon, Jul 17, 2023 at 08:21:40PM +0200, Andrzej Hajda wrote:
> On 17.07.2023 19:30, Andi Shyti wrote:
> > In preparation of the next patch allign with the datasheet (BSPEC
> > 47112) with the naming of the pipe control set of flag values.
> > Th
Hi Andrzej,
On Mon, Jul 17, 2023 at 09:11:26PM +0200, Andrzej Hajda wrote:
> On 17.07.2023 19:30, Andi Shyti wrote:
> > Perform some refactoring with the purpose of keeping in one
> > single place all the operations around the aux table
> > invalidation.
> >
> &g
Hi Matt,
On Mon, Jul 17, 2023 at 01:27:09PM -0700, Matt Roper wrote:
> On Mon, Jul 17, 2023 at 07:30:59PM +0200, Andi Shyti wrote:
> > Perform some refactoring with the purpose of keeping in one
> > single place all the operations around the aux table
> > invalidatio
Hi Matt,
> > > > > + /*
> > > > > + * Aux invalidations on Aux CCS platforms require
> > > > > + * memory traffic is quiesced prior.
> > > > > + */
> > > > > + if ((mode & EMIT_INVALIDATE) && !HAS_FLAT_CCS(engine->i915))
> > > >
> > > > It's a pre-existing mistake in drm-ti
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