I think nothing opened here... one comment from Nirmoy I see that
has been addressed.
Reviewed-by: Andi Shyti
Reviewed-by: Andrzej Hajda
Acked-by: Nirmoy Das
Andi
buffers as WC on CPU side. Since such allocations are
> not all done through GuC allocator, to avoid too many code changes,
> the i915_coherent_map_type() is now hard coded to return WC for MTL.
>
> BSpec: 45101
>
> Signed-off-by: Fei Yang
Reviewed-by: Andi Shyti
Acked-by: N
de at BO creation time.
>
> Signed-off-by: Fei Yang
Reviewed-by: Andi Shyti
Reviewed-by: Andrzej Hajda
Andi
the cache_level is not completely removed yet, because the KMD still
> has the need of creating buffer objects with simple cache settings such as
> cached, uncached, or writethrough. For such simple cases, using cache_level
> would help simplify the code.
>
> Cc: Chris Wilson
> Cc: Matt Roper
> Signed-off-by: Fei Yang
Reviewed-by: Andi Shyti
Andi
ngly in this version. see above.
oh... sorry... I got confused... never mind! :)
Thanks!
Andi
> > Reviewed-by: Andi Shyti
> > Reviewed-by: Andrzej Hajda
> > Reviewed-by: Nirmoy Das
> >
> > Andi
t; obj_to_i915(obj): macro moved to header file for wider usage.
>
> I915_MAX_CACHE_LEVEL: upper bound of i915_cache_level for the
> convenience of coding.
>
> Cc: Chris Wilson
> Cc: Matt Roper
> Cc: Andi Shyti
> Signed-off-by: Fei Yang
Reviewed-by: Andi Shyti
Andi
et PAT index for the object
> at creation time.
> The new extension is platform independent, so UMD's can switch to using
> this extension for older platforms as well, while {set, get}_caching are
> still supported on these legacy paltforms for compatibility reason.
>
> Cc: Chr
Hi Fei,
On Wed, Apr 19, 2023 at 04:00:50PM -0700, fei.y...@intel.com wrote:
> From: Fei Yang
>
> The series includes patches needed to enable MTL.
> Also add new extension for GEM_CREATE uAPI to let
> user space set cache policy for buffer objects.
>
> v2: addressing review comments and checkpa
nt, so UMD's can switch to using
> this extension for older platforms as well, while {set, get}_caching are
> still supported on these legacy paltforms for compatibility reason.
>
> Cc: Chris Wilson
> Cc: Matt Roper
> Cc: Andi Shyti
> Signed-off-by: Fei Yang
> Reviewed
set PAT index for the object
> >>> at creation time.
> >>> The new extension is platform independent, so UMD's can switch to using
> >>> this extension for older platforms as well, while {set, get}_caching are
> >>> still supported on these lega
Hajda
Reviewed-by: Nirmoy Das
Reviewed-by: Andi Shyti
Signed-off-by: Andi Shyti
---
Hi,
just extracting this patch from Fei's series.
Andi
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 6 +-
drivers/gpu/drm/i915/gt/intel_gtt.c | 47 ++-
drivers/gpu/drm/i915/gt/intel_
On Thu, Apr 20, 2023 at 02:23:22PM -0700, Matt Roper wrote:
> On Thu, Apr 20, 2023 at 11:13:52PM +0200, Andi Shyti wrote:
> > From: Madhumitha Tolakanahalli Pradeep
> >
> >
> > On MTL, GT can no longer allocate on LLC - only the CPU can.
> > This, along with
change the i915_irq.h, which is a
bit tricky (but not much) as the "dev_priv" is hardcoded inside
some defines.
Andi
Andi Shyti (2):
drm/i915/i915_drv: Use proper parameter naming in for_each_gt()
drm/i915/i915_drv: Use i915 instead of dev_priv insied the file_priv
structure
for_each_gt() loops through engines in the GT, not in dev_priv.
Because it's misleading, call it "gt__" instead of "dev_priv__".
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/driver
In the process of renaming all instances of 'dev_priv' to 'i915',
start using 'i915' within the 'drm_i915_file_private' structure.
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/i915_drv.h | 458
1 file changed, 2
Hi Rodrigo,
On Fri, Apr 21, 2023 at 10:05:07AM -0400, Rodrigo Vivi wrote:
> On Fri, Apr 21, 2023 at 10:00:29AM -0400, Rodrigo Vivi wrote:
> > On Fri, Apr 21, 2023 at 03:46:53PM +0200, Andi Shyti wrote:
> > > for_each_gt() loops through engines in the GT, not in dev_priv.
On Fri, Apr 21, 2023 at 10:07:28AM -0400, Rodrigo Vivi wrote:
> On Fri, Apr 21, 2023 at 03:46:54PM +0200, Andi Shyti wrote:
> > In the process of renaming all instances of 'dev_priv' to 'i915',
> > start using 'i915' within the 'drm_i915_file_pri
Hi,
just extracting this patch from Fei's series.
Andi
Changelog:
==
v1 -> v2:
Taken from Fei's new series: https://patchwork.freedesktop.org/series/115980/
- Removed unnecessary defines
- Place the selftest patches in a different patch
Fei Yang (1):
drm/i915/mtl: fix mocs selftest
From: Fei Yang
Media GT has a different base for MOCS register, need to apply
gsi_offset to the mmio address if not using the intel_uncore_r/w
functions for register access.
Cc: Matt Roper
Signed-off-by: Fei Yang
Reviewed-by: Matt Roper
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt
Reviewed-by: Andrzej Hajda
Reviewed-by: Nirmoy Das
Reviewed-by: Andi Shyti
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 6 ++-
drivers/gpu/drm/i915/gt/intel_gtt.c | 47 -
drivers/gpu/drm/i915/gt/intel_gtt.h | 8 +++
drivers/gpu/drm/i915/gt
rly the commit of patch 2.
Andi Shyti (2):
drm/i915/i915_drv: Use proper parameter naming in for_each_engine()
drm/i915/i915_drv: Use i915 instead of dev_priv insied the file_priv
structure
drivers/gpu/drm/i915/i915_drv.h | 462
1 file changed, 231 inser
for_each_engine() loops through engines in the GT, not in
dev_priv. Because it's misleading, call it "gt__" instead of
"dev_priv__".
Signed-off-by: Andi Shyti
Reviewed-by: Rodrigo Vivi
Reviewed-by: Andrzej Hajda
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
1 file ch
In the process of renaming all instances of 'dev_priv' to 'i915',
start using 'i915' within the i915_drv.h file.
Signed-off-by: Andi Shyti
Reviewed-by: Andrzej Hajda
---
drivers/gpu/drm/i915/i915_drv.h | 458
1 file changed, 22
Hi,
On Fri, Apr 21, 2023 at 08:25:33PM +0200, Andi Shyti wrote:
> Hi,
>
> just extracting this patch from Fei's series.
>
> Andi
>
> Changelog:
> ==
> v1 -> v2:
> Taken from Fei's new series: https://patchwork.freedesktop.org/series/115980/
Hi,
On Fri, Apr 21, 2023 at 03:46:52PM +0200, Andi Shyti wrote:
> Hi,
>
> just another "Friday patch". While reviewing some patches from
> Tejas I found a bit confusing the use of dev_priv__ inside the
> for_each_engine(), perhaps it should be moved inside the gt/?
>
at it I made the /dev_priv/i915/ change which is still
> >> harmless. Next in queue is to change the i915_irq.h, which is a
> >> bit tricky (but not much) as the "dev_priv" is hardcoded inside
> >> some defines.
> >>
> >> Andi
> >>
> &g
This reverts commit faca6aaa4838c3c234caa619d3c7d1f09da0d303.
This patch, in series with the next "Define MOCS and PAT tables
for MTL" are causing boot failures for MTL.
Revert them both.
Signed-off-by: Andi Shyti
Cc: Fei Yang
Cc: Matt Roper
---
drivers/gpu/drm/i915/gt/selftest_
Hi,
The two patches reverted in this series are, together, preventing
MTL from booting.
Revert them until the fix is deployed.
Andi
Andi Shyti (2):
Revert "drm/i915/mtl: fix mocs selftest"
Revert "drm/i915/mtl: Define MOCS and PAT tables for MTL"
drivers/gpu/drm/i91
This reverts commit b76c0deef6273609c02ed5053209f6397cd1b0fb.
This patch is causing boot failures for MTL.
Revert it.
Signed-off-by: Andi Shyti
Cc: Matt Roper
Cc: Lucas De Marchi
Cc: Aravind Iddamsetty
Cc: Nirmoy Das
Cc: Fei Yang
Cc: Andrzej Hajda
---
drivers/gpu/drm/i915/gt
Hi Tejas,
On Mon, Apr 24, 2023 at 07:06:07PM +0530, Tejas Upadhyay wrote:
> igt_live_test has pr_err dumped in case of some
> GT failures. It will be more informative regarding
> GT if we use gt_err instead.
>
> Cc: Andi Shyti
> Signed-off-by: Tejas Upadhyay
Thanks for t
Hi Tejas,
On Mon, Apr 24, 2023 at 03:47:49PM +0530, Tejas Upadhyay wrote:
> WA 18018781329 is applicable now across all MTL
> steppings.
>
> V2:
> - Remove IS_MTL check, code already running for MTL - Matt
>
> Cc: Matt Roper
> Signed-off-by: Tejas Upadhyay
Reviewed-by: Andi Shyti
Andi
Hi Tejas,
On Mon, Apr 24, 2023 at 07:06:07PM +0530, Tejas Upadhyay wrote:
> igt_live_test has pr_err dumped in case of some
> GT failures. It will be more informative regarding
> GT if we use gt_err instead.
>
> Cc: Andi Shyti
> Signed-off-by: Tejas Upadhyay
pushed to
Hi Tejas,
On Mon, Apr 24, 2023 at 03:47:49PM +0530, Tejas Upadhyay wrote:
> WA 18018781329 is applicable now across all MTL
> steppings.
>
> V2:
> - Remove IS_MTL check, code already running for MTL - Matt
>
> Cc: Matt Roper
> Signed-off-by: Tejas Upadhyay
pushed in drm-intel-gt-next.
Than
d
> the last release, but the advantages outweigh it.
>
> Signed-off-by: Andrzej Hajda
Reviewed-by: Andi Shyti
Andi
niele Ceraolo Spurio
> Cc: Alan Previn
> Cc: Umesh Nerlige Ramappa
> Cc: Rodrigo Vivi
> Cc: Matthew Brost
> Cc: Andi Shyti
> Cc: Matthew Auld
> Cc: Tvrtko Ursulin
> Cc: Lucas De Marchi
> Cc: Jani Nikula
Reviewed-by: Andi Shyti
Andi
Hi,
> Andrzej Hajda (7):
> lib/ref_tracker: add unlocked leak print helper
> lib/ref_tracker: improve printing stats
> lib/ref_tracker: add printing to memory buffer
> lib/ref_tracker: remove warnings in case of allocation failure
> drm/i915: Correct type of wakeref v
ates
>
> Fixes: 95ccf312a1e4 ("drm/i915/guc/slpc: Allow SLPC to use efficient
> frequency")
> Signed-off-by: Vinay Belgaumkar
> Reviewed-by: Rodrigo Vivi
> Reviewed-by: Ashutosh Dixit
Reviewed-by: Andi Shyti
Andi
> ---
> drivers/gpu/drm/i915/gt/
-by: Vinay Belgaumkar
Reviewed-by: Andi Shyti
Andi
y: Andrzej Hajda
> Signed-off-by: Andrzej Hajda
Reviewed-by: Andi Shyti
Andi
n see who
> either tried to free a stale wakeref, or who forgot to free theirs.
>
> Signed-off-by: Andrzej Hajda
Reviewed-by: Andi Shyti
Andi
Hi Mika,
> +static void intel_c20_pll_program(struct drm_i915_private *i915,
> + const struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> +{
> + const struct intel_c20pll_state *pll_state =
> &crtc_state->cx0pl
l address space for the page table to be flushed after
> initialization, so we must also add a flush statement there.
>
> Signed-off-by: Jonathan Cavitt
> Reviewed-by: Matthew Auld
> Signed-off-by: Andrzej Hajda
Reviewed-by: Andi Shyti
Andi
Hi Mika,
[...]
> +static int intel_c20_phy_check_hdmi_link_rate(int clock)
> +{
> + const struct intel_c20pll_state * const *tables = mtl_c20_hdmi_tables;
> + int i;
> +
> + for (i = 0; tables[i]; i++) {
> + if (clock == tables[i]->link_bit_rate)
> + re
Hi Mika,
> +
> + if (intel_c20_use_mplla(hw_state->clock)) {
> + for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++)
> + drm_dbg_kms(&i915->drm, "mplla[%d] = 0x%.4x\n", i,
> hw_state->mplla[i]);
> + } else {
> + for (i = 0; i < ARRAY_SIZE(hw_state
Hi Mika,
On Thu, Apr 20, 2023 at 03:40:44PM +0300, Mika Kahola wrote:
> Enabling and disabling sequence for Thunderbolt PLL.
if you will resend it:
/Enabling/Enable/
Andi
)
> {
> - pgprotval_t preservebits = pgprot_val(oldprot) & _PAGE_CHG_MASK;
> - pgprotval_t addbits = pgprot_val(newprot) & ~_PAGE_CHG_MASK;
> + unsigned long mask = _PAGE_CHG_MASK | _PAGE_CACHE_MASK;
nice catch!
Reviewed-by: Andi Shyti
Thanks,
Andi
> +
> + pgprotval_t preservebits = pgprot_val(oldprot) & mask;
> + pgprotval_t addbits = pgprot_val(newprot) & ~mask;
> return __pgprot(preservebits | addbits);
> }
>
> --
> 2.40.0
Hi Janusz,
On Mon, Apr 24, 2023 at 02:35:24PM +0200, Janusz Krzysztofik wrote:
> Visible glitches have been observed when running graphics applications on
> Linux under Xen hypervisor. Those observations have been confirmed with
> failures from kms_pwrite_crc Intel GPU test that verifies data coh
Hi Tejas,
On Fri, Apr 28, 2023 at 06:29:51PM +0530, Tejas Upadhyay wrote:
> It will be more informative regarding
> GT if we use gt_err instead.
>
> Cc: Andi Shyti
> Signed-off-by: Tejas Upadhyay
Thanks for this cleanup!
Reviewed-by: Andi Shyti
Andi
Hi Tejas,
On Fri, Apr 28, 2023 at 06:29:52PM +0530, Tejas Upadhyay wrote:
> It will be more informative regarding
> GT if we use gt_err instead.
>
> Cc: Andi Shyti
> Signed-off-by: Tejas Upadhyay
Reviewed-by: Andi Shyti
Andi
Hi,
a kind reminder on this patch, would be fantastic if anyone from
the x86 maintainers cha give it a look.
The patch has been tested thoroughly and even if it's marked as
an RFC in my opinion it can be already considered for a proper
review.
Thanks,
Andi
On Mon, Apr 24, 2023 at 02:35:24PM +02
Hi Tvrtko,
sorry for the very late reply, it's about time to bring this
patch up.
On Thu, Apr 13, 2023 at 12:56:00PM +0100, Tvrtko Ursulin wrote:
>
> On 12/04/2023 12:33, Andi Shyti wrote:
> > Currently, when we perform operations such as clearing or copying
> > lar
Hi Tvrtko,
> Another option - maybe - is this related to revert of fence error
> propagation? If it is and having that would avoid the need for this invasive
> fix, maybe we unrevert 3761baae908a7b5012be08d70fa553cc2eb82305 with edits
> to limit to special contexts? If doable..
I think that is no
Hi JP,
On Thu, May 04, 2023 at 01:28:02PM +0300, Juha-Pekka Heikkila wrote:
> From: Pallavi Mishra
>
> Remove FLAT CCS check from XY_FAST_COLOR_BLT usage, thus
> enabling MTL to use it.
>
> Signed-off-by: Pallavi Mishra
> Signed-off-by: Juha-Pekka Heikkila
Reviewed-by:
On Thu, May 04, 2023 at 01:28:03PM +0300, Juha-Pekka Heikkila wrote:
> From: Clint Taylor
>
> Add support for remapping CCS FBs on MTL to remove the restriction
> of the power-of-two sized stride and the 2MB surface offset alignment
> for these FBs.
The alignment here is off.
Andi
RM.debug calls already comport with this: 207 DRM_DEV_DEBUG,
> 1288 drm_dbg. Clean up the remainders, in maintainer sized chunks.
>
> No functional changes.
>
> Signed-off-by: Jim Cromie
Reviewed-by: Andi Shyti
Andi
Hi,
this bit of code escaped the multi-gt wave from a couple of years
ago.
Andi
Andi Shyti (2):
drm/i915: Split gt cache flushing and gt idling functions
drm/i915: When asked to drop the cache, do it per GT
drivers/gpu/drm/i915/i915_debugfs.c | 44 +
1 file
In preparation for multi-gt cache flushing debugfs interface,
split the cache dropping function and gt idling.
Based on a patch by Tvrtko.
Signed-off-by: Andi Shyti
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_debugfs.c | 32 +
1 file changed, 24 insertions
When the user sends the drop caches command through the debugfs
interface, do it on all the GT's, rather than just the root GT.
Based on a patch by Tvrtko.
Signed-off-by: Andi Shyti
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_debugfs.c | 18 --
1 file change
Hi John,
> > > > > > static void guc_cancel_busyness_worker(struct intel_guc *guc)
> > > > > > {
> > > > > > - cancel_delayed_work_sync(&guc->timestamp.work);
> > > > > > + /*
> > > > > > +* When intel_gt_reset was called, task will hold a lock.
> > > > > > +* To cacel delayed
Hi Radhakrishna,
On Tue, Sep 05, 2023 at 12:36:24PM -0700, Radhakrishna Sripada wrote:
> Meteorlake has been very usable for a while now, all of uapi changes
> related to fundamental platform usage have been finalized and all
> required firmware blobs are available. Recent CI results have also
> b
> > Meteorlake has been very usable for a while now, all of uapi changes
> > related to fundamental platform usage have been finalized and all
> > required firmware blobs are available. Recent CI results have also
> > been healthy, so we're ready to drop the force_probe requirement and
> > enable t
Hi Nirmoy,
please ignore this series... I'm going to send Tvrtko's original
work. The changes in patch 1 are not required.
Thank you!
Andi
On Thu, Sep 07, 2023 at 11:04:33AM +0200, Nirmoy Das wrote:
>
> On 9/5/2023 9:36 PM, Andi Shyti wrote:
> > In preparation for m
From: Tvrtko Ursulin
Walk all GTs when doing the respective bits of drop_caches work.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Andi Shyti
---
Hi,
I'm proposing this new version of the series I sent here[*].
Patch 1 from that series is not necessary so taht I'm going to
p
being used
> for soft-rc6).
>
> Signed-off-by: Chris Wilson
> Signed-off-by: Nirmoy Das
Reviewed-by: Andi Shyti
Andi
> - ret = gt_drop_caches(to_gt(i915), val);
> - if (ret)
> - return ret;
> + for_each_gt(i915, i, gt) {
argh... I forgot to add this change before formatting the patch
- for_each_gt(i915, i, gt) {
+ for_each_gt(gt, i915, i) {
Will resend.
Andi
From: Tvrtko Ursulin
Walk all GTs when doing the respective bits of drop_caches work.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Andi Shyti
---
Hi,
I'm proposing this new version of the series I sent here[*].
Patch 1 from that series is not necessary so taht I'm going to
p
Hi Nirmoy,
[...]
> + /* mark the bind context's availability status */
> + bool bind_context_ready;
Do we need some locking here?
> /**
>* pinned_contexts_list: List of pinned contexts. This list is only
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
> b/drivers/gpu/dr
Hi Nirmoy,
On Wed, Sep 06, 2023 at 01:31:20PM +0200, Nirmoy Das wrote:
> Implement GGTT update method with blitter command, MI_UPDATE_GTT
> and install those handlers if a platform requires that.
>
> v2: Make sure we hold the GT wakeref and Blitter engine wakeref before
> we call mutex_lock/intel
[...]
> +/**
> + * __for_each_daddr_next - iterates over the device addresses with
> pre-initialized iterator.
> + * @__dp:Device address (output)
> + * @__iter: 'struct sgt_iter' (iterator state, external)
> + * @__step: step size
> + */
> +#define __for_each_daddr_next(__dp, __iter, __ste
Hi Rodrigo and Nirmoy,
On Thu, Sep 07, 2023 at 09:47:19AM -0400, Rodrigo Vivi wrote:
> On Thu, Sep 07, 2023 at 02:58:08PM +0200, Andi Shyti wrote:
> > From: Tvrtko Ursulin
> >
> > Walk all GTs when doing the respective bits of drop_caches work.
> >
> > Signed-o
the workaround was added later it wasn't
checking whether obj had a valid value or not, leading to a
potential segfault.
Thanks for fixing it!
Reviewed-by: Andi Shyti
Andi
> /*
>* Wa_22016122933: For Media version 13.0, all Media GT shared
&g
Hi Dan,
> Possible regressions
>
> • igt@gem_ccs@ctrl-surf-copy-new-ctx:
>
> □ shard-mtlp: NOTRUN -> SKIP
> • igt@gen9_exec_parse@allowed-all:
>
> □ shard-apl: PASS -> INCOMPLETE
I believe these failures are not caused by this patch. I had to
retrigger the tests because the BAT
Hi Andrzej,
On Tue, Sep 12, 2023 at 09:35:21AM +0200, Andrzej Hajda wrote:
> Some DG2 firmware locks this register for modification. Using wa_add
> with read_mask 0 allows to skip checks of such registers.
>
> Signed-off-by: Andrzej Hajda
Reviewed-by: Andi Shyti
Andi
> ---
nathan Cavitt
> Cc: Andi Shyti
> Cc: # v5.8+
> Cc: Nirmoy Das
> Cc: Andrzej Hajda
> Cc: Tvrtko Ursulin
> Cc: Matt Roper
> Cc: Lucas De Marchi
> Cc: Tejas Upadhyay
> Cc: Prathap Kumar Valsan
> Signed-off-by: Nirmoy Das
Reviewed-by: Andi Shyti
and I believe
Tested-by: Tapani Pälli
Thanks,
Andi
Hi Nirmoy,
[...]
> ce = create_kernel_context(engine);
> if (IS_ERR(ce))
> return PTR_ERR(ce);
> + /*
> + * Create a separate pinned context for GGTT update with blitter engine
> + * if a platform require such service. MI_UPDATE_GTT works on other
> +
;
> Signed-off-by: Nirmoy Das
> Reviewed-by: Oak Zeng
Reviewed-by: Andi Shyti
Thanks,
Andi
Hi Nirmoy,
On Mon, Sep 18, 2023 at 07:02:53PM +0200, Nirmoy Das wrote:
> Implement a way to iterate over sgt with pre-initialized
> sgt_iter state.
>
> Signed-off-by: Nirmoy Das
> Reviewed-by: Oak Zeng
Reviewed-by: Andi Shyti
Andi
utex lock. It is a circular lock. So hold the GT/blitter engine wakeref
> before calling mutex_lock, to fix the circular lock.
>
> Signed-off-by: Nirmoy Das
> Signed-off-by: Oak Zeng
> Acked-by: Oak Zeng
Reviewed-by: Andi Shyti
Andi
_14019519902.
>
> Signed-off-by: Nirmoy Das
> Reviewed-by: Oak Zeng
Reviewed-by: Andi Shyti
Andi
Hi Nirmoy,
[...]
> > GEM_BUG_ON(!llist_empty(&engine->barrier_tasks));
> > cleanup_status_page(engine);
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > index a7e677598004..a8f527fab0f0 100644
> > --- a/drivers/gpu/drm/i
*gt)
{
__intel_gt_bind_context_set_ready(gt, gt);
}
I always had a personal dislike of booleans in arguments as they
mean very little to whoever reads them. On the other hand, set
ready to "false" is more meaningful than set unready. Your
choice.
Reviewed-by: Andi Shyti
Andi
ctly"). We see that
> there's already an implicit dependency on the i915_drv.h that we need to
> address too.
>
> Cc: Andi Shyti
> Cc: Fei Yang
> Cc: Jonathan Cavitt
> Cc: Matt Roper
> Signed-off-by: Jani Nikula
Reviewed-by: Andi Shyti
Andi
Hi Jani,
[...]
> > * upon acquiring the wakeref.
> > */
> > mutex_lock_nested(&wf->mutex, SINGLE_DEPTH_NESTING);
> > - if (!atomic_read(&wf->count)) {
> > - int err;
> >
> > - rpm_get(wf);
> > + if (likely(!atomic_read(&wf->count))) {
>
> Adding the likely
e region.
>
> v2:
> * Only account against the active region.
> * Use DMA_RESV_USAGE_BOOKKEEP when testing for active. (Tejas)
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Aravind Iddamsetty
> Cc: Rob Clark
> Cc: Andi Shyti
> Cc: Tejas Upadhyay
> Revi
> Cc: Jani Nikula
> Cc: Joonas Lahtinen
> Cc: Rodrigo Vivi
> Cc: Tvrtko Ursulin
> Cc: David Airlie
> Cc: Daniel Vetter
> Cc: Chris Wilson
> Cc: John Harrison
> Cc: Andi Shyti
> Cc: Matthew Brost
> Cc: intel-gfx@lists.freedesktop.org
> Cc: dri-de...@lists
adhakrishna Sripada
as this isn't merged yet:
Reviewed-by: Andi Shyti
Andi
Hi Jani,
On Thu, Sep 21, 2023 at 07:06:37PM +0300, Jani Nikula wrote:
> Just let the compiler decide what's best. Turns out absolutely nothing
> changes in the output with the inlines removed.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Andi Shyti
Andi
nore' info level one and just add the
> 'ignore' flag to the debug level one instead (which will therefore not
> appear by default but will still show up in CI runs).
>
> Signed-off-by: John Harrison
Reviewed-by: Andi Shyti
Andi
d int' here and I've seen it
reviewed. Personally, if I really have to express a preference, I
prefer 'int' because it's a bit safer, generally I don't really
mind :)
The rest looks good.
Reviewed-by: Andi Shyti
Andi
Hi Tvrtko,
On Mon, Sep 25, 2023 at 03:28:27PM +0100, Tvrtko Ursulin wrote:
>
> On 25/09/2023 15:14, Andi Shyti wrote:
> > Hi Tvrtko,
> >
> > On Wed, Sep 20, 2023 at 09:57:15AM +0100, Tvrtko Ursulin wrote:
> > > From: Tvrtko Ursulin
> > >
> >
Hi Jani,
> >>struct i915_vma *vma, *next;
> >>unsigned long freed_pages = 0;
> >>intel_wakeref_t wakeref;
> >> + struct intel_gt *gt;
> >> + int i;
> >
> > the trend is to use 'unsigned int' here and I've seen it
> > reviewed. Personally, if I really have to express a preference, I
>
Hi Tvrtko,
> Commit ade8a0f59844 ("drm/i915: Make all GPU resets atomic") added a
> preempt disable section over the hardware reset callback to prepare the
> driver for being able to reset from atomic contexts.
>
> In retrospect I can see that the work item at a time was about removing
> the stru
:
> * Fix timeouts which are now in us. (Andi)
> * Update one comment as a drive by. (Andi)
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Chris Wilson
> Cc: Paul Gortmaker
> Cc: Sebastian Andrzej Siewior
> Cc: Andi Shyti
Reviewed-by: Andi Shyti
Thanks,
Andi
Hi Nirmoy,
On Tue, Sep 26, 2023 at 04:24:01PM +0200, Nirmoy Das wrote:
> PIPE_CONTROL_FLUSH_L3 is not needed for aux invalidation
> so don't set that.
>
> Fixes: 78a6ccd65fa3 ("drm/i915/gt: Ensure memory quiesced before
> invalidation")
> Cc: Jonathan Cavitt
Hi Nirmoy,
...
> > PIPE_CONTROL_FLUSH_L3 is not needed for aux invalidation
> > so don't set that.
> >
> > Fixes: 78a6ccd65fa3 ("drm/i915/gt: Ensure memory quiesced before
> > invalidation")
> > Cc: Jonathan Cavitt
> > Cc: Andi Shyt
Hi Nirmoy,
On Tue, Sep 26, 2023 at 10:37:35AM +0200, Nirmoy Das wrote:
> Implement a way to update GGTT using MI_UPDATE_GTT command
> when possible for MTL as a suggested work around for HW bugs,
> Wa_13010847436 and Wa_14019519902.
>
> 1st patch improve pm wakeref handeling which needed as we
>
Cc: Aravind Iddamsetty
> Cc: Rob Clark
> Cc: Andi Shyti
> Cc: Tejas Upadhyay
> Reviewed-by: Andi Shyti # v1
> Reviewed-by: Aravind Iddamsetty # v2
Reviewed-by: Andi Shyti
Andi
Hi Nirmoy,
On Tue, Sep 26, 2023 at 11:58:02PM +0200, Nirmoy Das wrote:
> On MTL GEN12_RING_FAULT_REG is not replicated so don't
> do mcr based operation for this register.
>
> v2: use MEDIA_VER() instead of GRAPHICS_VER()(Matt).
>
> Signed-off-by: Nirmoy Das
This looks very good!
> - if (
;/"MEDIA_VER(i915) >= 13"(Matt)
> improve comment.
>
> Signed-off-by: Nirmoy Das
> Reviewed-by: Matt Roper
Reviewed-by: Andi Shyti
Andi
can occur in this
> process by other agents.
>
> Signed-off-by: Nirmoy Das
Reviewed-by: Andi Shyti
Andi
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