en used manually.
v1 -> v2
- fixed a couple of coding style issues in patch 2.
Andi Shyti (1):
drm/i915/gt: make a gt sysfs group and move power management files
Tvrtko Ursulin (1):
drm/i915: Prepare for multiple GTs
drivers/gpu/drm/i915/Makefile | 4 +-
drivers/gpu/drm
ure is in place to handle them.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
Signed-off-by: Andi Shyti
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Matthew Auld
Reviewed-by: Matt Roper
---
drivers/gpu/dr
gt0/
├── gt_RP0_freq_mhz|
└── gt_RP1_freq_mhz|
└── gt_RPn_freq_mhz -+
As soon as multitile platforms will start being supported, this
interface will allow to control the power (either manually or
with tools) on each tile, instead of affecting only tile 0 and
getting incomplete re
Hi Michal,
> please find few late nits below
thanks for the comments!
> > On a multi-tile platform, each tile has its own registers + GGTT
> > space, and BAR 0 is extended to cover all of them.
> >
> > Up to four gts are supported in i915->gt[], with slot zero
>
> s/gts/GTs (to match as below)
Hi Michal,
> > /sys/.../card0
> > ├── gt
> > │ ├── gt0
> > │ │ ├── id
> > │ │ ├── rc6_enable
> > │ │ ├── rc6_residency_ms
> > │ │ ├── rps_act_freq_mhz
> > │ │ ├── rps_boost_freq_mhz
> > │ │ ├── rps_cu
Ping... Lucas, do you mind merging this trivial refactoring?
Thanks,
Andi
On Sat, Nov 27, 2021 at 03:17:15AM +0200, Andi Shyti wrote:
> Change functions that always return '0' to be void type.
>
> Signed-off-by: Andi Shyti
> Cc: Maciej Patelczyk
> ---
&
Hi Tvrtko,
> > +bool is_object_gt(struct kobject *kobj)
>
> Not sure if you will need it exported in a later patch but for now it seems
> only users are local to this file.
it is actually used by sysfs_gt.c and sysfs_gt_pm.c.
Thank you,
Andi
PS. in this v4 I forgot to replace many drm_err() wi
Hi Joonas,
> > > The GT has its own properties and in sysfs they should be grouped
> > > in the 'gt/' directory.
> > >
> > > Create a 'gt/' directory in sysfs which will contain gt0...gtN
> > > directories related to each tile configured in the GPU. Move the
> > > power management files inside th
Hi Andrzej,
I'm sorry, but I'm not fully understanding,
> > > > +struct intel_gt *intel_gt_sysfs_get_drvdata(struct device *dev,
> > > > + const char *name)
> > > > +{
> > > > + struct kobject *kobj = &dev->kobj;
> > > > +
> > > > + /*
> > > >
> > > > > +struct intel_gt *intel_gt_sysfs_get_drvdata(struct device *dev,
> > > > > + const char *name)
> > > > > +{
> > > > > + struct kobject *kobj = &dev->kobj;
> > > > > +
> > > > > + /*
> > > > > + * We are interested at knowing from where
Hi Andrzej,
> > Now tiles have their own sysfs interfaces under the gt/
> > directory. Because RC6 is a property that can be configured on a
> > tile basis, then each tile should have its own interface
> >
> > The new sysfs structure will have a similar layout for the 4 tile
> > case:
> >
> > /s
Hi Andrzej,
[...]
> > +static ssize_t act_freq_mhz_show(struct device *dev,
> > +struct device_attribute *attr, char *buff)
> > +{
> > + s64 actual_freq = sysfs_gt_attribute_r_func(dev, attr,
> > + __act_freq_mhz_show);
>
Hi Michal,
[...]
> > +static ssize_t punit_req_freq_mhz_show(struct device *dev,
> > + struct device_attribute *attr,
> > + char *buff)
> > +{
> > + struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
> > +
line.
and some other minor refactoring.
v2 -> v3
- Added Matt and Sujaritha's r-b for patch 1 and 2.
- Reworded the commit of patch 2 to underline the fact that the
interface is useful also when used manually.
v1 -> v2
- fixed a couple of coding style issues in patc
With the upcoming multitile support each tile will have its own
local memory. Mark the current LMEM with the suffix '0' to
emphasise that it belongs to the root tile.
Suggested-by: Michal Wajdeczko
Signed-off-by: Andi Shyti
Reviewed-by: Michal Wajdeczko
Reviewed-by: Andrzej Hajda
--
The "gt_is_root(struct intel_gt *gt)" helper return true if the
gt is the root gt, which means that its id is 0. Return false
otherwise.
Suggested-by: Michal Wajdeczko
Signed-off-by: Andi Shyti
Reviewed-by: Michal Wajdeczko
Reviewed-by: Andrzej Hajda
---
drivers/gpu/drm/i915/gt/
ure is in place to handle them.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
Signed-off-by: Andi Shyti
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Matthew Auld
Reviewed-by: Matt Roper
---
drivers/gpu/dr
interfaces will be a basic tool for system
managers and administrators when using i915.
Signed-off-by: Andi Shyti
Cc: Matt Roper
Cc: Sujaritha Sundaresan
Cc: Tvrtko Ursulin
Reviewed-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/gt/intel_gt.c
the existing one to more tiles. In any
case this new set of interfaces will be a basic tool for system
managers and administrators when using i915.
Signed-off-by: Andi Shyti
Signed-off-by: Lucas De Marchi
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Matt Roper
Cc: Sujaritha Sundaresan
Cc: Tvr
is not really adding exposing new interfaces (new
ABI) other than adapting the existing one to more tiles. In any
case this new set of interfaces will be a basic tool for system
managers and administrators when using i915.
Signed-off-by: Andi Shyti
Signed-off-by: Lucas De Marchi
Cc: Chris Wilson
- throttle_reason_prochot
- throttle_reason_ratl
- throttle_reason_vr_thermalert
- throttle_reason_vr_tdc
Signed-off-by: Sujaritha Sundaresan
Cc: Dale B Stimson
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 74 +
drivers/gpu/drm/i915
> • igt@i915_selftest@mock@requests:
>
> □ shard-kbl: PASS -> DMESG-FAIL
>
> □ shard-tglb: PASS -> DMESG-FAIL
>
> □ shard-apl: PASS -> DMESG-FAIL
>
> □ shard-glk: PASS -> DMESG-FAIL
>
> □ shard-skl: PASS -> DMESG-FAIL
>
> □ shard-snb: PASS -> DMESG-FAIL
>
On Fri, Mar 18, 2022 at 01:19:18PM +, Matthew Auld wrote:
> On 18/03/2022 02:10, Andi Shyti wrote:
> > Now that we have tiles we want each of them to have its own
> > interface. A directory "gt/" is created under "cardN/" that will
> > contain as many
Hi Matt and Tvrtko,
> On 18/03/2022 13:25, Matthew Auld wrote:
> > On Fri, 18 Mar 2022 at 08:18, Andi Shyti wrote:
> > >
> > > >• igt@i915_selftest@mock@requests:
> > > >
> > > >□ shard-kbl: PASS -> DMESG-FAIL
line.
and some other minor refactoring.
v2 -> v3
- Added Matt and Sujaritha's r-b for patch 1 and 2.
- Reworded the commit of patch 2 to underline the fact that the
interface is useful also when used manually.
v1 -> v2
- fixed a couple of coding style issues in patc
With the upcoming multitile support each tile will have its own
local memory. Mark the current LMEM with the suffix '0' to
emphasise that it belongs to the root tile.
Suggested-by: Michal Wajdeczko
Signed-off-by: Andi Shyti
Reviewed-by: Michal Wajdeczko
Reviewed-by: Andrzej Hajda
--
The "gt_is_root(struct intel_gt *gt)" helper return true if the
gt is the root gt, which means that its id is 0. Return false
otherwise.
Suggested-by: Michal Wajdeczko
Signed-off-by: Andi Shyti
Reviewed-by: Michal Wajdeczko
Reviewed-by: Andrzej Hajda
---
drivers/gpu/drm/i915/gt/
ure is in place to handle them.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
Signed-off-by: Andi Shyti
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Matthew Auld
Reviewed-by: Matt Roper
---
drivers/gpu/dr
interfaces will be a basic tool for system
managers and administrators when using i915.
Signed-off-by: Andi Shyti
Cc: Matt Roper
Cc: Sujaritha Sundaresan
Cc: Tvrtko Ursulin
Reviewed-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/gt/intel_gt.c
the existing one to more tiles. In any
case this new set of interfaces will be a basic tool for system
managers and administrators when using i915.
Signed-off-by: Andi Shyti
Signed-off-by: Lucas De Marchi
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Matt Roper
Cc: Sujaritha Sundaresan
Cc: Tvr
is not really adding exposing new interfaces (new
ABI) other than adapting the existing one to more tiles. In any
case this new set of interfaces will be a basic tool for system
managers and administrators when using i915.
Signed-off-by: Andi Shyti
Signed-off-by: Lucas De Marchi
Cc: Chris Wilson
- throttle_reason_prochot
- throttle_reason_ratl
- throttle_reason_vr_thermalert
- throttle_reason_vr_tdc
Signed-off-by: Sujaritha Sundaresan
Cc: Dale B Stimson
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 74 +
drivers/gpu/drm/i915
Arghhh Sorry for spamming! I sent the wrong series!
Please ignore this.
Andi
On Sat, Mar 19, 2022 at 12:46:33AM +0200, Andi Shyti wrote:
> Hi,
>
> This is the second series that prepares i915 to host multitile
> platforms. It introduces the for_each_gt() macro that loops over
With the upcoming multitile support each tile will have its own
local memory. Mark the current LMEM with the suffix '0' to
emphasise that it belongs to the root tile.
Suggested-by: Michal Wajdeczko
Signed-off-by: Andi Shyti
Reviewed-by: Michal Wajdeczko
Reviewed-by: Andrzej Hajda
--
The "gt_is_root(struct intel_gt *gt)" helper return true if the
gt is the root gt, which means that its id is 0. Return false
otherwise.
Suggested-by: Michal Wajdeczko
Signed-off-by: Andi Shyti
Reviewed-by: Michal Wajdeczko
Reviewed-by: Andrzej Hajda
---
drivers/gpu/drm/i915/gt/
or patch 1 and 2.
- Reworded the commit of patch 2 to underline the fact that the
interface is useful also when used manually.
v1 -> v2
- fixed a couple of coding style issues in patch 2.
Andi Shyti (5):
drm/i915: Rename INTEL_REGION_LMEM with INTEL_REGION_LMEM_0
drm/i915/gt: add gt_i
ure is in place to handle them.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
Signed-off-by: Andi Shyti
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Matthew Auld
Reviewed-by: Matt Roper
Reviewed-by: Andrzej
interfaces will be a basic tool for system
managers and administrators when using i915.
Signed-off-by: Andi Shyti
Cc: Chris Wilson
Cc: Matt Roper
Cc: Sujaritha Sundaresan
Cc: Tvrtko Ursulin
Reviewed-by: Sujaritha Sundaresan
Reviewed-by: Andrzej Hajda
---
drivers/gpu/drm/i915/Makefile
the existing one to more tiles. In any
case this new set of interfaces will be a basic tool for system
managers and administrators when using i915.
Signed-off-by: Andi Shyti
Signed-off-by: Lucas De Marchi
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Matt Roper
Cc: Sujaritha Sundaresan
Cc: Tvr
is not really adding exposing new interfaces (new
ABI) other than adapting the existing one to more tiles. In any
case this new set of interfaces will be a basic tool for system
managers and administrators when using i915.
Signed-off-by: Andi Shyti
Signed-off-by: Lucas De Marchi
Cc: Chris Wilson
clipping.
- throttle_reason_vr_tdc: when set indicates that VR TDC
(Thermal Design Current) has caused GT frequency clipping.
Signed-off-by: Sujaritha Sundaresan
Signed-off-by: Andi Shyti
Cc: Dale B Stimson
Reviewed-by: Andrzej Hajda
---
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 74
Hi Michal,
[...]
> > +static int intel_gt_tile_setup(struct intel_gt *gt, phys_addr_t phys_addr)
> > +{
> > + int ret;
> > +
> > + if (!gt_is_root(gt)) {
> > + struct intel_uncore_mmio_debug *mmio_debug;
> > + struct intel_uncore *uncore;
> > +
> > + uncore = kza
Change functions that always return '0' to be void type.
Signed-off-by: Andi Shyti
Reviewed-by: Maciej Patelczyk
---
Hi,
just resending it once more time. Matt, can you please commit
this refactoring if you are OK with it?
Andi
drivers/gpu/drm/i915/gt/intel_gt_debugfs
Hi Tvrtko,
[...]
> > +static ssize_t act_freq_mhz_show(struct device *dev,
> > +struct device_attribute *attr, char *buff)
> > +{
> > + u32 actual_freq = sysfs_gt_attribute_r_max_func(dev, attr,
> > + __act_freq_mhz_show)
Hi Mauro,
[...]
> +static int ref_module_dependency(struct module *mod, struct module *this)
> +{
> + int ret;
> +
> + if (!this || !this->name)
> + return -EINVAL;
> +
> + if (mod == this)
> + return 0;
> +
> + mutex_lock(&module_mutex);
> +
> + ret =
/i915/gt: Create per-tile RPS sysfs interfaces")
> Signed-off-by: YueHaibing
Reviewed-by: Andi Shyti
Thanks,
Andi
> ---
> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_s
Hi Jani,
On Fri, May 06, 2022 at 02:53:50PM +0300, Jani Nikula wrote:
> On Sat, 19 Mar 2022, Andi Shyti wrote:
> > +#define INTEL_GT_RPS_SYSFS_ATTR(_name, _mode, _show, _store) \
> > + struct device_attribute dev_attr_gt_##_name = __ATTR(gt_##_name, _mode,
> > _show, _sto
Cleanup fb_info in .fb_destroy rather
> than .remove")
> Reported-by: Ville Syrjälä
> Reported-by: Andrzej Hajda
> Signed-off-by: Javier Martinez Canillas
Reviewed-by: Andi Shyti
Andi
e organization.
>
> v2: s/gtn/gt/ (Andi)
>
> Cc: Andi Shyti
> Cc: Andrzej Hajda
> Fixes: b770bcfae9ad ("drm/i915/gt: create per-tile sysfs interface")
> Signed-off-by: Ashutosh Dixit
I'm still not convinced this patch is 100% correct, but I think
it&
e organization.
>
> v2: s/gtn/gt/ (Andi)
>
> Cc: Andi Shyti
> Cc: Andrzej Hajda
> Fixes: b770bcfae9ad ("drm/i915/gt: create per-tile sysfs interface")
> Signed-off-by: Ashutosh Dixit
I tagget the wrong version (which is the same as this one):
Reviewed-by: Andi Shyti
Andi
n names to eliminate needless #defines (Rodrigo)
>
> Cc: Rodrigo Vivi
> Cc: Jani Nikula
> Cc: Andi Shyti
> Signed-off-by: Ashutosh Dixit
looks correct:
Reviewed-by: Andi Shyti
Thanks,
Andi
Hi Ashutosh,
> > +static ssize_t
> > +default_min_freq_mhz_show(struct kobject *kobj, struct kobj_attribute
> > *attr, char *buf)
> > +{
> > + struct intel_gt *gt = kobj_to_gt(kobj->parent);
> > +
> > + return sysfs_emit(buf, "%d\n", gt->rps_defaults.min_freq);
I guess this is %u.
> > +}
>
ani Nikula
Fixes: 56a709cf77468 ("drm/i915/gt: Create per-tile RPS sysfs interfaces")
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 21 +++--
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs
During object cleanup we invalidate the TLBs but we do it only
for gt0. Invalidate the caches for all the tiles.
Reported-by: Chris Wilson
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a
Hi,
The real fix is in patch 2. The rest is a helper that adds
the with_intel_gt_pm_if_awake() (from Chris) and one more check
on the status of the engine before accessing it for clearing the
TLB.
Andi
Andi Shyti (2):
drm/i915/gem: Flush TLBs for all the tiles when clearing an obj
drm/i915
-off-by: Chris Wilson
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt_pm.h | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
index bc898df7a48cc..2654133b39f22 100644
--- a/drivers/gpu/drm/i915/gt
During object cleanup we invalidate the TLBs but we do it only
for gt0. Invalidate the caches for all the tiles.
Reported-by: Chris Wilson
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 12 +---
drivers/gpu/drm/i915/gt/intel_gt_pm.h | 2 +-
2 files
We want to check if the engine is awake first before invalidating
its cache.
Suggested-by: Chris Wilson
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt
-off-by: Chris Wilson
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt_pm.h | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
index bc898df7a48cc..3b1fbce7ea369 100644
--- a/drivers/gpu/drm/i915/gt
During object cleanup we invalidate the TLBs but we do it only
for gt0. Invalidate the caches for all the tiles.
Reported-by: Chris Wilson
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a
We want to check if the engine is awake first before invalidating
its cache.
Suggested-by: Chris Wilson
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt
t; v2 (v1: https://patchwork.freedesktop.org/series/103831/)
- Add with_intel_gt_pm_if_awake() macro for gt specific wakeref.
- Check if an engine is awake before invalidating its TLB.
Andi Shyti (2):
drm/i915/gem: Flush TLBs for all the tiles when clearing an obj
drm/i915/gt: Skip TLB invali
Hi Thomas,
On Thu, May 12, 2022 at 11:40:45AM +0200, Thomas Hellström wrote:
> In vma destruction, the following race may occur:
>
> Thread 1: Thread 2:
> i915_vma_destroy();
>
> ...
> list_del_init(vma->vm_link);
> ...
> mutex_unlock(vma->vm->mutex);
>
Hi Daniele,
> > > @@ -909,6 +903,8 @@ int i915_driver_probe(struct pci_dev *pdev,
> > > const struct pci_device_id *ent)
> > > i915_ggtt_driver_late_release(i915);
> > > out_cleanup_mmio:
> > > i915_driver_mmio_release(i915);
> > > +out_tiles_cleanup:
> > > + intel_gt_release_all(
2]
3. please add a changelog, as this is a single patch, do it
after the '---'
No need to resend, just keep the three notes in mind for your
next patches. Anyway, thanks for the fix and as I am at it:
Reviewed-by: Andi Shyti
Thanks,
Andi
> ---
> drivers/gpu/drm/i915/selftests/i915
tch, this would be [PATCH v2]
> 3. please add a changelog, as this is a single patch, do it
> after the '---'
>
> No need to resend, just keep the three notes in mind for your
> next patches. Anyway, thanks for the fix and as I am at it:
>
> Reviewed-by: Andi Shyti
Pushed in drm-intel-next.
Thanks,
Andi
ing store")
> Signed-off-by: Chris Wilson
> Cc: Fei Yang
> Cc: Andi Shyti
> Cc: Thomas Hellström
> Signed-off-by: Mauro Carvalho Chehab
For me it's good, but please, sort out with Tvrtko about his
doubts:
Reviewed-by: Andi Shyti
Andi
> ---
>
> To avoid mai
er.kernel.org
> Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
> Signed-off-by: Chris Wilson
> Cc: Fei Yang
> Cc: Andi Shyti
> Acked-by: Thomas Hellström
> Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Andi Shyti
Thanks,
Andi
ore")
> Signed-off-by: Chris Wilson
> Cc: Fei Yang
> Cc: Andi Shyti
> Acked-by: Thomas Hellström
> Signed-off-by: Mauro Carvalho Chehab
Please, once you have sorted out Tvrtko's question you can add:
Reviewed-by: Andi Shyti
Thanks,
Andi
r has access to the TLB's in each engine.
>
> That helps to reduce the performance regression introduced by TLB
> invalidate logic.
>
> Cc: sta...@vger.kernel.org
> Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
> Signed-off-by: Chri
gt; Signed-off-by: Mauro Carvalho Chehab
Just a copy paste, I checked line by line and it looked all
correct:
Reviewed-by: Andi Shyti
Thanks,
Andi
Hi,
On Mon, Jul 25, 2022 at 12:25:22PM +0300, Gwan-gyeong Mun wrote:
> It moves overflows_type utility macro into drm util header from i915_utils
> header. The overflows_type can be used to catch the truncation between data
> types. And it adds safe_conversion() macro which performs a type convers
Hi Mauro,
> Add a kernel-doc markup to document this new macro.
>
> Reviewed-by: Tvrtko Ursulin
> Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Andi Shyti
Andi
d a vma resource
> * @vma_res: The vma resource to unbind.
> + * @tlb: pointer to vma->obj->mm.tlb associated with the resource
> + *to be stored at vma_res->tlb. When not-NULL, it will be used
> + * to do TLB cache invalidation before freeing a VMA resource.
> + *used only for async unbind.
/used/Used/
With that:
Reviewed-by: Andi Shyti
Thanks,
Andi
Hi Mauro,
I think there are still some unanswered questions from Tvrtko on
this patch, am I right?
Andi
On Wed, Jul 27, 2022 at 02:29:55PM +0200, Mauro Carvalho Chehab wrote:
> From: Chris Wilson
>
> Invalidate TLB in batches, in order to reduce performance regressions.
>
> Currently, every c
dd support for LMEM PCIe resizable bar")
> Reported-by: Linux Kernel Functional Testing
> Tested-by: Linux Kernel Functional Testing
> Acked-by: Matthew Auld
> Signed-off-by: Nirmoy Das
Reviewed-by: Andi Shyti
Andi
PS You forgot to CC the author of the patch you are fixing
ed-off-by: Chris Wilson
> Co-developed-by: Nirmoy Das
> Signed-off-by: Nirmoy Das
Reviewed-by: Andi Shyti
Andi
Hi Mauro,
Pushed in drm-intel-gt-next.
Thanks,
Andi
On Wed, Jul 27, 2022 at 02:29:50PM +0200, Mauro Carvalho Chehab wrote:
> Doing TLB invalidation cause performance regressions, like:
> [424.370996] i915 :00:02.0: [drm] *ERROR* rcs0 TLB invalidation did
> not complete in 4ms!
>
> As
gt; Signed-off-by: Mauro Carvalho Chehab
I already reviewed this patch... anyway I checked it again and
it's all correct.
Reviewed-by: Andi Shyti
Thanks,
Andi
Hi Jani,
> >> It moves overflows_type utility macro into drm util header from i915_utils
> >> header. The overflows_type can be used to catch the truncation between data
> >> types. And it adds safe_conversion() macro which performs a type conversion
> >> (cast) of an source value into a new varia
Hi Randy,
> > +/**
> > + * intel_gt_invalidate_tlb_full - do full TLB cache invalidation
> > + * @gt: GT structure
>
> In multiple places (here and below) it would be nice to know what a
> GT structure is. I looked thru multiple C and header files yesterday
> and didn't find any comments about it
Hi Mauro,
On Thu, Aug 04, 2022 at 09:37:22AM +0200, Mauro Carvalho Chehab wrote:
> WRITE_ONCE() should happen at the original var, not on a local
> copy of it.
>
> Fixes: 5d36acb7198b ("drm/i915/gt: Batch TLB invalidations")
> Signed-off-by: Mauro Carvalho Chehab
Revi
Hi Mauro,
On Thu, Aug 04, 2022 at 09:37:24AM +0200, Mauro Carvalho Chehab wrote:
> Add a description for the TLB cache invalidation algorithm and for
> the related kAPI functions.
>
> Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Andi Shyti
Andi
Hi Rodrigo,
On Mon, Aug 08, 2022 at 03:04:13PM -0400, Rodrigo Vivi wrote:
> On Mon, Aug 08, 2022 at 06:37:58PM +0200, Andi Shyti wrote:
> > Hi Mauro,
> >
> > On Thu, Aug 04, 2022 at 09:37:22AM +0200, Mauro Carvalho Chehab wrote:
> > > WRITE_ONCE() should happen
> Cc: Thomas Hellström
> Cc: Matthew Auld
> Cc: Nirmoy Das
> Cc: Jani Nikula
> Cc: Andi Shyti
> Reviewed-by: Mauro Carvalho Chehab (v5)
> ---
> drivers/gpu/drm/i915/i915_utils.h | 5 +--
> include/linux/overflow.h | 54 +++
> 2
ou could use in this case the ".is_visible()" function as you are
not inheriting it from the upper drm class.
Anyway,
Reviewed-by: Andi Shyti
Thanks,
Andi
or XEHPSDV and DG2/ATS-M.
>
> Cc: Rodrigo Vivi
> Signed-off-by: Ashutosh Dixit
> Reviewed-by: Rodrigo Vivi
Reviewed-by: Andi Shyti
Thanks,
Andi
base_ms);
> +
> +#define snb_pcode_read(i915, mbox, val, val1) \
> + intel_gt_pcode_read(&(i915)->gt0, mbox, val, val1)
> +
> +#define snb_pcode_write_timeout(i915, mbox, val, fast_timeout_us,
> slow_timeout_ms) \
> + intel_gt_pcode_write_timeout(&(i915)->
acy pcode interface.
>
> Cc: Andi Shyti
> Cc: Jani Nikula
> Cc: Rodrigo Vivi
> Signed-off-by: Ashutosh Dixit
Reviewed-by: Andi Shyti
Thanks,
Andi
Hi Ashutosh,
On Tue, Apr 19, 2022 at 11:25:05PM -0700, Ashutosh Dixit wrote:
> From: Dale B Stimson
>
> Add a couple of helpers to help formatting pcode commands and improve code
> readability.
Can you please add some more details on the helpers?
> v2: Fixed commit author (Rodrigo)
>
> Cc: Mi
> + if (err)
> + return err;
> +
> + /* data_out - Fused P0 for domain ID in units of 50 MHz */
this comment doesn't say much, can we make it a bit clearer? The
same for the one below.
The rest looks good:
Reviewed-by: Andi Shyti
> + val *= GT_FREQUE
Hi Ashutosh,
[...]
> -static struct kobj_type kobj_gt_type = {
> - .release = kobj_gt_release,
> +static struct kobj_type kobj_gtn_type = {
what does it mean GTN? Or is it GTn? Please use just GT, gtn is
confusing.
Same for all the rest of the gtn's you have used below.
Thanks,
Andi
Hi Andrzej and Ashutosh,
> > > > b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> > > > index 937b2e1a305e..4c72b4f983a6 100644
> > > > --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> > > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> > > > @@ -222,6 +222,9 @@ struct intel_gt {
> > > > }
Hi Matt,
On Fri, Apr 22, 2022 at 12:50:06PM -0700, Matt Roper wrote:
> We're now ready to start exposing compute engines to userspace.
>
> While we're at it, let's extend the kerneldoc description for the other
> engine types as well.
I would make two different patches. The kerneldoc description
On Fri, Apr 22, 2022 at 12:50:07PM -0700, Matt Roper wrote:
> From: Daniele Ceraolo Spurio
>
> Cc: Vinay Belgaumkar
> Signed-off-by: Daniele Ceraolo Spurio
> Signed-off-by: Matt Roper
> Reviewed-by: Matt Roper
Reviewed-by: Andi Shyti
Andi
Hi Ashutosh,
> > > -static struct kobj_type kobj_gt_type = {
> > > - .release = kobj_gt_release,
> > > +static struct kobj_type kobj_gtn_type = {
> >
> > what does it mean GTN? Or is it GTn? Please use just GT, gtn is
> > confusing.
> >
> > Same for all the rest of the gtn's you have used below.
>
[...]
> + if (!dmc_mmio_addr_sanity_check(dmc, mmioaddr, mmio_count,
> dmc_header->header_ver, dmc_id))
> + drm_err(&i915->drm, "DMC firmware has Wrong MMIO Addresses\n");
> + return 0;
> +
mh? :)
Hi Matt,
On Wed, Apr 27, 2022 at 09:19:23PM -0700, Matt Roper wrote:
> We'll be adding a new type of engine soon. Let's document the existing
> engine classes first to help make it clear what each type of engine is
> used for.
>
> Cc: Andi Shyti
> Signed-off-by: Ma
in
> Cc: Vinay Belgaumkar
> Cc: Jordan Justen
> Cc: Szymon Morek
> UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14395
> Signed-off-by: Matt Roper
looks good,
Reviewed-by: Andi Shyti
Thanks,
Andi
Hi Tvrtko,
> > [...]
> >
> > > static int
> > > intel_gt_tile_setup(struct intel_gt *gt, unsigned int id, phys_addr_t
> > > phys_addr)
> >
> > we don't actually need 'id', it's gt->info.id. It's introduced in
> > patch 3 with the value '0' but it's not needed.
>
> I have a suspicion code g
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