On Wed, 2020-12-30 at 16:02 -0800, Matt Roper wrote:
> On Wed, Dec 30, 2020 at 10:37:42AM +, Chris Wilson wrote:
> > The timeouts are frequent and expected. We will complain if we
> > retry so
> > often as to lose patience and give up, so the cacophony from
> > individual
> > complaints is redu
On Tue, 2021-01-12 at 22:35 +0200, Imre Deak wrote:
> On Tue, Jan 12, 2021 at 08:10:40PM +0200, Ville Syrjälä wrote:
> > On Tue, Dec 29, 2020 at 07:22:01PM +0200, Imre Deak wrote:
> > > The DP PHY vswing/pre-emphasis level programming the driver does
> > > is
> > > related to the DPTX -> first LTTP
On Sat, 2021-05-29 at 13:17 +0800, William Tseng wrote:
> In some cases, the MAX_LANE_COUNT in the register at DCPD Address
> 0002h
> may be updated by LTTPR in non-transparent mode while reading DPRX
> Caps
> registers, e.g., the lane count is changed from 2 to 4. This may
> cause
> Link Training
On Tue, 2021-10-19 at 15:01 +0300, Ville Syrjälä wrote:
> On Tue, Oct 19, 2021 at 02:52:15PM +0300, Jani Nikula wrote:
> > On Mon, 19 Jul 2021, Khaled Almahallawy <
> > khaled.almahall...@intel.com> wrote:
> > > Bits 20:19 are used to set CP2520 Patterns 1/2/3 (refer to
> > > Specs:50484).
> > > TP
On Thu, 2021-10-21 at 13:00 +0300, Jani Nikula wrote:
> On Wed, 20 Oct 2021, Khaled Almahallawy > wrote:
> > This series updates DPCD 248h register name and PHY test patterns
> > names to follow DP 2.0 Specs.
> > Also updates the DP PHY CTS codes of the affected drivers (i915,
> > amd, msm)
> > No
Thank you for the patch. HDMI, DP HBR and HBR2_HBR3 tables match the
spces.
Acked-by: Khaled Almahallawy
On Thu, 2021-07-22 at 22:38 -0700, Matt Roper wrote:
> ADL-P now has its own set of DDI buf translation tables (except for
> eDP
> which appears to be the same as TGL). Add the new values (l
Tested on latest drm-tip with DPCD=1.2 Sink and LTTPR set to non-
transparent mode:
[ 706.966375] i915 :00:02.0: [drm:drm_dp_dpcd_read] AUX USBC2/DDI
TC2/PHY TC2: 0xf AUX -> (ret= 8) 14 1e 80 55 04 00 00 00
[ 706.966383] i915 :00:02.0:
[drm:intel_dp_init_lttpr_and_dprx_caps [i915]]
Hi Imre,
I applied this patch to today drm-tip and it applied cleanely.
Could you please help with mergin it?
Thanks
Khaled
On Fri, 2021-02-26 at 00:15 -0800, Almahallawy, Khaled wrote:
> Source needs to write DPCD 103-106 after receiving a PHY request to
> change
> swing/pre-empha
I believe Imre’s LT fallback:
https://github.com/ideak/linux/commits/linktraining-fallback-fix and
Chrome user space fix:
https://chromium-review.googlesource.com/c/chromium/src/+/3003487
should address Chrome concerns for LT failure and LTTPRs
Thanks
Khaled
On Tue, 2021-07-06 at 23:25 +0800, L
On Wed, 2019-05-22 at 12:25 -0700, Manasi Navare wrote:
> On Tue, May 21, 2019 at 04:24:58PM +0300, Ville Syrjälä wrote:
> > On Mon, May 20, 2019 at 04:25:41PM -0700, Khaled Almahallawy wrote:
> > > According to DP 1.4 standard, if the source supports four pre-
> > > emphasis levels, then the sourc
On Fri, 2022-04-08 at 20:21 +0300, Imre Deak wrote:
> Factor out from drm_dp_dpcd_read() a function to probe a DPCD address
> with a 1-byte read access. This will be needed by the next patch
> doing a
> read from an LTTPR address, which must happen without the preceding
> wake-up read in drm_dp_dpc
Thank You Animesh. Tested using scope with small set of tests and
automation run to completion. Started full DP PHY compliance (~160
tests) overnight.
On Tue, 2020-03-10 at 21:07 +0530, Animesh Manna wrote:
> This patch process phy compliance request by programming requested
> vswing, pre-emphasi
On Mon, 2021-01-18 at 20:31 +0200, Imre Deak wrote:
> Atm, the driver programs explicitly the default transparent link
> training mode (0x55) to DP_PHY_REPEATER_MODE even if no LTTPRs are
> detected.
>
> This conforms to the spec (3.6.6.1):
> "DP upstream devices that do not enable the Non-transpa
On Wed, 2021-01-13 at 17:04 +0200, Imre Deak wrote:
> On Fri, Aug 21, 2020 at 11:48:37PM -0700, Khaled Almahallawy wrote:
> > Source needs to write DPCD 103-106 after receiving a PHY request to
> > change
> > swing/pre-emphasis after reading DPCD 206-207. This is especially
> > needed if
> > there
On Wed, 2021-01-27 at 20:19 +0200, Imre Deak wrote:
> At least on some TGL platforms PUNIT wants to access some display HW
> registers, but it doesn't handle display power managment (disabling
> DC
> states as required) and so this register access will lead to a hang.
> To
> prevent this disable ru
On Thu, 2021-01-21 at 15:15 +0200, Imre Deak wrote:
> On Tue, Jan 19, 2021 at 08:47:25AM +0200, Almahallawy, Khaled wrote:
> > On Mon, 2021-01-18 at 20:31 +0200, Imre Deak wrote:
> > > Atm, the driver programs explicitly the default transparent link
> > &
On Wed, 2021-02-10 at 09:55 +0100, Thomas Zimmermann wrote:
> Hi
>
> Am 10.02.21 um 09:33 schrieb Khaled Almahallawy:
> > The number of AUX retries specified in the DP specs is 7.
> > Currently, to make Dell 4k monitors happier, the number of retries
> > are 32.
> > i915 also retries 5 times (inte
On Wed, 2021-02-10 at 13:03 -0500, Lyude Paul wrote:
> On Wed, 2021-02-10 at 00:33 -0800, Khaled Almahallawy wrote:
> > The number of AUX retries specified in the DP specs is 7.
> > Currently, to make
> > Dell 4k monitors happier, the number of retries are 32.
> > i915 also retries 5 times (intel_d
ch
> is a big
> reason we have these helpers), but I think we might be able to fix
> some of the
> issues you've mentioned by coming up with better workarounds. More
> details below
>
> On Thu, 2021-02-11 at 06:56 +, Almahallawy, Khaled wrote:
> > On Wed, 2021-02-1
On Thu, 2021-03-18 at 20:06 +0200, Imre Deak wrote:
> On Thu, Mar 18, 2021 at 07:49:13PM +0200, Imre Deak wrote:
> > On Thu, Mar 18, 2021 at 07:33:20PM +0200, Ville Syrjälä wrote:
> > > On Wed, Mar 17, 2021 at 08:48:59PM +0200, Imre Deak wrote:
> > > > The spec requires to use at least 3.2ms for th
On Sat, 2021-03-20 at 09:15 +0200, Imre Deak wrote:
> On Fri, Mar 19, 2021 at 11:07:21PM +0200, Imre Deak wrote:
> > On Fri, Mar 19, 2021 at 04:44:26PM -0400, Lyude Paul wrote:
> > > > > > [...]
> > > > > > I think it would work if we can make the retries
> > > > > > configurable and set it
> > > >
On Wed, 2020-10-21 at 00:29 +, Souza, Jose wrote:
> On Tue, 2020-10-20 at 16:25 -0700, José Roberto de Souza wrote:
> > On Tue, 2020-10-20 at 15:41 +0300, Ville Syrjälä wrote:
> > > On Tue, Oct 20, 2020 at 12:45:55AM -0700, Khaled Almahallawy
> > > wrote:
> > > > This patch avoids failing atomi
On Fri, 2020-05-29 at 16:27 -0700, José Roberto de Souza wrote:
> Small updates in dkl_de_emphasis_control field.
>
> BSpec: 49292
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git
On Thu, 2020-06-04 at 22:06 +0300, Ville Syrjälä wrote:
> On Thu, Jun 04, 2020 at 10:33:48AM +0530, Vidya Srinivas wrote:
> > Signed-off-by: Khaled Almahallawy
> > Signed-off-by: Vidya Srinivas
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 40
> > ++---
> > 1
On Tue, 2020-06-02 at 13:54 -0700, José Roberto de Souza wrote:
> As latest update we have now 2 voltage swing tables for DP over DKL
> PHY with only one difference in Level 0 pre-emphasis 3.
> So with 2 tables for DP is time to have one single function to return
> all DKL voltage swing tables.
>
On Mon, 2020-06-29 at 21:58 +0300, Imre Deak wrote:
> When the reference clock is 38.4MHz, using the current TBT PLL
> fractional divider value results in a slightly off TBT link
> frequency.
> This causes an endless loop of link training success followed by a
> bad
> link signaling and retraining
On Mon, 2020-07-20 at 10:09 -0700, José Roberto de Souza wrote:
> This new HBR2 table for TGL-U and TGL-Y is required to pass
> DisplayPort compliance.
>
> BSpec: 49291
> Cc: Khaled Almahallawy
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 19
On Mon, 2020-07-20 at 17:11 -0700, Manasi Navare wrote:
> On Mon, Jul 20, 2020 at 04:41:26PM -0700, Khaled Almahallawy wrote:
> > Adding support for TPS4 (CP2520 Pattern 3) PHY pattern source
> > tests.
> >
> > Signed-off-by: Khaled Almahallawy
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c
On Mon, 2020-07-20 at 17:07 -0700, Manasi Navare wrote:
> On Mon, Jul 20, 2020 at 04:41:25PM -0700, Khaled Almahallawy wrote:
> > Add the missing CP2520 pattern 2 and 3 phy compliance patterns
> >
> > Signed-off-by: Khaled Almahallawy
> > ---
> > drivers/gpu/drm/drm_dp_helper.c | 2 +-
> > inclu
On Tue, 2020-08-18 at 14:29 -0700, Navare, Manasi wrote:
> On Wed, Jul 22, 2020 at 05:36:27PM -0700, Khaled Almahallawy wrote:
> > Adding support for TPS4 (CP2520 Pattern 3) PHY pattern source
> > tests.
> >
> > v2: uniform bit names TP4a/b/c (Manasi)
> >
> > Signed-off-by: Khaled Almahallawy
>
Thank You for the patch. This does the trick. No full modest because of
Mbus joining
Tested-by: Khaled Almahallawy
On Thu, 2023-08-10 at 11:17 +0300, Stanislav Lisovskiy wrote:
> Currently we can't change MBUS join status without doing a modeset,
> because we are lacking mechanism to synchronize
Hi Imre and Jani,
Could you please review this series in order to add DP2.1 reg defn.
Thank You
Khaled
On Thu, 2023-06-08 at 22:49 -0700, Almahallawy, Khaled wrote:
> Starting from DP2.0 specs, DPCD 248h is renamed
> LINK_QUAL_PATTERN_SELECT and it has the same values of registers
>
On Fri, 2023-06-09 at 11:35 +0300, Jani Nikula wrote:
> On Fri, 09 Jun 2023, Animesh Manna wrote:
> > For DP alt mode display driver get the information
> > about cable speed and cable type through TCSS_DDI_STATUS
> > register which will be updated by type-c platform driver.
> > Accodingly Update
Thank You for the fix
Tested-by: Khaled Almahallawy
On Thu, 2023-06-15 at 21:39 -0700, Radhakrishna Sripada wrote:
> Driver does not clear the default SSC for MPLLA. This causes link
> training
> failure when trying to use 10G and 20G rates. Fix the behaviour and
> enable ssc
> only when we real
On Fri, 2023-12-01 at 02:53 +, Patchwork wrote:
> Patch Details
> Series: series starting with [v2,1/2] drm/i915/dp: Use
> LINK_QUAL_PATTERN_* Phy test pattern names
> URL: https://patchwork.freedesktop.org/series/127146/
> State:failure
> Details:
> https://intel-gfx-ci.01
On Fri, 2023-12-01 at 03:34 +, Patchwork wrote:
> Patch Details
> Series: drm/display/dp: Add the remaining Square PHY patterns
> DPCD register definitions (rev2)
> URL: https://patchwork.freedesktop.org/series/123149/
> State:failure
> Details:
> https://intel-gfx-ci.01.or
Thank You for the patch. We noticed a break in the customer board with
the latest GOP + this patch.
Thank You
Khaled
On Wed, 2023-12-06 at 18:46 +, Paz Zcharya wrote:
> There was an assumption that for iGPU there should be a 1:1 mapping
> of GGTT to physical address pointing to the framebu
On Thu, 2023-12-07 at 03:14 +, Patchwork wrote:
> Patch Details
> Series: series starting with [v3,1/3] drm/i915/dp: Use
> LINK_QUAL_PATTERN_* Phy test pattern names
> URL: https://patchwork.freedesktop.org/series/127465/
> State:failure
> Details:
> https://intel-gfx-ci.01
Thank you for the patch
Tested-by: Khaled Almahallawy
-Original Message-
From: Intel-gfx On Behalf Of Arun R
Murthy
Sent: Wednesday, January 3, 2024 1:07 AM
To: intel-gfx@lists.freedesktop.org; Nikula, Jani ;
Deak, Imre
Subject: [PATCH] drm/i915/display/dp: 128/132b DP-capable with S
On Mon, 2022-09-26 at 19:48 +0300, Jani Nikula wrote:
> On Fri, 16 Sep 2022, Khaled Almahallawy > wrote:
> > Bspecs has updated recently to remove the restriction to disable
> > DDI/Transcoder before setting PHY test pattern. This update is to
> > address PHY compliance test failures observed on a
On Tue, 2024-02-06 at 16:17 +0530, Arun R Murthy wrote:
> Fallback mandates on DP link training failure. This patch just covers
> the DP2.0 fallback sequence.
>
> TODO: Need to implement the DP1.4 fallback.
>
> Signed-off-by: Arun R Murthy
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 92 ++
On Tue, 2024-02-06 at 15:06 +, Murthy, Arun R wrote:
> > -Original Message-
> > From: Nikula, Jani
> > Sent: Tuesday, February 6, 2024 5:10 PM
> > To: Murthy, Arun R ;
> > intel-gfx@lists.freedesktop.org
> > Cc: Deak, Imre ; Syrjala, Ville <
> > ville.syrj...@intel.com>;
> > Shankar,
Thank You for the patch.
Do you think we need to revert:
9c058492b16f ("drm/i915/mst: Reject modes that require the bigjoiner")
On Wed, 2024-02-21 at 00:09 +0200, Stanislav Lisovskiy wrote:
> Patch calculates bigjoiner pipes in mst compute.
> Patch also passes bigjoiner bool to validate plane
>
Thank You for the fixes
Tested-by: Khaled Almahallawy
On Wed, 2024-03-20 at 22:11 +0200, Imre Deak wrote:
> This patchset fixes a few MTL/DSC 1.2 related issues and adds a
> workaround for the native 5k@60Hz uncompressed mode on a
> MediaTek/Dell
> UHBR monitor, force-enabling DSC on it as requi
Thank You for the fix.
Tested-by: Khaled Almahallawy
Reviewed-by: Khaled Almahallawy
On Thu, 2025-02-06 at 01:28 +0200, Imre Deak wrote:
> The MST intel_connector::encoder pointer is NULL if the connector
> hasn't
> been enabled before, so it can't be used to retrieve the display
> pointer. Us
Thank You for the series.
Tested a modeline that is not pre-computed and able to see pixel clock
calculation done correctly and the analyzer turns on:
adjusted mode: "3440x1440": 50 265250 3440 3488 3520 3600 1440 1443
1453 1474 0x48 0x9
crtc timings: clock=265250, hd=3440 hb=3440-3600 hs=3488-35
Thank You for the patch
Without this patch on monitors that support this mode like Acer x34 and
LG 34GS95QE. this resolution is rejected as follow:
[drm:drm_mode_prune_invalid] Rejected mode: "3440x1440": 50 265250 3440
3488 3520 3600 1440 1443 1453 1474 0x48 0x9 (CLOCK_RANGE)
With this patch, w
On Wed, 2025-02-12 at 17:19 +0530, Mohammed Thasleem wrote:
> Starting from MTL we don't have a platform agnostic way to validate
> DC6 state due to dc6 counter has been removed to validate DC state.
>
> The goal is to validate that the display HW can reach the DC6 power
> state. There is no HW DC
48 matches
Mail list logo
