Forward declare struct drm_printer instead of including drm/drm_print.h,
as we only need the pointer. Turns out quite a few places depend on this
include implicitly. Make them explicit.
Some of the includes are just stale and unnecessary. Group the forward
declarations together while at it.
Signe
On Thu, 27 Feb 2025, Jani Nikula wrote:
> Update GVT-g MAINTAINERS entry to reflect the current status of
> maintenance and repositories.
>
> Cc: Dave Airlie
> Cc: Joonas Lahtinen
> Cc: Rodrigo Vivi
> Cc: Simona Vetter
> Cc: Tvrtko Ursulin
> Cc: Zhenyu Wang
> Cc: Zhi Wang
Zhenyu, Zhi, ping
== Series Details ==
Series: drm/i915: reduce intel_wakeref.h dependencies
URL : https://patchwork.freedesktop.org/series/146799/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16321 -> Patchwork_146799v1
Summary
---
On Wed, Mar 26, 2025 at 09:35:38AM +0530, Ankit Nautiyal wrote:
> For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
> bits are not required. Since the support for these bits is going to
> be deprecated in upcoming platforms, avoid writing these bits for the
> platforms that do n
Due to changes in allocator, the size of the allocation for
contiguous region is not rounded up to a power-of-two and
instead allocated as is. Thus, change the part of test that
expected the allocation to fail.
Signed-off-by: Mikolaj Wasiak
---
v1 -> v2:
- Added negative test for too large alloca
Enable runtime PM in mtd driver to notify graphics driver that
whole card should be kept awake while nvm operations are
performed through this driver.
CC: Lucas De Marchi
Acked-by: Karthik Poosa
Acked-by: Miquel Raynal
Signed-off-by: Alexander Usyskin
---
drivers/mtd/devices/mtd_intel_dg.c |
From: "Abliyev, Reuven"
Erase command is slow on discrete graphics storage
and may overshot PCI completion timeout.
BMG introduces the ability to have non-posted erase.
Add driver support for non-posted erase with polling
for erase completion.
Signed-off-by: Abliyev, Reuven
Signed-off-by: Alexa
== Series Details ==
Series: mtd: add driver for Intel discrete graphics (rev7)
URL : https://patchwork.freedesktop.org/series/140306/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
Add driver for access to Intel discrete graphics card
internal NVM device.
Expose device on auxiliary bus by i915 and Xe drivers and
provide mtd driver to register this device with MTD framework.
This is a rewrite of "drm/i915/spi: spi access for discrete graphics"
and "spi: add driver for Intel d
Register the on-die nvm device with the mtd subsystem.
Refcount nvm object on _get and _put mtd callbacks.
For erase operation address and size should be 4K aligned.
For write operation address and size has to be 4bytes aligned.
CC: Rodrigo Vivi
CC: Lucas De Marchi
Acked-by: Miquel Raynal
Co-de
Implement read(), erase() and write() functions.
CC: Lucas De Marchi
CC: Rodrigo Vivi
Acked-by: Miquel Raynal
Co-developed-by: Tomas Winkler
Signed-off-by: Tomas Winkler
Co-developed-by: Vitaly Lubart
Signed-off-by: Vitaly Lubart
Signed-off-by: Alexander Usyskin
---
drivers/mtd/devices/mt
Add auxiliary driver for intel discrete graphics
non-volatile memory device.
CC: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
Acked-by: Miquel Raynal
Co-developed-by: Tomas Winkler
Signed-off-by: Tomas Winkler
Signed-off-by: Alexander Usyskin
---
MAINTAINERS| 7 ++
dr
Check NVM access mode from GSC FW status registers
and overwrite access status read from SPI descriptor, if needed.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Alexander Usyskin
---
drivers/gpu/drm/xe/regs/xe_gsc_regs.h | 4 +++
drivers/gpu/drm/xe/xe_heci_gsc.c | 5 +---
drivers/gpu/drm/xe/
Now that we have switched to VRR Timing generator from PTL onwards, we
no longer need to program VTOTAL.Vtotal bits, which were used by Legacy
Timing Generator.
This patch series is a continuation from discussion of another patch for
avoid reading/writing VTOTAL.Vtotal bits [1].
First patch introdu
To avoid having VRR read/write for DSI transcoders, we currently use
!transcoder_is_dsi() in many places.
Instead introduce a new helper to check transcoder_has_vrr() and use
that to exclude transcoders which do not support VRR.
v2: Include HAS_VRR into the helper. (Ville)
Signed-off-by: Ankit Na
For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
bits are not required. Since the support for these bits is going to
be deprecated in upcoming platforms, avoid writing these bits for the
platforms that do not use legacy Timing Generator.
Since for these platforms TRAN_VMIN is
Check NVM access mode from GSC FW status registers
and overwrite access status read from SPI descriptor, if needed.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Alexander Usyskin
---
drivers/gpu/drm/i915/intel_nvm.c | 25 -
1 file changed, 24 insertions(+), 1 deletion(-)
di
== Series Details ==
Series: mtd: add driver for Intel discrete graphics (rev7)
URL : https://patchwork.freedesktop.org/series/140306/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16321 -> Patchwork_140306v7
Summary
--
== Series Details ==
Series: drm/i915: sagv/bw cleanup (rev4)
URL : https://patchwork.freedesktop.org/series/146014/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16321 -> Patchwork_146014v4
Summary
---
**FAILURE**
Hello,
Now that the freedesktop server migration is almost done, it's time to
turn our attention on the 2025 X.Org Foundation elections, which are
rapidly approaching! We will be forwarding the election schedule and
nominating process to the membership shortly.
Please note that only current membe
From: Ville Syrjälä
Extract the struct intel_dbuf_bw comparison into a small
helper. We'll get more users later.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bw.c | 23 +--
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm
From: Ville Syrjälä
Rename the intel_crtc_bw struct to intel_dbuf_bw to better
reflect what it does.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bw.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/disp
From: Ville Syrjälä
Continue improving the code around sagv/bw vs.
watermarks. A lot of the details get better encapsulated
within intel_bw.c and the complicated interactions between
different parts of the code are somewhat reduced.
v2: Rebase due to intel_display conversions
Ville Syrjälä (14)
From: Ville Syrjälä
Make skl_*_calc_dbuf_bw() a bit lower level passing in the
to be mutated dbuf_bw struct in explicitly. This will allow
more reuse later.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bw.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions
From: Ville Syrjälä
Update a bunch of bw related stuff during readout:
- bw_state->dbuf_bw possible now that the wm readout
has given us access to the plane ddb data
- cdclk_state->bw_min_cdclk
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bw.c| 3 +++
drivers/gpu/d
From: Ville Syrjälä
intel_compute_sagv_mask() has become pointless. Just inline
its contents into the existing loop in skl_compute_wm().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_watermark.c | 64
1 file changed, 24 insertions(+), 40 deletions(-)
d
On Wed, Mar 26, 2025 at 09:35:37AM +0530, Ankit Nautiyal wrote:
> To avoid having VRR read/write for DSI transcoders, we currently use
> !transcoder_is_dsi() in many places.
> Instead introduce a new helper to check transcoder_has_vrr() and use
> that to exclude transcoders which do not support VRR
> > Add driver for access to Intel discrete graphics card
> > internal NVM device.
> > Expose device on auxiliary bus by i915 and Xe drivers and
> > provide mtd driver to register this device with MTD framework.
> >
> > This is a rewrite of "drm/i915/spi: spi access for discrete graphics"
> > and "
From: Ville Syrjälä
intel_bw_crtc_min_cdclk() only depends on the pipe data rate,
which we already have stashed in bw_state->data_rate[]. So
stashing the resulting min_cdclk[] as well is redundant. Get
rid of it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bw.c | 17 +++
From: Ville Syrjälä
The only thing between the current intel_bw_check_sagv_mask() call
site and intel_bw_atomic_check() is skl_wm_add_affected_planes()
which no longer depends on the sagv mask, so we can make life
a lot less confusing by calling intel_bw_check_sagv_mask() from
intel_bw_atomic_che
From: Ville Syrjälä
Remove the force_check_qgv flag and just fill the pipe_sagv_reject
bitmask properly during readout. This will cause the initial commit
to re-enable SAGV if possible.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bw.c | 12 ++--
drivers/gpu/drm/
From: Ville Syrjälä
Currently intel_bw_calc_min_cdclk() always adds the bw_state
to the atomic state. Not only does it result in potentially
redundant work later, it's also currently causing unwanted cdclk
changes during driver load.
Check if the dbuf bw is actually changing before we decide to
Enable access to internal non-volatile memory on DGFX
with GSC/CSC devices via a child device.
The nvm child device is exposed via auxiliary bus.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Alexander Usyskin
---
drivers/gpu/drm/xe/Makefile | 1 +
drivers/gpu/drm/xe/xe_device.c |
From: Ville Syrjälä
Pull the new_bw_state->active_pipes computation out from
intel_compute_sagv_mask() and move it into the intel_bw.c
(which is arguably the correct place for it).
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bw.c | 29
drivers/
From: Ville Syrjälä
I want to use the crtc_state->inherited flag to clean up some
of the early SAGV handling. To make that work nicely I need to
flag even the inactive crtcs as "inherited".
Since we can't expect user space to perform any real commits
on inactive crtcs we'll clear the flag alread
From: Ville Syrjälä
Now that all the sagv computation has been moved from the
skl+ watermark code into intel_bw_atomic_check() there is
no point in calling intel_bw_modeset_checks() before the
wm computation. Hide it within intel_bw_atomic_check().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/
From: Ville Syrjälä
Move the bw_state->pipe_sagv_reject computation into intel_bw.c
where it belongs.
Previously we had a complicated dance between watermarks and
sagv which required this to be computed earlier, but that was
changed in commit 5e8146251f7b ("extract intel_bw_check_sagv_mask()")
w
From: Ville Syrjälä
If there are no changes to intel_crtc_can_enable_sagv() there
is no need to do all the sagv bw_state recomputation.
The only slight caveat here is hw state takeover where we
initially disable SAGV, and want it to get re-enabled once
we've determined that it's safe to do so.
== Series Details ==
Series: mtd: add driver for Intel discrete graphics (rev7)
URL : https://patchwork.freedesktop.org/series/140306/
State : warning
== Summary ==
Error: dim checkpatch failed
5a696b562b94 mtd: core: always create master device
a547710a3913 mtd: add driver for intel graphics
== Series Details ==
Series: VRR Register Read/Write Updates (rev2)
URL : https://patchwork.freedesktop.org/series/146778/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16321 -> Patchwork_146778v2
Summary
---
**FAILU
On Wed, Mar 26, 2025 at 09:33:20PM +0530, Ankit Nautiyal wrote:
> To avoid having VRR read/write for DSI transcoders, we currently use
> !transcoder_is_dsi() in many places.
> Instead introduce a new helper to check transcoder_has_vrr() and use
> that to exclude transcoders which do not support VRR
On Wed, Mar 26, 2025 at 09:33:21PM +0530, Ankit Nautiyal wrote:
> For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
> bits are not required. Since the support for these bits is going to
> be deprecated in upcoming platforms, avoid writing these bits for the
> platforms that do n
GSC NVM controller HW errors on quad access overlapping 1K border.
Align 64bit read and write to avoid readq/writeq over 1K border.
Acked-by: Miquel Raynal
Signed-off-by: Alexander Usyskin
---
drivers/mtd/devices/mtd_intel_dg.c | 35 ++
1 file changed, 35 insertions(
On Wed, Mar 19, 2025 at 04:02:17PM +0530, Arun R Murthy wrote:
> Hook up the newly added plane function pointer
> format_mod_supported_async to populate the modifiers/formats supported
> by asynchronous flips.
>
> v5: Correct the if condition for modifier support check (Chaitanya)
> v6: Replace ui
On Wed, Mar 19, 2025 at 04:02:17PM +0530, Arun R Murthy wrote:
> Hook up the newly added plane function pointer
> format_mod_supported_async to populate the modifiers/formats supported
> by asynchronous flips.
>
> v5: Correct the if condition for modifier support check (Chaitanya)
> v6: Replace ui
On Wed, Mar 19, 2025 at 04:02:15PM +0530, Arun R Murthy wrote:
> There exists a property IN_FORMATS which exposes the plane supported
> modifiers/formats to the user. In some platforms when asynchronous flip
> are used all of modifiers/formats mentioned in IN_FORMATS are not
> supported. This patch
On Wed, Mar 19, 2025 at 04:02:16PM +0530, Arun R Murthy wrote:
> create_in_formats creates the list of supported format/modifiers for
> synchronous flips, modify the same function so as to take the
> format_mod_supported as argument and create list of format/modifier for
> async as well.
>
> v5: c
== Series Details ==
Series: drm/i915: sagv/bw cleanup (rev4)
URL : https://patchwork.freedesktop.org/series/146014/
State : warning
== Summary ==
Error: dim checkpatch failed
9fc812bc536d drm/i915: Drop the cached per-pipe min_cdclk[] from bw state
0bc4c8cc5e4c drm/i915: s/intel_crtc_bw/intel
On Wed, Mar 26, 2025 at 12:59:55AM +0900, Vincent Mailhol via B4 Relay wrote:
> Introduce some fixed width variant of the GENMASK() and the BIT()
> macros in bits.h. For example:
>
> GENMASK_U16(16, 0)
>
> will raise a build bug.
>
> This series is a continuation of:
>
>
> https://lore.ker
From: Andi Shyti
Some GPUs, like DG2, can host more than one CCS engine. Some
workarounds or enablements need to happen only once for all the
engines in the GT—for example, on the engine with the lowest
instance.
The FIRST_CCS() helper first checks if the engine is a Compute
engine, and then whe
On Wed, Mar 26, 2025 at 05:26:11PM +0200, Alexander Usyskin wrote:
> Add driver for access to Intel discrete graphics card
> internal NVM device.
> Expose device on auxiliary bus by i915 and Xe drivers and
> provide mtd driver to register this device with MTD framework.
>
> This is a rewrite of "d
== Series Details ==
Series: Remove I915_ENGINE_FIRST_RENDER_COMPUTE
URL : https://patchwork.freedesktop.org/series/146832/
State : warning
== Summary ==
Error: dim checkpatch failed
a150ec769409 drm/i915: Add the FIRST_CCS() helper
-:27: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'e__' - pos
elp, would you please give this a try?
> > https://lore.kernel.org/linux-iommu/20250324170743.GA1339275@ax162/
> >
>
> Thank you, Nicolin, for your reply. Unfortunately, these changes
> does not solve the issue. (applied individually and together)
Would you please try the lat
Hi,
While testing the multi-CCS static load balancing, Arshad
discovered that the CCS workaround was being applied twice, due
to commit [*].
Further discussions with Lucas led to rethinking the purpose of
I915_ENGINE_FIRST_RENDER_COMPUTE. This flag was originally
introduced to handle plat
From: Andi Shyti
The I915_ENGINE_FIRST_RENDER_COMPUTE flag is no longer used.
Its purpose has been replaced by the FIRST_CCS() helper, which
determines the first render or compute engine as needed.
Remove the flag definition and its assignment from
intel_engine_setup().
Suggested-by: Lucas De M
From: Andi Shyti
Replace checks for I915_ENGINE_FIRST_RENDER_COMPUTE combined
with CCS_MASK() with the FIRST_CCS() helper. This improves
readability and ensures that certain CCS-specific actions, such
as enabling GEN12_RCU_MODE and calling xehp_enable_ccs_engines(),
are performed only once, on th
From: Andi Shyti
All platforms supported by i915 have at least one RCS engine,
so there's no need to explicitly check for RCS or CCS presence.
Remove the redundant check and move the associated functions
to a more appropriate location in the code.
Signed-off-by: Andi Shyti
---
drivers/gpu/drm
The CCS engine workaround was previously added in a section
shared by both RCS and CCS engines.
Move it to the proper CCS-specific section so that it's applied
only once, avoiding unintended duplication caused by the first
CCS/RCS detection check.
To do this, the ccs_mode() function had to be mov
== Series Details ==
Series: Implement Wa_14021768792 to bypass m_n ratio limit (rev4)
URL : https://patchwork.freedesktop.org/series/138257/
State : warning
== Summary ==
Error: dim checkpatch failed
8c868148a86f Add bits for link_n_exended for DISPLAY >= 14
76bc82ed6982 drm/i915/display: Lim
== Series Details ==
Series: drm/i915: reduce intel_wakeref.h dependencies
URL : https://patchwork.freedesktop.org/series/146799/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: Disable RPG during live selftest (rev5)
URL : https://patchwork.freedesktop.org/series/143886/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16321 -> Patchwork_143886v5
Summary
---
On 3/22/2025 12:01 AM, Ville Syrjälä wrote:
On Fri, Mar 21, 2025 at 04:56:47PM +0530, Ankit Nautiyal wrote:
LINK_N register has bits 31:24 for extended link N value used for
HDMI2.1 and for an alternate mode of operation of DP TG DDA
(Bspec:50488).
Add support for these extra bits.
For displ
Acked-by: Zhi Wang
Jani Nikula 于 2025年3月26日周三 下午1:56写道：
> On Thu, 27 Feb 2025, Jani Nikula wrote:
> > Update GVT-g MAINTAINERS entry to reflect the current status of
> > maintenance and repositories.
> >
> > Cc: Dave Airlie
> > Cc: Joonas Lahtinen
> > Cc: Rodrigo Vivi
> > Cc: Simona Vetter
Usually I'd argue hardcoding values is the wrong thing to do, but in
this case, GVT looking deep into the guts of the DPLL manager for the
reference clocks is worse. This is done for BDW and BXT only, and there
shouldn't be any reason to try to be so dynamic about it.
This helps reduce the direct
> -Original Message-
> From: Nicolin Chen
> Sent: Tuesday, March 25, 2025 1:10 PM
> To: Borah, Chaitanya Kumar
> Cc: io...@lists.linux.dev; intel-gfx@lists.freedesktop.org; intel-
> x...@lists.freedesktop.org; Kurmi, Suresh Kumar
> ; Saarinen, Jani ;
> j...@nvidia.com
> Subject: Re: Re
Quoting Andi Shyti (2025-03-25 12:52:58)
> On Tue, Mar 25, 2025 at 10:24:42AM +0200, Joonas Lahtinen wrote:
> > Do you have a reference to some GitLab issues or maybe some external
> > project issues where regressions around here are discussed?
>
> AFAIK, there's no GitLab issue for this becaus
On Wed, Mar 26, 2025 at 01:00:01AM +0900, Vincent Mailhol via B4 Relay wrote:
> From: Vincent Mailhol
>
> Add some additional tests in lib/tests/test_bits.c to cover the
> expected results of the fixed type BIT_U*() macros.
>
> Signed-off-by: Vincent Mailhol
> Reviewed-by: Lucas De Marchi
New
> On Wed, Mar 19, 2025 at 04:02:16PM +0530, Arun R Murthy wrote:
> > create_in_formats creates the list of supported format/modifiers for
> > synchronous flips, modify the same function so as to take the
> > format_mod_supported as argument and create list of format/modifier
> > for async as well.
On 3/26/2025 10:39 PM, Ville Syrjälä wrote:
On Wed, Mar 26, 2025 at 09:33:21PM +0530, Ankit Nautiyal wrote:
For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
bits are not required. Since the support for these bits is going to
be deprecated in upcoming platforms, avoid writi
== Series Details ==
Series: Remove I915_ENGINE_FIRST_RENDER_COMPUTE
URL : https://patchwork.freedesktop.org/series/146832/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16321 -> Patchwork_146832v1
Summary
---
**SUCC
> On Wed, Mar 19, 2025 at 04:02:17PM +0530, Arun R Murthy wrote:
> > Hook up the newly added plane function pointer
> > format_mod_supported_async to populate the modifiers/formats supported
> > by asynchronous flips.
> >
> > v5: Correct the if condition for modifier support check (Chaitanya)
> > v
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