Add support for blocking the IRQ handling on the HPD pin of a given
encoder, handling IRQs that arrived while in the blocked state after
unblocking the IRQ handling. This will be used by a follow-up change,
which blocks/unblocks the IRQ handling around DP link training.
This is similar to the inte
The Xserver has been moved to using pixman for all matrix operations, back in
2008, but left some #define's so drivers still compile. Since 1.5 decades have
passed now, it's time to fix remaining drivers still using the old name, so
we can drop these #define's from the Xserver includes.
Signed-off
After link training - both in case of a passing and failing LT result -
a work is scheduled to check the link state. This check should take
place after the link training is completed by disabling the link
training pattern and setting intel_dp::link_trained=true. Atm, the work
is scheduled before th
On 3/5/2025 12:20 AM, Ville Syrjälä wrote:
On Tue, Mar 04, 2025 at 01:49:41PM +0530, Ankit Nautiyal wrote:
During modeset enable sequence, program the fixed timings, and turn on the
VRR Timing Generator (VRR TG) for platforms that always use VRR TG.
For this intel_vrr_set_transcoder now alway
Add support for blocking the IRQ handling on the HPD pin of a given
encoder, handling IRQs that arrived while in the blocked state after
unblocking the IRQ handling. This will be used by a follow-up change,
which blocks/unblocks the IRQ handling around DP link training.
This is similar to the inte
FBDEV ggtt is not restored correctly, add missing GGTT flag to
intel_fbdev_fb_alloc to make it work.
This ensures that the global GGTT mapping is always restored on resume. The
GGTT mapping would
otherwise be created in intel_fb_pin_to_ggtt() by intel_fbdev anyway.
This fixes the fbdev device no
On Wed, Mar 05, 2025 at 02:11:21PM +0530, Nautiyal, Ankit K wrote:
>
> On 3/5/2025 12:20 AM, Ville Syrjälä wrote:
> > On Tue, Mar 04, 2025 at 01:49:41PM +0530, Ankit Nautiyal wrote:
> >> During modeset enable sequence, program the fixed timings, and turn on the
> >> VRR Timing Generator (VRR TG) f
On 2025-03-05 00:09, Lucas De Marchi wrote:
> On Thu, Feb 20, 2025 at 06:17:01PM +0100, Maarten Lankhorst wrote:
>> Hey,
>>
>> On 2025-02-20 16:43, Matthew Auld wrote:
>>> On 20/02/2025 14:22, Lucas De Marchi wrote:
On Wed, Feb 19, 2025 at 04:34:40PM +0100, Maarten Lankhorst wrote:
> Th
On Wed, Mar 05, 2025 at 10:51:20AM -0600, Knop, Ryszard wrote:
Hey everyone,
Patchwork has been having lots of issues recently, dropping patches,
being unusably slow and generally starting to become more of a pain
than help. Over on the CI side we are also not super fond of it and we
don't have
On Wed, 05 Mar 2025, "Knop, Ryszard" wrote:
> Hey everyone,
>
> Patchwork has been having lots of issues recently, dropping patches,
> being unusably slow and generally starting to become more of a pain
> than help. Over on the CI side we are also not super fond of it and we
> don't have enough re
== Series Details ==
Series: drm/i915/dp: Fix link training interrupted by HPD pulse (rev3)
URL : https://patchwork.freedesktop.org/series/145782/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
This defines a new structure to define color lut ranges,
along with related macro definitions and enums. This will help
describe segmented lut ranges/PWL LUTs in the hardware.
Signed-off-by: Uma Shankar
Signed-off-by: Chaitanya Kumar Borah
---
include/uapi/drm/drm_mode.h | 64 ++
Add capability property which a colorop can expose it's
hardware's abilities. It's a blob property that can be
filled with respective data structures depending on the
colorop. The user space is expected to read this property
and program the colorop accordingly.
v2: Added documentation for hw_caps
On Wed, Mar 05, 2025 at 03:05:25AM +0900, Masahiro Yamada wrote:
> > IMO headers should almost invariably be self-contained, instead of
> > putting the burden on their users to include other headers to make it
> > work. It's a PITA in a project the size of the kernel, or even just the
> > drm subsy
Hi
The bug appeared recently once, and it is possible that it will pop up
from time to times, so it might be better to get rid of this workaround
from the kernel, especially since it's already in Mesa. I would like to
know, what you think about it ?
--
Best regards,
Sebastian
Hi Ville
On Wed Mar 5, 2025 at 3:26 PM UTC, Ville Syrjälä wrote:
> On Wed, Mar 05, 2025 at 02:49:46PM +, Sebastian Brzezinka wrote:
>> This reverts commit 0ddae025ab6cefa9aba757da3cd1d27908d70b0e.
>>
>> According to bspec 14181, CACHE_MODE_0 is a register that's under userspace
>> control, an
== Series Details ==
Series: drm/i915/dp: Fix link training interrupted by HPD pulse (rev3)
URL : https://patchwork.freedesktop.org/series/145782/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16229 -> Patchwork_145782v3
Su
On Tue, 04 Mar 2025, "Garg, Nemesa" wrote:
> LGTM,
> Reviewed-by: Nemesa Garg
Thanks for the reviews, series pushed to drm-intel-next.
BR,
Jani.
--
Jani Nikula, Intel
Hey everyone,
Patchwork has been having lots of issues recently, dropping patches,
being unusably slow and generally starting to become more of a pain
than help. Over on the CI side we are also not super fond of it and we
don't have enough resources to maintain it properly. Lucas has
suggested usi
Starting with commit ec3e00b4ee27 ("drm/i915: stop registering if
drm_dev_register() fails"), we may return from i915_driver_register()
immediately, skipping remaining registration steps. However, the
_unregister() counterpart called at device remove knows nothing about that
skip and executes reve
Starting with commit ec3e00b4ee27 ("drm/i915: stop registering if
drm_dev_register() fails"), we return from i915_driver_register()
immediately if drm_dev_register() fails, skipping remaining registration
steps. However, the _unregister() counterpart called at device remove
knows nothing about tha
To simplify i915_driver_unregister() code, make sure reverts of driver
registration steps executed before potentially unsuccessful device
registration are symmetrically called after drm_dev_unplug(). There is
one case that doesn't follow that rule, introduced by commit b46a33e271ed
("drm/i915/pmu:
Further simplification of i915_driver_unregister() requires moving of two
steps, intel_pxp_fini() and intel_gt_driver_unregister(), down, e.g.,
right behind drm_dev_unplug(). Local testing hasn't revealed any issues
with that move, so go for it.
Former placement of intel_gt_driver_unregister() wi
== Series Details ==
Series: Revert "drm/i915: Disable compression tricks on JSL"
URL : https://patchwork.freedesktop.org/series/145842/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16229 -> Patchwork_145842v1
Summary
Now that we have a flag that indicates device registration status, when
unregistering the driver, jump over reverts of driver registration steps
that were not called due to device registration failure.
Unfortunately, not all steps of i915_driver_unregister() are limited only
to reverting changes i
From: Chaitanya Kumar Borah
Add intel colorop create helper
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 39 ++
drivers/gpu/drm/i915/display/intel_color.h | 3 ++
2 files changed, 42 insertions(+)
diff -
Existing LUT precision structure is having only 16 bit
precision. This is not enough for upcoming enhanced hardwares
and advance usecases like HDR processing. Hence added a new
structure with 32 bit precision values.
Signed-off-by: Uma Shankar
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gp
This series intends to add support for Plane Color Management for
Intel platforms. This is based on the design which has been agreed
upon by the community. Series implementing the design for generic
DRM core has been sent out by Harry Wentland and is under review
below:
https://patchwork.freedeskto
From: Chaitanya Kumar Borah
Add a color pipeline with three colorops in the sequence
1D LUT MULTSEG - CTM - 1D LUT MULTSEG
This pipeline can be used to do any color space conversion or HDR
tone mapping
Signed-off-by: Uma Shankar
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/d
From: Chaitanya Kumar Borah
Add macros to identify intel color blocks. It will help
in mapping drm_color_ops to intel color HW blocks
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_display_limits.h | 13 +
1 file changed, 13
From: Chaitanya Kumar Borah
Add support for color ops that can be programmed
by 1 dimensional multi segmented Look Up Tables.
v2: Fixed the documentation for Multi segmented lut (Dmitry)
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_atomic.c |
From: Chaitanya Kumar Borah
Add data structure to store intel specific details of colorop
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
.../drm/i915/display/intel_display_types.h| 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/
Hi Mikolaj
On Tue Mar 4, 2025 at 1:09 PM UTC, Mikolaj Wasiak wrote:
> This test exposes bug in tigerlake hardware which prevents it from
> succeeding. Since the tested feature is only available on bugged hardware
> and we won't support any new hardware, this test is obsolete and
> should be remove
On Wed, Mar 05, 2025 at 10:22:44AM -0500, Yury Norov wrote:
> + Anshuman Khandual
>
> Anshuman,
>
> I merged your GENMASK_U128() because you said it's important for your
> projects, and that it will get used in the kernel soon.
>
> Now it's in the kernel for more than 6 month, but no users were
On Wed, 05 Mar 2025, Yury Norov wrote:
> On Wed, Mar 05, 2025 at 10:00:15PM +0900, Vincent Mailhol via B4 Relay wrote:
>> +#define GENMASK_U8(h, l) ((unsigned int)GENMASK_t(u8, h, l))
>> +#define GENMASK_U16(h, l) ((unsigned int)GENMASK_t(u16, h, l))
>
> Typecast to the type that user provides ex
On Wed, 05 Mar 2025, Vincent Mailhol via B4 Relay
wrote:
> Introduce some fixed width variant of the GENMASK() and the BIT()
> macros in bits.h. Note that the main goal is not to get the correct
> type, but rather to enforce more checks at compile time. For example:
>
> GENMASK_U16(16, 0)
>
> w
From: Chaitanya Kumar Borah
Add supported color pipelines and attach it to plane.
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 42 ++
drivers/gpu/drm/i915/display/intel_color.h | 3 ++
2 files changed, 45
From: Chaitanya Kumar Borah
Add callback to intel color functions for setting plane CTM.
Signed-off-by: Uma Shankar
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_color.c | 23 ++
drivers/gpu/drm/i915/display/intel_color.h | 3 ++-
2 files cha
From: Chaitanya Kumar Borah
Add framework that will help in loading LUT to Pre/Post CSC color
blocks.
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 27 ++
drivers/gpu/drm/i915/display/intel_color.h | 2 ++
Add callback for programming Pre-CSC LUT for TGL and beyond
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 88 ++
1 file changed, 88 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/dr
This adds helper functions to create 1D multi-segmented Lut
color block capabilities. It exposes the hardware block as segments
which are converted to blob and passed in the property.
This also adds helper to initialize 1D segmented LUT.
v2: Squashed the 1d lut helpers (Dmitry)
Signed-off-by: Cha
From: Chaitanya Kumar Borah
Add support for 3x3 Color Transformation Matrices in Color Pipeline.
v2: Updated the documentation for 3x3 CTM colorop (Dmitry)
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_atomic.c | 3 +++
drivers/gpu/drm/drm_atom
From: Chaitanya Kumar Borah
Expose color pipeline and add ability to program it.
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/skl_uni
Add callback for setting CTM block in platforms D13 and beyond
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 79 ++
1 file changed, 79 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b
From: Chaitanya Kumar Borah
Since we intend to add plane color callbacks from Xelpd(D13 and beyond),
create a different structure for it.
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 15 ++-
1 file changed, 14 ins
From: Chaitanya Kumar Borah
Add infrastructure to set colorop. We iterate through all the color ops
in a selected COLOR PIPELINE and set them one by one.
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 31 ++
On Wed, Mar 05, 2025 at 11:39:50AM +0100, Maarten Lankhorst wrote:
On 2025-03-05 00:09, Lucas De Marchi wrote:
On Thu, Feb 20, 2025 at 06:17:01PM +0100, Maarten Lankhorst wrote:
Hey,
On 2025-02-20 16:43, Matthew Auld wrote:
On 20/02/2025 14:22, Lucas De Marchi wrote:
On Wed, Feb 19, 2025 a
On Wed, Mar 05, 2025 at 12:01:06PM +0100, Maarten Lankhorst wrote:
FBDEV ggtt is not restored correctly, add missing GGTT flag to
intel_fbdev_fb_alloc to make it work.
This ensures that the global GGTT mapping is always restored on resume. The
GGTT mapping would
otherwise be created in intel_fb
On 3/5/2025 6:23 PM, Ville Syrjälä wrote:
On Wed, Mar 05, 2025 at 02:11:21PM +0530, Nautiyal, Ankit K wrote:
On 3/5/2025 12:20 AM, Ville Syrjälä wrote:
On Tue, Mar 04, 2025 at 01:49:41PM +0530, Ankit Nautiyal wrote:
During modeset enable sequence, program the fixed timings, and turn on the
V
This reverts commit 0ddae025ab6cefa9aba757da3cd1d27908d70b0e.
According to bspec 14181, CACHE_MODE_0 is a register that's under userspace
control, and DISABLE_REPACKING_FOR_COMPRESSION workaround should be already
in all recent Mesa releases. So, there is no need to include it in kernel.
Also, th
On Wed, Mar 05, 2025 at 02:49:46PM +, Sebastian Brzezinka wrote:
> This reverts commit 0ddae025ab6cefa9aba757da3cd1d27908d70b0e.
>
> According to bspec 14181, CACHE_MODE_0 is a register that's under userspace
> control, and DISABLE_REPACKING_FOR_COMPRESSION workaround should be already
> in al
On 3/5/2025 12:19 AM, Ville Syrjälä wrote:
On Tue, Mar 04, 2025 at 01:49:33PM +0530, Ankit Nautiyal wrote:
Currently we always compute the timings as if vrr is enabled.
With this approach the state checker becomes complicated when we
introduce fixed refresh rate mode with vrr timing generator.
On 3/5/2025 12:26 AM, Ville Syrjälä wrote:
On Tue, Mar 04, 2025 at 01:49:44PM +0530, Ankit Nautiyal wrote:
To have Guardband/Pipeline_full reconfigured seamlessly, move the
guardband and pipeline_full from intel_pipe_config_compare() to fastboot
exception.
Update the intel_set_transcoder_timin
On 3/5/2025 12:37 AM, Ville Syrjälä wrote:
On Tue, Mar 04, 2025 at 01:49:45PM +0530, Ankit Nautiyal wrote:
VRR with joiner is currently disabled as it still needs some work to
correctly sequence the primary and secondary transcoders. However, we can
still use VRR Timing generator in fixed refr
On 3/5/2025 12:23 AM, Ville Syrjälä wrote:
On Tue, Mar 04, 2025 at 01:49:42PM +0530, Ankit Nautiyal wrote:
For fixed refresh rate use fixed timings for all platforms that support
VRR. For this add checks to avoid computing and reading VRR for
platforms that do not support VRR.
v2: Avoid touch
On Tue, Mar 04, 2025 at 12:00:31PM -0800, Matt Atwood wrote:
> From: Suraj Kandpal
>
> We only support resolution upto 4k for single pipe when using
> YUV420 format so we prune these modes and restrict the plane size
> at src.
>
> Signed-off-by: Suraj Kandpal
> Signed-off-by: Matt Atwood
> ---
Extract the LUT and program plane post csc registers.
Signed-off-by: Uma Shankar
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_color.c | 109 +
1 file changed, 109 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers
Add macros to define Plane Degamma registers
Signed-off-by: Uma Shankar
Signed-off-by: Chaitanya Kumar Borah
---
.../i915/display/skl_universal_plane_regs.h | 53 +++
1 file changed, 53 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
b/driv
Add documentation to explain properties of the exposed hardware
1D LUT blocks, its identification and computation of the LUT samples
based on the number of samples, their distribution and precison.
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
Documentation/gpu/rfc/color_p
Add macros to define Plane Post CSC registers
Signed-off-by: Uma Shankar
Signed-off-by: Chaitanya Kumar Borah
---
.../i915/display/skl_universal_plane_regs.h | 73 +++
1 file changed, 73 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
b/dri
Hi Nitin,
On Wed, Mar 05, 2025 at 07:45:31AM +, Gote, Nitin R wrote:
> > On Mon, Feb 24, 2025 at 12:01:04PM +0530, Nitin Gote wrote:
> > > Sometimes engine reset fails because the engine resumes from an
> > > incorrect RING_HEAD. Engine head failed to set to zero even after
> > > writing into
On Wed, Mar 05, 2025 at 10:00:15PM +0900, Vincent Mailhol via B4 Relay wrote:
> From: Yury Norov
>
> Add __GENMASK_t() which generalizes __GENMASK() to support different
Is it with double underscore? I do not see it.
_t is used for typedef simple types. It's unfortunate to have it
in such a mac
On Wed, Mar 05, 2025 at 10:00:13PM +0900, Vincent Mailhol via B4 Relay wrote:
> From: Vincent Mailhol
>
> "int" was misspelled as "init" in GENMASK_U128() comments. Fix the typo.
Please, fix it everywhere:
$ git grep -lw __init128
include/linux/bits.h
include/uapi/linux/const.h
tools/include/li
On Wed, Mar 05, 2025 at 10:00:17PM +0900, Vincent Mailhol via B4 Relay wrote:
> From: Lucas De Marchi
>
> Now that include/linux/bits.h implements fixed-width GENMASK_*, use them
GENMASK_*()
and in the Subject
REG_GENMASK*()
> to implement the i915/xe specific macros. Converting each driver t
On Wed, Mar 05, 2025 at 10:00:16PM +0900, Vincent Mailhol via B4 Relay wrote:
> From: Lucas De Marchi
>
> Implement fixed-type BIT to help drivers add stricter checks, like was
Here and in the Subject I would use BIT_Uxx().
> done for GENMASK().
...
> +/*
> + * Fixed-type variants of BIT(), w
On Wed, Mar 05, 2025 at 09:30:20AM -0500, Yury Norov wrote:
> On Wed, Mar 05, 2025 at 10:00:13PM +0900, Vincent Mailhol via B4 Relay wrote:
> > From: Vincent Mailhol
> >
> > "int" was misspelled as "init" in GENMASK_U128() comments. Fix the typo.
>
> Thanks for respinning the series. I'll take t
On Wed, Mar 05, 2025 at 11:38:19PM +0900, Vincent Mailhol wrote:
> On 05/03/2025 at 23:30, Andy Shevchenko wrote:
> > On Wed, Mar 05, 2025 at 10:00:15PM +0900, Vincent Mailhol via B4 Relay
> > wrote:
...
> > Perhaps T or TYPE will suffice. Or perhaps we want
> > __GENMASK_Uxx() here?
>
> If no
On Wed, Mar 05, 2025 at 11:48:10PM +0900, Vincent Mailhol wrote:
> On 05/03/2025 at 23:33, Andy Shevchenko wrote:
> > On Wed, Mar 05, 2025 at 10:00:16PM +0900, Vincent Mailhol via B4 Relay
> > wrote:
...
> >> +#define BIT_U8(b) (BIT_INPUT_CHECK(u8, b) + (unsigned int)BIT(b))
> >> +#define BIT_U1
Rebase of [1]. Patch 1 allows #include "i915_drv.h" to be removed from
intel_atomic_plane.c in patch 2.
BR,
Jani.
[1] https://lore.kernel.org/r/20250228142539.3216960-1-jani.nik...@intel.com
Jani Nikula (2):
drm/xe/compat: refactor compat i915_drv.h
drm/i915/plane: convert intel_atomic_plan
Going forward, struct intel_display is the main display device data
pointer. Convert intel_atomic_plane.[ch] to struct intel_display.
Signed-off-by: Jani Nikula
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 78 +--
1 file changed, 38 insertions(+), 40 deletions(-)
diff --g
The compat i915_drv.h contains things that aren't there in the original
i915_drv.h. Split out gem/i915_gem_object.h and i915_scheduler_types.h,
moving the corresponding pieces out, including FORCEWAKE_ALL to
intel_uncore.h.
Technically I915_PRIORITY_DISPLAY should be in i915_priolist_types.h,
but
Hi Mikolaj,
On 2025-03-04 at 09:43:26 GMT, Mikolaj Wasiak wrote:
> When the driver is loaded on the system with numa nodes it might be run in
> a kthread, which makes it impossible to use current->mm in the selftest.
> This patch allows the selftest to use current->mm by using active_mm.
>
> Sign
On Thu, Mar 06, 2025 at 02:17:18AM +0900, Vincent Mailhol wrote:
> On 06/03/2025 at 00:48, Andy Shevchenko wrote:
> > On Wed, Mar 05, 2025 at 11:48:10PM +0900, Vincent Mailhol wrote:
> >> On 05/03/2025 at 23:33, Andy Shevchenko wrote:
> >>> On Wed, Mar 05, 2025 at 10:00:16PM +0900, Vincent Mailhol
Hi Uma,
kernel test robot noticed the following build errors:
[auto build test ERROR on next-20250305]
[also build test ERROR on v6.14-rc5]
[cannot apply to drm-exynos/exynos-drm-next linus/master v6.14-rc5 v6.14-rc4
v6.14-rc3]
[If your patch is applied to the wrong git tree, kindly drop us a
On Thu, Mar 06, 2025 at 01:48:49AM +0900, Vincent Mailhol wrote:
> On 06/03/2025 at 00:47, Yury Norov wrote:
> > On Wed, Mar 05, 2025 at 10:00:15PM +0900, Vincent Mailhol via B4 Relay
> > wrote:
...
> > Having, in fact, different implementations of the same macro for kernel
> > and userspace is
On Wed, Mar 05, 2025 at 07:52:31PM +0200, Jani Nikula wrote:
On Wed, 05 Mar 2025, "Knop, Ryszard" wrote:
Hey everyone,
Patchwork has been having lots of issues recently, dropping patches,
being unusably slow and generally starting to become more of a pain
than help. Over on the CI side we are
Hi Uma,
kernel test robot noticed the following build errors:
[auto build test ERROR on next-20250305]
[also build test ERROR on v6.14-rc5]
[cannot apply to drm-exynos/exynos-drm-next linus/master v6.14-rc5 v6.14-rc4
v6.14-rc3]
[If your patch is applied to the wrong git tree, kindly drop us a
Hi Uma,
kernel test robot noticed the following build warnings:
[auto build test WARNING on next-20250305]
[also build test WARNING on v6.14-rc5]
[cannot apply to drm-exynos/exynos-drm-next linus/master v6.14-rc5 v6.14-rc4
v6.14-rc3]
[If your patch is applied to the wrong git tree, kindly drop
== Series Details ==
Series: drm/xe/compat: cleanup
URL : https://patchwork.freedesktop.org/series/145854/
State : warning
== Summary ==
Error: dim checkpatch failed
0e1c61e96f57 drm/xe/compat: refactor compat i915_drv.h
-:36: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
M
== Series Details ==
Series: drm/xe/compat: cleanup
URL : https://patchwork.freedesktop.org/series/145854/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16230 -> Patchwork_145854v1
Summary
---
**FAILURE**
Serious
== Series Details ==
Series: drm/i915: Fix harmfull driver register/unregister assymetry (rev4)
URL : https://patchwork.freedesktop.org/series/144436/
State : warning
== Summary ==
Error: dim checkpatch failed
fc579ebc3a39 drm/i915: Skip harmful unregister steps if not registered
-:14: WARNING
== Series Details ==
Series: drm/i915: Fix harmfull driver register/unregister assymetry (rev4)
URL : https://patchwork.freedesktop.org/series/144436/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: Fix harmfull driver register/unregister assymetry (rev4)
URL : https://patchwork.freedesktop.org/series/144436/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16231 -> Patchwork_144436v4
> -Original Message-
> From: Intel-gfx On Behalf Of Jani
> Nikula
> Sent: Wednesday, March 5, 2025 10:08 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel...@lists.freedesktop.org; Nikula, Jani ;
> Vivi,
> Rodrigo
> Subject: [PATCH v2 1/2] drm/xe/compat: refactor compat i915_drv.h
>
> -Original Message-
> From: Intel-gfx On Behalf Of Jani
> Nikula
> Sent: Wednesday, March 5, 2025 10:08 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel...@lists.freedesktop.org; Nikula, Jani ;
> Vivi,
> Rodrigo
> Subject: [PATCH v2 2/2] drm/i915/plane: convert intel_atomic_plane
85 matches
Mail list logo
