== Series Details ==
Series: drm/i915/dmc_wl: Do not check for DMC payload
URL : https://patchwork.freedesktop.org/series/143951/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16018 -> Patchwork_143951v1
Summary
---
On Fri, Jan 24, 2025 at 08:30:09PM +0530, Ankit Nautiyal wrote:
> DP sink uses MSA timings for the fixed refresh rate mode.
> For using VRR timing generator for fixed refresh rate mode, the HW prepares
> the Vtotal for the MSA from the VMAX register. Since the MSA Vtotal is
> one-based while Vmax i
On Fri, Jan 24, 2025 at 08:29:56PM +0530, Ankit Nautiyal wrote:
> CMRR has a separate logic for computing vrr timings and so it
> overwrites the timings prepared for vrr.
>
> Avoid prepare vrr timings for cmrr. This will help to separate the
> helpers for timings for vrr, cmrr and the forthcoming
On Fri, Jan 24, 2025 at 08:30:05PM +0530, Ankit Nautiyal wrote:
> As per the spec, the PUSH enable must be set if not configuring for a
> fixed refresh rate (i.e Vmin == Flipline == Vmax is not true).
>
> v2: Use helper intel_vrr_use_push(). (Ville)
> v3: directly use the condition, instead of che
On Fri, Jan 24, 2025 at 08:30:06PM +0530, Ankit Nautiyal wrote:
> MSA Ignore Timing PAR enable is set in the DP sink when we enable variable
> refresh rate. When using VRR timing generator for fixed refresh rate
> we do not want to ignore the mode timings, as the refresh rate is still
> fixed. Modi
On Fri, Jan 24, 2025 at 12:45:40PM +, Patchwork wrote:
Patch Details
Series: drm/i915/pmu: Fix zero delta busyness issue
URL: [1]https://patchwork.freedesktop.org/series/143900/
State: failure
Details:
[2]https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143900v1/index.html
C
== Series Details ==
Series: drm/i915: intel_display conversions and some debug improvements
URL : https://patchwork.freedesktop.org/series/143942/
State : warning
== Summary ==
Error: dim checkpatch failed
deccf783a3bf drm/i915: Decouple i915_gem_dumb_create() from the display a bit
0dac8de94
== Series Details ==
Series: drm/i915: intel_display conversions and some debug improvements
URL : https://patchwork.freedesktop.org/series/143942/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Thu, Jan 23, 2025 at 11:38:39AM -0800, Umesh Nerlige Ramappa wrote:
> When running igt@gem_exec_balancer@individual for multiple iterations,
> it is seen that the delta busyness returned by PMU is 0. The issue stems
> from a combination of 2 implementation specific details:
>
> 1) gt_park is th
== Series Details ==
Series: drm/i915/cmtg: Disable the CMTG (rev9)
URL : https://patchwork.freedesktop.org/series/142947/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/cmtg: Disable the CMTG (rev9)
URL : https://patchwork.freedesktop.org/series/142947/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16018 -> Patchwork_142947v9
Summary
---
**SUCCE
On Fri, Jan 24, 2025 at 01:06:08PM -0500, Rodrigo Vivi wrote:
On Thu, Jan 23, 2025 at 11:38:39AM -0800, Umesh Nerlige Ramappa wrote:
When running igt@gem_exec_balancer@individual for multiple iterations,
it is seen that the delta busyness returned by PMU is 0. The issue stems
from a combination
Enabling and disabling of DMC wakelock is already coupled with enabling
and disabling of dynamic DC states, which already depend on the DMC
being properly loaded. As such, we do not need to check if we already
have a DMC payload parsed in __intel_dmc_wl_supported().
Furthermore, the presence of su
== Series Details ==
Series: drm/i915/cmtg: Disable the CMTG (rev9)
URL : https://patchwork.freedesktop.org/series/142947/
State : warning
== Summary ==
Error: dim checkpatch failed
fb2adb7ce696 drm/i915/cmtg: Disable the CMTG
-:87: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), d
On Fri, Jan 24, 2025 at 08:29:49PM +0530, Ankit Nautiyal wrote:
> From: Mitul Golani
>
> Compute as_sdp.vtotal based on minimum vtotal calculated
> during vrr computation.
>
> --v2:
> - make a separate patch and update to vmin only [Ankit].
>
> --v3:
> - Update vtotal to vmin for cmrr case as
Hi，
At 2025-01-23 23:09:09, "Jani Nikula" wrote:
>The expectation is that the struct drm_device based logging helpers get
>passed an actual struct drm_device pointer rather than some random
>struct pointer where you can dereference the ->dev member.
>
>Convert drm_err(hdmi, ...) to dev_err(hdmi-
On Fri, Jan 24, 2025 at 09:29:32AM +0100, Thomas Zimmermann wrote:
> Hi Dave, Sima,
>
> here's the weekly PR for drm-misc-fixes.
>
> Best regards
> Thomas
>
> drm-misc-fixes-2025-01-24:
> Short summary of fixes pull:
>
> bochs:
> - Fix double-free on driver removal
>
> client:
> - Improve supp
On Fri, Jan 24, 2025 at 01:43:25PM +0200, Ville Syrjälä wrote:
> On Fri, Jan 24, 2025 at 12:56:23PM +0200, Jouni Högander wrote:
> > We may have commit which doesn't have any non-arming plane register
> > writes. In that case there aren't "Frame Change" event before DSB vblank
> > evasion which han
On Fri, 2025-01-24 at 13:39 +0200, Ville Syrjälä wrote:
> On Fri, Jan 24, 2025 at 12:56:22PM +0200, Jouni Högander wrote:
> > PIPEDSL is reading as 0 when in SRDENT(PSR1) or DEEP_SLEEP(PSR2).
> > On
> > wake-up scanline counting starts from vblank_start - 1. We don't
> > know if
> > wake-up is alre
Do needed changes to handle PSR2_MAN_TRK_CTL correctly when DSB is in use:
1. Write PSR2_MAN_TRK_CTL in commit_pipe_pre_planes only when not using
DSB.
2. Add PSR2_MAN_TRK_CTL writing into DSB commit in
intel_atomic_dsb_finish.
Taking PSR lock over DSB commit is not needed because PSR2_MAN_
Now as we have correct PSR2_MAN_TRK_CTL handling in place we can allow DSB
usage also when PSR is enabled for LunarLake onwards.
Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
On Fri, Jan 24, 2025 at 12:56:22PM +0200, Jouni Högander wrote:
> PIPEDSL is reading as 0 when in SRDENT(PSR1) or DEEP_SLEEP(PSR2). On
> wake-up scanline counting starts from vblank_start - 1. We don't know if
> wake-up is already ongoing when evasion starts. In worst case PIPEDSL could
> start rea
PIPEDSL is reading as 0 when in SRDENT(PSR1) or DEEP_SLEEP(PSR2). On
wake-up scanline counting starts from vblank_start - 1. We don't know if
wake-up is already ongoing when evasion starts. In worst case PIPEDSL could
start reading valid value right after checking the scanline. In this
scenario we
psr_force_hw_tracking_exit is misleading name as it is used for PSR1, PSR2
HW tracking and PSR2 selective fetch. Due to this rename it as
intel_psr_force_update.
Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_psr.c | 8
1 file changed, 4
This patch set is doing necessary modifications to support PSR update
using DSB on LunarLake onwards
It is not necessary to wait for PSR1 to idle or PSR2 to exit DEEP
sleep at the begin of commit This is left out from DSB commit. There
might be room for optimization for non-DSB as well because suc
We are preparing for a change where only frontbuffer flush will use
single full frame bit of a new register (SFF_CTL) available on LunarLake
onwards.
It shouldn't be necessary to have SFF bit set if CFF bit is set in
PSR2_MAN_TRK_CTL -> removing setting it on all platforms as there is not
reason t
This is a clean-up and a preparation for adding own SFF and CFF registers
for LunarLake onwards.
Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_psr.c | 88 +---
1 file changed, 31 insertions(+), 57 deletions(-)
diff --git a/d
In LunarLake we have SFF_CTL register which contains SFF bit ored with
respective SFF bit in PSR2_MAN_TRK_CTL register. Use this register instead
of the bit in PSR2_MAN_TRK_CTL on frontbuffer tracking callbacks. This
helps us avoiding taking psr mutex when performing atomic commit.
We don't need t
Add register definitions for SFF_CTL and CFF_CTL registers. Name them as
LNL_SFF_CTL and LNL_CFF_CTL.
v2: use _MMIO_TRANS instead of _MMIO_TRANS2
Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_psr_regs.h | 10 ++
1 file changed, 10 inser
Allow writing PSR2_MAN_TRK_CTL using DSB by using intel_de_write_dsb. Do
not check intel_dp->psr.lock being held when using DSB. This assertion
doesn't make sense as in case of using DSB the actual write happens later
and we are not taking intel_dp->psr.lock mutex over dsb commit.
Signed-off-by: J
We have different approach on how flip is considered being complete. We are
waiting for vblank on DSB and generate interrupt when it happens and this
interrupt is considered as indication of completion -> we definitely do not
want to skip vblank wait.
Also not skipping scanline wait shouldn't caus
Changing PSR mode using DSB is not implemented. Do not use DSB when PSR
mode is changing.
Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/
We may have commit which doesn't have any non-arming plane register
writes. In that case there aren't "Frame Change" event before DSB vblank
evasion which hangs as PIPEDSL register is reading as 0 when PSR state is
SRDENT(PSR1) or DEEP_SLEEP(PSR2). Handle this by adding dummy write
triggering the "
Add new interface for checking possible PSR/PR mode change. We need this
information to decide if DSB can be used.
Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_psr.c | 20
drivers/gpu/drm/i915/display/intel_psr.h | 2 ++
2
On Fri, 24 Jan 2025, "Andy Yan" wrote:
> Hi，
>
> At 2025-01-23 23:09:09, "Jani Nikula" wrote:
>>The expectation is that the struct drm_device based logging helpers get
>>passed an actual struct drm_device pointer rather than some random
>>struct pointer where you can dereference the ->dev member.
On Fri, Jan 24, 2025 at 12:56:23PM +0200, Jouni Högander wrote:
> We may have commit which doesn't have any non-arming plane register
> writes. In that case there aren't "Frame Change" event before DSB vblank
> evasion which hangs as PIPEDSL register is reading as 0 when PSR state is
> SRDENT(PSR1)
On Thu, 23 Jan 2025, Simona Vetter wrote:
> On Thu, Jan 23, 2025 at 05:09:10PM +0200, Jani Nikula wrote:
>> The expectation is that the struct drm_device based logging helpers get
>> passed an actual struct drm_device pointer rather than some random
>> struct pointer where you can dereference the
On Fri, Jan 24, 2025 at 12:56:21PM +0200, Jouni Högander wrote:
> We have different approach on how flip is considered being complete. We are
> waiting for vblank on DSB and generate interrupt when it happens and this
> interrupt is considered as indication of completion -> we definitely do not
> w
On Thu, 23 Jan 2025, Gustavo Sousa wrote:
> Quoting Jani Nikula (2025-01-23 12:14:31-03:00)
>>On Thu, 23 Jan 2025, Jani Nikula wrote:
>>> From: Gustavo Sousa
>>>
>>> The header drm_print.h uses members of struct drm_device pointers, as
>>> such, it should include drm_device.h to let the compiler
We are preparing for a change where only frontbuffer flush will use
single full frame bit of a new register (SFF_CTL) available on LunarLake
onwards.
It shouldn't be necessary to have SFF bit set if CFF bit is set in
PSR2_MAN_TRK_CTL -> removing setting it on all platforms as there is not
reason t
On Fri, 2025-01-24 at 13:46 +0200, Ville Syrjälä wrote:
> On Fri, Jan 24, 2025 at 12:56:21PM +0200, Jouni Högander wrote:
> > We have different approach on how flip is considered being
> > complete. We are
> > waiting for vblank on DSB and generate interrupt when it happens
> > and this
> > interru
On Fri, Jan 24, 2025 at 12:56:20PM +0200, Jouni Högander wrote:
> Changing PSR mode using DSB is not implemented. Do not use DSB when PSR
> mode is changing.
>
> Signed-off-by: Jouni Högander
> Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
> 1 file cha
On Fri, 2025-01-24 at 13:43 +0200, Ville Syrjälä wrote:
> On Fri, Jan 24, 2025 at 12:56:23PM +0200, Jouni Högander wrote:
> > We may have commit which doesn't have any non-arming plane register
> > writes. In that case there aren't "Frame Change" event before DSB
> > vblank
> > evasion which hangs
In LunarLake we have SFF_CTL register which contains SFF bit ored with
respective SFF bit in PSR2_MAN_TRK_CTL register. Use this register instead
of the bit in PSR2_MAN_TRK_CTL on frontbuffer tracking callbacks. This
helps us avoiding taking psr mutex when performing atomic commit.
We don't need t
This patch set is doing necessary modifications to support PSR update
using DSB on LunarLake onwards
It is not necessary to wait for PSR1 to idle or PSR2 to exit DEEP
sleep at the begin of commit This is left out from DSB commit. There
might be room for optimization for non-DSB as well because suc
PIPEDSL is reading as 0 when in SRDENT(PSR1) or DEEP_SLEEP(PSR2). On
wake-up scanline counting starts from vblank_start - 1. We don't know if
wake-up is already ongoing when evasion starts. In worst case PIPEDSL could
start reading valid value right after checking the scanline. In this
scenario we
We may have commit which doesn't have any non-arming plane register
writes. In that case there aren't "Frame Change" event before DSB vblank
evasion which hangs as PIPEDSL register is reading as 0 when PSR state is
SRDENT(PSR1) or DEEP_SLEEP(PSR2). Handle this by adding dummy write
triggering the "
Add new interface for checking possible PSR/PR mode change. We need this
information to decide if DSB can be used.
Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_psr.c | 20
drivers/gpu/drm/i915/display/intel_psr.h | 2 ++
2
Changing PSR mode using DSB is not implemented. Do not use DSB when PSR
mode is changing.
Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/
Do needed changes to handle PSR2_MAN_TRK_CTL correctly when DSB is in use:
1. Write PSR2_MAN_TRK_CTL in commit_pipe_pre_planes only when not using
DSB.
2. Add PSR2_MAN_TRK_CTL writing into DSB commit in
intel_atomic_dsb_finish.
Taking PSR lock over DSB commit is not needed because PSR2_MAN_
This is a clean-up and a preparation for adding own SFF and CFF registers
for LunarLake onwards.
Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_psr.c | 88 +---
1 file changed, 31 insertions(+), 57 deletions(-)
diff --git a/d
Now as we have correct PSR2_MAN_TRK_CTL handling in place we can allow DSB
usage also when PSR is enabled for LunarLake onwards.
Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
Allow writing PSR2_MAN_TRK_CTL using DSB by using intel_de_write_dsb. Do
not check intel_dp->psr.lock being held when using DSB. This assertion
doesn't make sense as in case of using DSB the actual write happens later
and we are not taking intel_dp->psr.lock mutex over dsb commit.
Signed-off-by: J
Add register definitions for SFF_CTL and CFF_CTL registers. Name them as
LNL_SFF_CTL and LNL_CFF_CTL.
v2: use _MMIO_TRANS instead of _MMIO_TRANS2
Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_psr_regs.h | 10 ++
1 file changed, 10 inser
On Fri, Jan 24, 2025 at 12:16:56PM +, Hogander, Jouni wrote:
> On Fri, 2025-01-24 at 14:09 +0200, Hogander, Jouni wrote:
> > On Fri, 2025-01-24 at 13:53 +0200, Ville Syrjälä wrote:
> > > On Fri, Jan 24, 2025 at 12:56:20PM +0200, Jouni Högander wrote:
> > > > Changing PSR mode using DSB is not i
On Fri, Jan 24, 2025 at 11:57:10AM +, Hogander, Jouni wrote:
> On Fri, 2025-01-24 at 13:39 +0200, Ville Syrjälä wrote:
> > On Fri, Jan 24, 2025 at 12:56:22PM +0200, Jouni Högander wrote:
> > > PIPEDSL is reading as 0 when in SRDENT(PSR1) or DEEP_SLEEP(PSR2).
> > > On
> > > wake-up scanline coun
On Fri, 2025-01-24 at 14:32 +0200, Ville Syrjälä wrote:
> On Fri, Jan 24, 2025 at 12:16:56PM +, Hogander, Jouni wrote:
> > On Fri, 2025-01-24 at 14:09 +0200, Hogander, Jouni wrote:
> > > On Fri, 2025-01-24 at 13:53 +0200, Ville Syrjälä wrote:
> > > > On Fri, Jan 24, 2025 at 12:56:20PM +0200, Jo
On Fri, 2025-01-24 at 14:37 +0200, Ville Syrjälä wrote:
> On Fri, Jan 24, 2025 at 11:57:10AM +, Hogander, Jouni wrote:
> > On Fri, 2025-01-24 at 13:39 +0200, Ville Syrjälä wrote:
> > > On Fri, Jan 24, 2025 at 12:56:22PM +0200, Jouni Högander wrote:
> > > > PIPEDSL is reading as 0 when in SRDENT
== Series Details ==
Series: drm/i915/cx0: Set ssc_enabled for c20 too (rev2)
URL : https://patchwork.freedesktop.org/series/143824/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
> -Original Message-
> From: Al Viro On Behalf Of Al Viro
> Sent: Thursday, January 23, 2025 11:49 PM
> To: Borah, Chaitanya Kumar
> Cc: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org; Kurmi,
> Suresh Kumar ; Saarinen, Jani
> ; linux-fsde...@vger.kernel.org
> Subject:
== Series Details ==
Series: drm/i915/cx0: Set ssc_enabled for c20 too (rev2)
URL : https://patchwork.freedesktop.org/series/143824/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16017 -> Patchwork_143824v2
Summary
---
== Series Details ==
Series: drm/i915: intel_display conversions and some debug improvements
URL : https://patchwork.freedesktop.org/series/143942/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16018 -> Patchwork_143942v1
S
The CMTG is a timing generator that runs in parallel with transcoders
timing generators and can be used as a reference for synchronization.
We have observed that we are inheriting from GOP a display configuration
with the CMTG enabled. Because our driver doesn't currently implement
any CMTG sequen
On Fri, Jan 24, 2025 at 08:50:23AM +0200, Badal Nilawar wrote:
> The Forcewake timeout issue has been observed on Gen 12.0 and above. To
> address this,
> disable Render Power-Gating (RPG) during live self-tests for these
> generations.
> The temporary workaround 'drm/i915/mtl: do not enable rend
On Fri, Jan 24, 2025 at 08:30:16PM +0530, Ankit Nautiyal wrote:
> To work seamlessly between variable and fixed timings,
> intel_vrr_{enable,disable}() should just flip between the fixed and
> variable timings in vmin/flipline/vmax.
>
> The idea is to just do this for all the platforms, regardless
Hi Sebastian,
> This reverts commit 835443da6f50d9516b58bba5a4fdf9e563d961c7.
>
> - turns out that logging with gt_err() causes CI to pick up an error
> even in intentional error injects,
> - the unintentional (real) errors are already reported correctly by CI,
> - a gt wedge is already being l
Hi Dave, Sima,
here's the weekly PR for drm-misc-fixes.
Best regards
Thomas
drm-misc-fixes-2025-01-24:
Short summary of fixes pull:
bochs:
- Fix double-free on driver removal
client:
- Improve support for tile-based modes
- Fix fbdev Kconfig select rules
xlnx:
- zynqmp_dp: Add locking to DP-b
Hi Dave, Simona,
Oops, I messsed up the pull request, didn't see the other commits in the
branch.
Additionally:
- Fix bogus Kconfig change in cgroup/rdma
- Kernel doc fixup for xlnx.
- virtio UAF in virtgpu
Cheers,
~Maarten
drm-misc-next-fixes-2025-01-24:
drm-misc-next-fixes for v6.14-rc1:
-
Switching between variable and fixed timings is possible as for that we
just need to flip between VRR timings. However for CMRR along with the
timings, few other bits also need to be changed on the fly, which might
cause issues. So disable CMRR for now, till we have variable and fixed
timings sorte
On Fri, Jan 24, 2025 at 04:25:32PM +0100, Maarten Lankhorst wrote:
> Hi Dave, Simona,
>
> Oops, I messsed up the pull request, didn't see the other commits in the
> branch.
>
> Additionally:
> - Fix bogus Kconfig change in cgroup/rdma
> - Kernel doc fixup for xlnx.
> - virtio UAF in virtgpu
Ah h
On Wed, Jan 22, 2025 at 10:07 PM Srinivas, Vidya
wrote:
>
> Hello Brian, Many thanks for the fix. I am adding my tested-by.
> Tested-by: Vidya Srinivas
Thanks for testing Vidya.
Can we get a maintainer to take a look?
>
>
> > -Original Message-
> > From: Brian Geffon
> > Sent: 16 Janu
Separate out functions for computing cmrr and vrr timings.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_vrr.c | 45 +++-
1 file changed, 28 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/di
Add vrr enable/disable steps to the modeset sequence for MTL+ when we
want to always use the vrr timing generator.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_display.c | 20 +++-
drivers/gpu/drm/i915/display/intel_vrr.c | 5 +
drivers/gpu/drm/i9
Currently we always compute the timings as if vrr is enabled.
With this approach the state checker becomes complicated when we
introduce fixed refresh rate mode with vrr timing generator.
To avoid the complications, instead of always computing vrr timings, we
compute vrr timings based on uapi.vrr_
== Series Details ==
Series: Use VRR timing generator for fixed refresh rate modes (rev7)
URL : https://patchwork.freedesktop.org/series/134383/
State : warning
== Summary ==
Error: dim checkpatch failed
90e352a2d66b drm/i915/vrr: Add crtc_state dump for vrr.vsync params
-:24: WARNING:QUOTED_W
== Series Details ==
Series: Use VRR timing generator for fixed refresh rate modes (rev7)
URL : https://patchwork.freedesktop.org/series/134383/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/in
== Series Details ==
Series: Use VRR timing generator for fixed refresh rate modes (rev7)
URL : https://patchwork.freedesktop.org/series/134383/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16017 -> Patchwork_134383v7
Summ
From: Ville Syrjälä
struct intel_display will replace struct drm_i915_private as
the main thing for display code. Convert the cursor code to
use it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_crtc.c | 2 +-
drivers/gpu/drm/i915/display/intel_cursor.c | 136
From: Ville Syrjälä
struct intel_display will replace struct drm_i915_private as
the main thing for display code. Convert the skl+ universal plane
code to use it.
Note that we still have two straggles in the form on
HAS_FLAT_CCS() and the pxp stuff.
Signed-off-by: Ville Syrjälä
---
drivers/gp
From: Ville Syrjälä
struct intel_display will replace struct drm_i915_private as
the main thing for display code. Convert the fb code to
use it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 3 +-
drivers/gpu/drm/i915/display/intel_cursor.c | 3 +-
driv
From: Ville Syrjälä
struct intel_display will replace struct drm_i915_private as
the main thing for display code. Convert the pre-skl primary plane
code to use it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 240 +++---
drivers/gpu/drm/i915/disp
From: Ville Syrjälä
Include the standard "[PLANE:%d:s]" stuff in all plane debugs
(or rather all I was able to find), to provide better information
on which plane we're actually talking about.
There are a few spots where we care about the CRTC as well, so
include that where appropriate.
Signed-
From: Ville Syrjälä
Switch the plane debugs to use DRM_RECT_FMT & co. instead
of drm_rect_debug_print() so that the debugs go on the same line.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
From: Ville Syrjälä
Pass intel_display to the display power stuff. These are spread
all over the place so tend to hinder clean conversions of whole
files.
TODO: The gt part/unpark power domain shenanigans need some
kind of more abstract interface...
Signed-off-by: Ville Syrjälä
---
drivers/gp
From: Ville Syrjälä
Convert a bunch of stuff over to struct intel_display, and
finish off with a few debug print improvements.
Ville Syrjälä (11):
drm/i915: Decouple i915_gem_dumb_create() from the display a bit
drm/i915: Decouple intel_fb_bo.h interfaces from driver specific types
drm/i91
From: Ville Syrjälä
Pass the device argument as drm_device to intel_plane_fb_max_stride()
to decouple i915_gem_dumb_create() vs. the display code a bit.
xe currently doesn't even call this, but it probably should...
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c
From: Ville Syrjälä
Make the intel_fb_bo.h interfaces operated purely in base
drm_ types so that each driver (i915 and xe) doesn't have to
know about each other, or the display stuff.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fb.c| 5 ++---
drivers/gpu/drm/i915/di
From: Ville Syrjälä
intel_sprite.c was partially converted to struct intel_display.
Finish the job now that we can deal with the platform checks
as well.
And while at it we also move the 'display' variable declaration
to be the first thing in most functions, consistency. We can
actually do that
From: Ville Syrjälä
struct intel_display will replace struct drm_i915_private as
the main thing for display code. Convert intel_crtc.c code to
use it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/g4x_dp.c | 4 +-
drivers/gpu/drm/i915/display/g4x_hdmi.c | 3 +-
Quoting Ville Syrjälä (2025-01-24 12:16:20-03:00)
>On Fri, Jan 24, 2025 at 11:32:13AM -0300, Gustavo Sousa wrote:
>> Quoting Ville Syrjälä (2025-01-24 10:02:18-03:00)
>> >On Wed, Jan 22, 2025 at 05:03:41PM -0300, Gustavo Sousa wrote:
>> >> The CMTG is a timing generator that runs in parallel with t
== Series Details ==
Series: drm/i915: Disable RPG during live selftest (rev2)
URL : https://patchwork.freedesktop.org/series/143886/
State : warning
== Summary ==
Error: dim checkpatch failed
01853816d099 drm/i915: Disable RPG during live selftest
-:6: WARNING:COMMIT_LOG_LONG_LINE: Prefer a m
Quoting Ville Syrjälä (2025-01-24 10:02:18-03:00)
>On Wed, Jan 22, 2025 at 05:03:41PM -0300, Gustavo Sousa wrote:
>> The CMTG is a timing generator that runs in parallel with transcoders
>> timing generators and can be used as a reference for synchronization.
>>
>> We have observed that we are inh
== Series Details ==
Series: drm/i915: Disable RPG during live selftest (rev2)
URL : https://patchwork.freedesktop.org/series/143886/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16017 -> Patchwork_143886v2
Summary
---
== Series Details ==
Series: PSR DSB support (rev6)
URL : https://patchwork.freedesktop.org/series/142520/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:116:1: warning: unr
== Series Details ==
Series: PSR DSB support (rev6)
URL : https://patchwork.freedesktop.org/series/142520/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16017 -> Patchwork_142520v6
Summary
---
**SUCCESS**
No regre
On Thu, Jan 23, 2025 at 07:47:14AM +, Murthy, Arun R wrote:
> > > On Wed, Jan 08, 2025 at 11:09:00AM +0530, Arun R Murthy wrote:
> > > > Expose drm plane function to create formats/modifiers blob. This
> > > > function can be used to expose list of supported formats/modifiers
> > > > for sync/a
psr_force_hw_tracking_exit is misleading name as it is used for PSR1, PSR2
HW tracking and PSR2 selective fetch. Due to this rename it as
intel_psr_force_update.
Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_psr.c | 8
1 file changed, 4
== Series Details ==
Series: Introduce DRM device wedged event (rev9)
URL : https://patchwork.freedesktop.org/series/138069/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Introduce DRM device wedged event (rev9)
URL : https://patchwork.freedesktop.org/series/138069/
State : warning
== Summary ==
Error: dim checkpatch failed
5c0d56fa92ec drm: Introduce device wedged event
-:194: WARNING:STATIC_CONST_CHAR_ARRAY: char * array declarati
== Series Details ==
Series: Introduce DRM device wedged event (rev9)
URL : https://patchwork.freedesktop.org/series/138069/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16017 -> Patchwork_138069v9
Summary
---
**SUC
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