Issue is seen when PSR enabled with setup frames and when try to disable
PSR at SRDONACK State (0x1). PSR FSM is stuck at SRDONACK(0x1) for more
than 5 seconds. Issue not seen with Setup frames disabled. Currently
disable psr1 if setuptime > vblank to workaround the above issue.
HSD: 16024594674
During GuC reset prepare, interrupt is disabled, if the interrupt
event already happens and is in progress, from interrupt event to
tasklet get running, there is alway some kind of latency. In long
latency case, it might have 2 rare race conditions:
1. Tasklet runs after IRQ flush, add request to q
All MTL and ARL SKUs share the same GSC FW, but the newer platforms are
only supported in newer blobs. In particular, ARL-S is supported
starting from 102.0.10.1878 (which is already the minimum required
version for ARL in the code), while ARL-H and ARL-U are supported from
102.1.15.1926. Therefore
From: Dnyaneshwar Bhadane
Common display code requires IS_PANTHERLAKE macro.
Define the macro and set 0 as PTL is no longer support for i915.
Signed-off-by: Dnyaneshwar Bhadane
Signed-off-by: Matt Atwood
Signed-off-by: Clint Taylor
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/i915_drv.h
From: Suraj Kandpal
Read PICA register to see if edp over type C is possible and then
add the appropriate tables for it.
--v2
-remove bool from intel_encoder have it in runtime_info [Jani]
-initialize the bool in runtime_info init [Jani]
-dont abbreviate the bool [Jani]
--v3
-Remove useless dis
From: "Heikkila, Juha-pekka"
Xe3 has no more support for x-tile on display.
v2: Include up to display 29 for X-tiled support. (Gustavo)
Signed-off-by: Heikkila, Juha-pekka
Signed-off-by: Matt Atwood
Signed-off-by: Clint Taylor
Reviewed-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/int
Switch to using the new display->platform. members for
platform identification in display code.
v2: Split out an unrelated hunk to a separate patch (Rodrigo)
Reviewed-by: Rodrigo Vivi
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_vblank.c | 8
1 file changed, 4 ins
Switch to using the new display->platform. members for
platform identification in display code.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_bios.c | 40 +--
1 file changed, 15 insertions(+), 25 deletions(-)
diff --git a/driver
Switch to using the new display->platform. members for
platform identification in display code.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_pps.c | 47 ++--
1 file changed, 20 insertions(+), 27 deletions(-)
diff --git a/driver
Switch to using the new display->platform. members for
platform identification in display code.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_vga.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i
Use struct intel_display where possible.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_vblank.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c
b/drivers/gpu/drm/i915/display/intel_v
From: Matt Roper
There are some minor changes to pmdemand handling on Xe3:
- Active scalers are no longer tracked. We can simply skip the readout
and programming of this field.
- Active dbuf slices are no longer tracked. We should skip the readout
and programming of this field and also
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch Cx0 PHY code over to it.
v2: Rebase, split out the include cleanups (Rodrigo)
Reviewed-by: Rodrigo Vivi
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 33
Just resending [1] because I never got the CI logs for it.
[1] https://lore.kernel.org/r/cover.1729776384.git.jani.nik...@intel.com
Jani Nikula (12):
drm/i915/gmbus: convert to struct intel_display
drm/i915/cx0: remove unnecessary includes
drm/i915/cx0: convert to struct intel_display
drm
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch DPIO PHY code over to it.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Jani Nikula
---
.../i915/display/intel_display_power_well.c | 19 ++-
drivers/gpu/drm/i915/display/intel_dpio_phy.c
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch gmbus code over to it.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_bios.c | 6 +-
drivers/gpu/drm/i915/display/intel_crt.c |
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch CRT code over to it.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_crt.c | 209 +-
drivers/gpu/drm/i915/display/intel_
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch DP HDCP code over to it.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 88 ++--
1 file changed, 45 insertions(+
There are some unconverted stragglers left in the HDCP API still using
struct drm_i915_private. Convert to struct intel_display.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Jani Nikula
---
.../drm/i915/display/intel_display_driver.c | 7 +++--
drivers/gpu/drm/i915/display/intel_dp.c | 3
There's nothing in the header that requires the bit or bitfield
headers. Remove.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
b/drivers/gpu
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch vlv_wait_port_ready() over to
it. The main motivation to do just one function is to stop passing i915
to intel_de_wait(), so its generic wrapper can be removed.
Reviewed-by: Rodrigo Vivi
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch assert_chv_phy_status() and its
callers to it. Main motivation to do just one function is to stop
passing i915 to intel_de_wait(), so its generic wrapper can be removed.
Reviewed-by: Rodri
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch HSW IPS code over to it.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/hsw_ips.c | 47 ++
1 file changed, 26 insertions(+
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch ICL DSI code over to it.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/icl_dsi.c | 444 ---
drivers/gpu/drm/i915/display/ic
With many of the intel_de_* callers switched over to struct
intel_display, we can remove some of the unnecessary generic wrappers.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_de.h | 46 ++---
1 file changed, 18 insertions(+), 2
On Mon, Oct 28, 2024 at 3:04 PM Jani Nikula wrote:
>
> drm_dev_register() already prints the same information on successful
> init. Remove the redundant prints.
>
> Signed-off-by: Jani Nikula
Acked-by: Alex Deucher
>
> ---
>
> Note: I prefer to merge this together with the next patch via
> drm
Hello Ville,
As suggested on Revision 1,
Added,
1. State checker and dump for vrr.vsync_{start,end},
2. Removed dependency from vrr.enable
Any further inputs on this ?
> -Original Message-
> From: Intel-gfx On Behalf Of
> Mitul Golani
> Sent: 21 October 2024 16:21
> To: intel-gfx@list
We need to disable HDCP Line Rekeying for Xe3 when we are using an HDMI
encoder. Also remove the Wa comment tag as this follows the bspec and
does not implement the wa.
v2: add additional definition instead of function, commit message typo
fix and update.
v3: restore lost conditional from v2.
v4:
We are currently seeing unexpected link trainings with several different
eDP panels. These are caused by these panels stating bad link status in
their dpcd registers. This can be observed by doing following test:
1. Boot up without Xe module loaded
2. Load Xe module with PSR disabled:
$ modpr
On Fri, 25 Oct 2024, Jani Nikula wrote:
> On Fri, 25 Oct 2024, Raag Jadav wrote:
>> @@ -70,6 +73,16 @@ static struct dentry *drm_debugfs_root;
>>
>> DEFINE_STATIC_SRCU(drm_unplug_srcu);
>>
>> +/*
>> + * Available recovery methods for wedged device. To be sent along with
>> device
>> + * wed
Increase the max source width and height to be able to support 6k
resolution
on a single pipe. The changes for cdclk that accompany this change are
already merged in the code.
Bspec: 68858
Signed-off-by: Arun R Murthy
Signed-off-by: Suraj Kandpal
Suraj Kandpal (3):
drm/i915/xe3lpd: Increase r
On Mon, 2024-10-28 at 03:51 +, Kandpal, Suraj wrote:
>
>
> > -Original Message-
> > From: Roper, Matthew D
> > Sent: Saturday, October 26, 2024 3:31 AM
> > To: Kandpal, Suraj
> > Cc: intel...@lists.freedesktop.org;
> > intel-gfx@lists.freedesktop.org; Nautiyal,
> > Ankit K
> > Subj
DISPLAY_VER >= 30 onwards CRTC can now support 6k resolution.
Increase pipe and plane max width and height to reflect this
increase in resolution.
--v2
-Take care of the subsampling scenario sooner rather than later [Matt]
--v3
-Take care of the joined pipe limits too [Ankit/Matt]
--v4
-Leave th
Change the check to only check for psr size limits till Pre-Xe2
since after that the psr size is equal to maximum pipe size anyways.
--v2
-Check only size limit until pre-Xe2 [Matt]
Bspec: 69885, 68858
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_psr.c | 4 ++--
1 file ch
With 6k resolution support for a single crtc being added
bigjoiner will only come into picture when hdisplay > 6144
Signed-off-by: Suraj Kandpal
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/driver
> -Original Message-
> From: Sousa, Gustavo
> Sent: Wednesday, 23 October 2024 23.40
> To: Atwood, Matthew S ; intel-
> g...@lists.freedesktop.org; intel...@lists.freedesktop.org
> Cc: Kahola, Mika ; Atwood, Matthew S
> ; Taylor, Clinton A
> Subject: Re: [PATCH 12/12] drm/i915/xe3lpd: Pow
Quoting Clint Taylor (2024-10-25 17:47:42-03:00)
>From: Mika Kahola
>
>There is a HW issue that arises when there are race conditions
>between TCSS entering/exiting TC7 or TC10 states while the
>driver is asserting/deasserting TCSS power request. As a
>workaround, Display driver will implement a m
Quoting Govindapillai, Vinod (2024-10-28 12:19:01-03:00)
>On Fri, 2024-10-25 at 13:47 -0700, Clint Taylor wrote:
>> From: Matt Roper
>>
>> There are some minor changes to pmdemand handling on Xe3:
>> - Active scalers are no longer tracked. We can simply skip the readout
>> and programming of
We stopped using the driver initialized date in commit 7fb8af6798e8
("drm: deprecate driver date") and (eventually) started returning "0"
for drm_version ioctl instead.
Finish the job, and remove the unused date member from struct
drm_driver, its initialization from drivers, along with the common
drm_dev_register() already prints the same information on successful
init. Remove the redundant prints.
Signed-off-by: Jani Nikula
---
Note: I prefer to merge this together with the next patch via
drm-misc-next.
Cc: Oleksandr Andrushchenko
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Thomas
The ivpu struct drm_driver has conditional initialization based on #ifdef
DRIVER_DATE, which is never defined anywhere. Neither are the macros
referenced within the block: DRIVER_DATE, DRIVER_MAJOR, DRIVER_MINOR,
and DRIVER_PATCHLEVEL. With the struct drm_driver date member going away
anyway, just
On 10/28/2024 1:13 PM, Suraj Kandpal wrote:
Change the check to only check for psr size limits till Pre-Xe2
since after that the psr size is equal to maximum pipe size anyways.
--v2
-Check only size limit until pre-Xe2 [Matt]
Bspec: 69885, 68858
Signed-off-by: Suraj Kandpal
LGTM.
Reviewed
On Mon, 28 Oct 2024, Vinod Govindapillai wrote:
> From: Stanislav Lisovskiy
>
> From LNL onwards there is a new hardware feature, which
> allows to detect if the driver wrongly allocated DBuf
> entries and they happen to overlap. If enabled this will
> cause a specific interrupt to occur.
> We no
On 10/26/2024 8:26 AM, Lucas De Marchi wrote:
> When the exec queue is destroyed, there's a race between a query to the
> fdinfo and the exec queue value being updated: after the destroy ioctl,
> if the fdinfo is queried before a call to guc_exec_queue_free_job(),
> the wrong utilization is repor
On 10/26/2024 8:26 AM, Lucas De Marchi wrote:
> Help debugging when LRC timestamp is updated for a exec queue.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Nirmoy Das
> ---
> drivers/gpu/drm/xe/Makefile | 1 +
> drivers/gpu/drm/xe/xe_lrc.c | 3 ++
> drivers/gpu/drm/xe/xe_tr
On Mon, 2024-10-28 at 14:24 +0200, Jani Nikula wrote:
> On Mon, 28 Oct 2024, Jouni Högander wrote:
> > We are currently seeing unexpected link trainings with several
> > different
> > eDP panels. These are caused by these panels stating bad link
> > status in
> > their dpcd registers. This can be
== Series Details ==
Series: drm/i915/xe2lpd: Update C20 HDMI TMDS algorithm to include tx_misc
(rev2)
URL : https://patchwork.freedesktop.org/series/140136/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15586 -> Patchwork_140136v2
On 10/28/2024 6:14 PM, Nautiyal, Ankit K wrote:
On 10/28/2024 1:13 PM, Suraj Kandpal wrote:
Change the check to only check for psr size limits till Pre-Xe2
since after that the psr size is equal to maximum pipe size anyways.
--v2
-Check only size limit until pre-Xe2 [Matt]
Bspec: 69885, 688
On Mon, 28 Oct 2024, Arun R Murthy wrote:
> Mandate a minimum Hblank symbol cycle count between BS and BE in 8b/10b
> MST and 12b/132b mode.
> Spec: DP2.1a
>
> v2: Affine calculation/updation of min HBlank to dp_mst (Jani)
> v3: moved min_hblank from struct intel_dp to intel_crtc_state (Jani)
>
>
== Series Details ==
Series: drm/xe: Fix races on fdinfo
URL : https://patchwork.freedesktop.org/series/140538/
State : warning
== Summary ==
Error: dim checkpatch failed
be111ababfbe drm/xe: Add trace to lrc timestamp update
-:44: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), do
== Series Details ==
Series: drm/xe: Fix races on fdinfo
URL : https://patchwork.freedesktop.org/series/140538/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/xe: Fix races on fdinfo
URL : https://patchwork.freedesktop.org/series/140538/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15602 -> Patchwork_140538v1
Summary
---
**SUCCESS**
No
Quoting Mika Kahola (2024-10-28 09:58:35-03:00)
>There is a HW issue that arises when there are race conditions
>between TCSS entering/exiting TC7 or TC10 states while the
>driver is asserting/deasserting TCSS power request. As a
>workaround, Display driver will implement a mailbox sequence
>to ens
On Mon, 28 Oct 2024, Mika Kahola wrote:
> There is a HW issue that arises when there are race conditions
> between TCSS entering/exiting TC7 or TC10 states while the
> driver is asserting/deasserting TCSS power request. As a
> workaround, Display driver will implement a mailbox sequence
> to ensur
This is the first part of a 5-part series (split for convenience). All 5
parts are:
Part 1: https://lore.kernel.org/lkml/cover.1729864615.git.nam...@linutronix.de
Part 2: https://lore.kernel.org/lkml/cover.1729864823.git.nam...@linutronix.de
Part 3: https://lore.kernel.org/lkml/cover.1729865232.gi
+Jani
On Fri, Sep 01, 2023 at 05:04:02PM +0300, Imre Deak wrote:
Disabling HPD polling from i915_hpd_poll_init_work() involves probing
all display connectors explicitly to account for lost hotplug
interrupts. On some platforms (mostly pre-ICL) with HDMI connectors the
I2C EDID bit-banging using
Hi,
> -Original Message-
> From: Intel-gfx On Behalf Of Clint
> Taylor
> Sent: Friday, 25 October 2024 23.48
> To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
> Subject: [PATCH v5 11/11] drm/xe/ptl: Enable PTL display
>
> From: Haridhar Kalvala
>
> Signed-off-by: H
Quoting Clint Taylor (2024-10-25 17:47:38-03:00)
>C10 phy timeouts occur on xe3lpd if the c10 bus is reset every
>transaction. Starting with xe3lpd this is bus reset not necessary
I provided a r-b with minor suggestions to this patch in the v4 series:
https://lore.kernel.org/intel-xe/172986437914
On Fri, Oct 25, 2024 at 01:47:43PM -0700, Clint Taylor wrote:
> From: Haridhar Kalvala
Every patch needs a commit message. No exception.
>
> Signed-off-by: Haridhar Kalvala
> Signed-off-by: Clint Taylor
> ---
> drivers/gpu/drm/xe/xe_pci.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(
With an added commit message (something simple like "At this point we
should have enough support landed to turn on and start testing basic
display functionality" would be fine),
Reviewed-by: Matt Roper
Matt
On Fri, Oct 25, 2024 at 01:47:43PM -0700, Clint Taylor wrote:
> From: Haridhar Kalvala
From: Stanislav Lisovskiy
>From LNL onwards there is a new hardware feature, which
allows to detect if the driver wrongly allocated DBuf
entries and they happen to overlap. If enabled this will
cause a specific interrupt to occur.
We now handle it in the driver, by writing correspondent
error mes
Change the check to only check for psr size limits till Pre-Xe2
since after that the psr size is equal to maximum pipe size anyways.
--v2
-Check only size limit until pre-Xe2 [Matt]
--v3
-Make sure psr_max_{h,v} and max_bpp are equal to crtc_{h,v}_display
and pipe_bpp [Ankit]
Bspec: 69885, 68858
On Fri, 25 Oct 2024, Suraj Kandpal wrote:
> Fix the condition for gsc structure validity in
> gsc_cs_status_check(). It needs to be an OR and not an AND
> condition
This is a completely different and new patch. For future reference,
please send them in new threads, not in-reply-to the old ones. I
== Series Details ==
Series: drm/i915/xe2lpd: Update C20 HDMI TMDS algorithm to include tx_misc
(rev2)
URL : https://patchwork.freedesktop.org/series/140136/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15586 -> Patchwork_140136v2
On Thu, Oct 24, 2024 at 10:41:22AM +, Hogander, Jouni wrote:
> On Wed, 2024-10-09 at 21:21 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Looks like CCS + async flips has been a thing for a while now.
> > Enable this for TGL+ render compression modifiers.
> >
> > Note that we ca
On Mon, Oct 28, 2024 at 11:21:59AM -0300, Gustavo Sousa wrote:
> Quoting Raag Jadav (2024-10-28 11:02:02-03:00)
> >On Mon, Oct 28, 2024 at 02:58:35PM +0200, Mika Kahola wrote:
> >
> >...
> >
> >> +static bool wa_tcss_power_request_assert(struct drm_i915_private *i915,
> >> +
On Fri, 2024-10-25 at 13:47 -0700, Clint Taylor wrote:
> From: Matt Roper
>
> There are some minor changes to pmdemand handling on Xe3:
> - Active scalers are no longer tracked. We can simply skip the readout
> and programming of this field.
> - Active dbuf slices are no longer tracked. We
On Fri, Oct 25, 2024 at 07:02:59PM +0300, Imre Deak wrote:
> At least the i-tec USB-C Nano 2x Display Docking Station (containing a
> Synaptics MST branch device) requires the driver to update the source
> OUI DPCD registers to expose its DSC capability. Accordingly update the
> OUI for all sink ty
On Mon, Oct 28, 2024 at 11:44:18AM +0530, Arun R Murthy wrote:
> Mandate a minimum Hblank symbol cycle count between BS and BE in 8b/10b
> MST and 12b/132b mode.
> Spec: DP2.1a
>
> v2: Affine calculation/updation of min HBlank to dp_mst (Jani)
> v3: moved min_hblank from struct intel_dp to intel_c
On Mon, Oct 28, 2024 at 02:58:35PM +0200, Mika Kahola wrote:
...
> +static bool wa_tcss_power_request_assert(struct drm_i915_private *i915,
> + bool enable)
> +{
> + /*
> + * Limit to PTL only
> + * TODO: Add check for PICA IP and use that instea
On Mon, 2024-10-28 at 14:43 +0200, Jani Nikula wrote:
> On Mon, 28 Oct 2024, Vinod Govindapillai
> wrote:
> > From: Stanislav Lisovskiy
> >
> > From LNL onwards there is a new hardware feature, which
> > allows to detect if the driver wrongly allocated DBuf
> > entries and they happen to overla
Quoting Raag Jadav (2024-10-28 11:02:02-03:00)
>On Mon, Oct 28, 2024 at 02:58:35PM +0200, Mika Kahola wrote:
>
>...
>
>> +static bool wa_tcss_power_request_assert(struct drm_i915_private *i915,
>> + bool enable)
>> +{
>> +/*
>> + * Limit to PT
On Tue, Oct 22, 2024 at 01:41:18PM +0300, Alexander Usyskin wrote:
> Enable access to internal non-volatile memory on DGFX
> with GSC/CSC devices via a child device.
> The nvm child device is exposed via auxiliary bus.
I looked at all of the i915 and xe patches here and everything looks right.
Jus
There is a HW issue that arises when there are race conditions
between TCSS entering/exiting TC7 or TC10 states while the
driver is asserting/deasserting TCSS power request. As a
workaround, Display driver will implement a mailbox sequence
to ensure that the TCSS is in TC0 when TCSS power request i
On Mon, Oct 28, 2024 at 09:46:42AM +0200, Jouni Högander wrote:
> We are currently seeing unexpected link trainings with several different
> eDP panels. These are caused by these panels stating bad link status in
> their dpcd registers. This can be observed by doing following test:
>
> 1. Boot up
> -Original Message-
> From: Jadav, Raag
> Sent: Monday, 28 October 2024 16.43
> To: Sousa, Gustavo
> Cc: Kahola, Mika ; intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/i915/xe3lpd: Power request asserting/deasserting
>
> On Mon, Oct 28, 2024 at 11:21:59AM -0300, Gustavo Sou
> -Original Message-
> From: Jani Nikula
> Sent: Monday, 28 October 2024 16.55
> To: Kahola, Mika ; intel-gfx@lists.freedesktop.org
> Cc: Sousa, Gustavo ; Kahola, Mika
>
> Subject: Re: [PATCH] drm/i915/xe3lpd: Power request asserting/deasserting
>
> On Mon, 28 Oct 2024, Mika Kahola wrot
On Thu, Oct 24, 2024 at 10:50:06AM +, Hogander, Jouni wrote:
> On Wed, 2024-10-09 at 21:22 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > TGL+ should no longer need any VT-d scanout workarounds.
> > Don't apply any.
> >
> > Not 100% sure whether pre-SNB might also suffer from th
On Tue, Oct 22, 2024 at 01:41:15PM +0300, Alexander Usyskin wrote:
> Enable runtime PM in mtd driver to notify graphics driver that
> whole card should be kept awake while nvm operations are
> performed through this driver.
>
> CC: Lucas De Marchi
> Signed-off-by: Alexander Usyskin
> ---
> driv
> -Original Message-
> From: Vivi, Rodrigo
> Sent: Monday, October 28, 2024 8:27 PM
> To: Usyskin, Alexander ; Gupta, Anshuman
> ; Deak, Imre
> Cc: Miquel Raynal ; Richard Weinberger
> ; Vignesh Raghavendra ; De Marchi,
> Lucas ; Thomas Hellström
> ; Maarten Lankhorst
> ; Maxime Ripard
On Thu, Oct 24, 2024 at 10:46:42AM +, Hogander, Jouni wrote:
> On Wed, 2024-10-09 at 21:22 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Async flips often require bigger alignment that sync flips.
> > Currently we have HAS_ASYNC_FLIPS() checks strewn about to
> > inidcate that a
On Thu, Oct 24, 2024 at 10:52:13AM +, Hogander, Jouni wrote:
> On Wed, 2024-10-09 at 21:22 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Wa_22011186057 (some CCS problem) only affected ADL A-stepping,
> > which I presume is pre-production hw. Drop the dead code.
>
> Maybe you c
On Mon, 28 Oct 2024, Lucas De Marchi wrote:
> +Jani
>
> On Fri, Sep 01, 2023 at 05:04:02PM +0300, Imre Deak wrote:
>>Disabling HPD polling from i915_hpd_poll_init_work() involves probing
>>all display connectors explicitly to account for lost hotplug
>>interrupts. On some platforms (mostly pre-ICL
On Mon, Oct 28, 2024 at 04:49:21PM +0200, Jani Nikula wrote:
> On Mon, 28 Oct 2024, Lucas De Marchi wrote:
> > +Jani
> >
> > On Fri, Sep 01, 2023 at 05:04:02PM +0300, Imre Deak wrote:
> >>Disabling HPD polling from i915_hpd_poll_init_work() involves probing
> >>all display connectors explicitly to
Commit 255fc1703e42 ("drm/i915/gem: Calculate object page offset for
partial memory mapping") introduced a new offset that is compared to
sg_dma_len(r.sgt.sgp) in remap_io_sg() function. However, later in
remap_sg() the offset (which at that point resides in r->sgt.curr)
is compared to r->sgt.max.
> -Original Message-
> From: dri-devel On Behalf Of
> 1064094...@qq.com
> Sent: Monday, October 28, 2024 3:13 PM
> To: Jani Nikula
> Cc: Vivi, Rodrigo ; De Marchi, Lucas
> ; Thomas ;
> Maarten Lankhorst ; Maxime Ripard
> ; Thomas Zimmermann ;
> David Airlie ; Simona Vetter ; intel-
> g
On Mon, 28 Oct 2024, Jouni Högander wrote:
> We are currently seeing unexpected link trainings with several different
> eDP panels. These are caused by these panels stating bad link status in
> their dpcd registers. This can be observed by doing following test:
>
> 1. Boot up without Xe module loa
On Mon, 28 Oct 2024, Jani Nikula wrote:
> On Mon, 28 Oct 2024, Jouni Högander wrote:
>> We are currently seeing unexpected link trainings with several different
>> eDP panels. These are caused by these panels stating bad link status in
>> their dpcd registers. This can be observed by doing follow
== Series Details ==
Series: drm/i915/xe2lpd: Update C20 HDMI TMDS algorithm to include tx_misc
(rev2)
URL : https://patchwork.freedesktop.org/series/140136/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15586 -> Patchwork_140136v2
== Series Details ==
Series: drm/i915/xe2lpd: Update C20 HDMI TMDS algorithm to include tx_misc
(rev2)
URL : https://patchwork.freedesktop.org/series/140136/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15586 -> Patchwork_140136v2
Commit 255fc1703e42 ("drm/i915/gem: Calculate object page offset for
partial memory mapping") introduced a new offset that is compared to
sg_dma_len(r.sgt.sgp) in remap_io_sg() function. However, later in
remap_sg() the offset (which at that point resides in r->sgt.curr)
is compared to r->sgt.max.
== Series Details ==
Series: drm/i915/display: Add Wa_16023981245 (rev2)
URL : https://patchwork.freedesktop.org/series/140327/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
On Mon, Oct 28, 2024, Nam Cao wrote:
> This is the first part of a 5-part series (split for convenience). All 5
> parts are:
>
> Part 1: https://lore.kernel.org/lkml/cover.1729864615.git.nam...@linutronix.de
> Part 2: https://lore.kernel.org/lkml/cover.1729864823.git.nam...@linutronix.de
> Part 3:
C10 phy timeouts occur on xe3lpd if the c10 bus is reset every
transaction. Although not required by BSPEC bus resets were added for
prior platforms as a workaround. Starting with xe3_lpd this bus reset is
not necessary.
Signed-off-by: Clint Taylor
Reviewed-by: Gustavo Sousa
---
drivers/gpu/drm
From: Dnyaneshwar Bhadane
When deciding the type of the phy, add PTL support to make
sure the correct path is taken for selection of C10 PHY.
Only port A is connected C10 PHY for Pantherlake.
Bspec: 72571
Signed-off-by: Dnyaneshwar Bhadane
Signed-off-by: Matt Atwood
Signed-off-by: Clint Taylo
This series has all review comments addressed and review-by's. Basic
enabling is now complete to start testing.
Clint Taylor (1):
drm/i915/cx0: Remove bus reset after every c10 transaction
Dnyaneshwar Bhadane (3):
drm/i915/ptl: Define IS_PANTHERLAKE macro
drm/i915/cx0: Extend C10 check to P
From: Haridhar Kalvala
At this point we should have enough support landed to turn on and start
basic testing of display functionality.
Signed-off-by: Haridhar Kalvala
Signed-off-by: Clint Taylor
Acked-by: Jani Saarinen
Tested-by: Jani Saarinen
Reviewed-by: Matt Roper
---
drivers/gpu/drm/xe/
Just resending [1] because I never got the CI logs for it.
[1] https://lore.kernel.org/r/cover.1729773149.git.jani.nik...@intel.com
Jani Nikula (16):
drm/i915/display: reindent subplatform initialization
drm/i915/display: use a macro to initialize subplatforms
drm/i915/display: use a macro
We'll be needing a macro based list of platforms for more things in the
future. Start by defining the platform enumerations with it.
v3: Rebase for PTL
Reviewed-by: Rodrigo Vivi
Signed-off-by: Jani Nikula
---
.../drm/i915/display/intel_display_device.h | 119 +-
1 file change
We'll want to use the subplatforms similar to platforms. Join the
subplatforms next to their corresponding platforms. Update the comment
while at it.
v2: Put the subplatforms next to the platforms
Reviewed-by: Rodrigo Vivi
Signed-off-by: Jani Nikula
---
.../drm/i915/display/intel_display_devic
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