Add dmc null check before dereferncing to get the major and minor
version.
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_dmc.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/i
Hi Tejas,
On 2024-10-09 at 15:26:08 +0530, Tejas Upadhyay wrote:
one more nit, imho a patch with new test should have in subject
tests/intel: Add xe_pci_membarrier test
Also see nit about a test name.
> We want to make sure that direct mmap mapping of physical
> page at doorbell space and whole
== Series Details ==
Series: drm/xe: Fix HPD interrupt enabling during runtime resume
URL : https://patchwork.freedesktop.org/series/139813/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15510 -> Patchwork_139813v1
Summary
-Original Message-
From: Deak, Imre
Sent: Wednesday, October 9, 2024 2:26 PM
To: Cavitt, Jonathan
Cc: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2 1/4] drm/i915/dp: Assume panel power is off if runtime
suspended
>
> On Wed, Oct 09, 2024 at 11:3
On Thu, Aug 29, 2024 at 08:38:12AM -, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/mtl: Update PLL c20 phy value for DP uhbr20 (rev2)
> URL : https://patchwork.freedesktop.org/series/137844/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_15307_full
== Series Details ==
Series: Align framebuffers according to what display minimum alignment states
URL : https://patchwork.freedesktop.org/series/139795/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Align framebuffers according to what display minimum alignment states
URL : https://patchwork.freedesktop.org/series/139795/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15508 -> Patchwork_139795v1
=
-Original Message-
From: Intel-gfx On Behalf Of Jouni
Högander
Sent: Wednesday, October 9, 2024 6:42 AM
To: intel-gfx@lists.freedesktop.org
Cc: ville.syrj...@linux.intel.com; jani.nik...@linux.intel.com; Hogander, Jouni
Subject: [PATCH v2 2/2] drm/i915/display: Fix Panel Replay vblank e
On Wed, Oct 09, 2024 at 06:19:47PM +0300, Juha-Pekka Heikkila wrote:
> Align framebuffers in memory according to hw requirements instead of
> default page size alignment.
>
> Signed-off-by: Juha-Pekka Heikkila
> ---
> drivers/gpu/drm/xe/display/xe_fb_pin.c | 57 --
> 1 fi
On Wed, Oct 09, 2024 at 04:05:20PM +0300, Jani Nikula wrote:
> On Wed, 09 Oct 2024, Raag Jadav wrote:
> > On Tue, Oct 08, 2024 at 08:24:42PM +0300, Jani Nikula wrote:
> >> On Mon, 07 Oct 2024, Raag Jadav wrote:
> >> > +
> >> > +/* Wa_14022698589:dg2 */
> >> > +static void intel_enable_g8(struct i
On Wed, 09 Oct 2024, Raag Jadav wrote:
> On Wed, Oct 09, 2024 at 04:05:20PM +0300, Jani Nikula wrote:
>> On Wed, 09 Oct 2024, Raag Jadav wrote:
>> > On Tue, Oct 08, 2024 at 08:24:42PM +0300, Jani Nikula wrote:
>> >> On Mon, 07 Oct 2024, Raag Jadav wrote:
>> >> > +
>> >> > +/* Wa_14022698589:dg2
On Wed, Oct 09, 2024 at 07:42:40PM +0300, Raag Jadav wrote:
> On Wed, Oct 09, 2024 at 04:05:20PM +0300, Jani Nikula wrote:
> > On Wed, 09 Oct 2024, Raag Jadav wrote:
> > > On Tue, Oct 08, 2024 at 08:24:42PM +0300, Jani Nikula wrote:
> > >> On Mon, 07 Oct 2024, Raag Jadav wrote:
> > >> > +
> > >>
== Series Details ==
Series: drm/i915: remove all IS__GT() macros (rev2)
URL : https://patchwork.freedesktop.org/series/139306/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15508 -> Patchwork_139306v2
Summary
---
**
On Tue, 08 Oct 2024, Ville Syrjälä wrote:
> On Mon, Oct 07, 2024 at 09:43:47AM +0200, Thomas Zimmermann wrote:
>> Hi
>>
>> Am 03.10.24 um 13:33 schrieb Ville Syrjala:
>> > From: Ville Syrjälä
>> >
>> > Replace the 'unsigned int i' footguns with plain old signed
>> > int. Avoids accidents if/when
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/display: Add own counter for
Panel Replay vblank workaround
URL : https://patchwork.freedesktop.org/series/139784/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won'
-Original Message-
From: Intel-xe On Behalf Of Juha-Pekka
Heikkila
Sent: Wednesday, October 9, 2024 8:20 AM
To: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
Cc: Juha-Pekka Heikkila
Subject: [PATCH 1/2] drm/xe: add interface to request physical alignment for
buffer obj
== Series Details ==
Series: drm/i915: Async flip + compression, and some plane cleanups
URL : https://patchwork.freedesktop.org/series/139807/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15509 -> Patchwork_139807v1
Summa
Here added interface to request physical alignemnt for BOs and
use it to align framebuffers according to what display code
min_align says.
/Juha-Pekka
Juha-Pekka Heikkila (2):
drm/xe: add interface to request physical alignment for buffer objects
drm/xe/display: align framebuffers according t
Add xe_bo_create_pin_map_at_aligned() which augment
xe_bo_create_pin_map_at() with alignment parameter allowing to pass
required alignemnt if it differ from default.
Signed-off-by: Juha-Pekka Heikkila
---
.../compat-i915-headers/gem/i915_gem_stolen.h | 2 +-
drivers/gpu/drm/xe/xe_bo.c
Align framebuffers in memory according to hw requirements instead of
default page size alignment.
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/xe/display/xe_fb_pin.c | 57 --
1 file changed, 35 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/xe/disp
On Tue, 08 Oct 2024, Chaitanya Kumar Borah
wrote:
> From PTL, FEC_DECODE_EN sequence can be sent to a DPRX independent
> of TRANS_CONF enable. This allows us to re-issue an FEC_DECODE_EN
> sequence without re-doing the whole mode set sequence. This separate
> control over FEC_ECODE_EN/DIS sequenc
Hi Jani,
On 2024-10-09 at 15:02:10 +0300, Jani Nikula wrote:
> On Wed, 09 Oct 2024, Kamil Konieczny wrote:
> > Hi Tejas,
> > On 2024-10-09 at 15:26:08 +0530, Tejas Upadhyay wrote:
> >> We want to make sure that direct mmap mapping of physical
> >> page at doorbell space and whole page is accessibl
-Original Message-
From: Intel-gfx On Behalf Of
Juha-Pekka Heikkila
Sent: Wednesday, October 9, 2024 8:20 AM
To: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
Cc: Juha-Pekka Heikkila
Subject: [PATCH 2/2] drm/xe/display: align framebuffers according to hw
requirements
>
On Wed, Oct 09, 2024 at 11:35:56PM +0300, Cavitt, Jonathan wrote:
> -Original Message-
> From: Intel-xe On Behalf Of Imre Deak
> Sent: Wednesday, October 9, 2024 12:44 PM
> To: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Subject: [PATCH v2 1/4] drm/i915/dp: Assume pan
== Series Details ==
Series: drm/xe: Fix HPD interrupt enabling during runtime resume
URL : https://patchwork.freedesktop.org/series/139813/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On 05-10-2024 02:38, Clint Taylor wrote:
Some devices NAK DPCD writes to the SOURCE OUI (0x300) DPCD registers.
Reduce the log level priority to prevent dmesg noise for these devices.
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
1 file changed, 1 insertio
Hi Dave, Simona,
Here's drm-misc-next for v6.13!
drm-misc-next-2024-10-09:
drm-misc-next for v6.13:
UAPI Changes:
- Add drm fdinfo support to panthor, and add sysfs knob to toggle.
Cross-subsystem Changes:
- Convert fbdev drivers to use backlight power constants.
- Some small dma-fence fixes.
-
From: Ville Syrjälä
Move the "does this modifier support async flips?" check
to be handled by the platform specific plane code instead
of having a big mess in common code.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 9 +++
.../gpu/drm/i915/display/intel_at
From: Ville Syrjälä
Async flips often require bigger alignment that sync flips.
Currently we have HAS_ASYNC_FLIPS() checks strewn about to
inidcate that async flips are generally supported and thus
we want more alignment. Switch that over to using
intel_plane_can_async_flip() so that we can handl
From: Ville Syrjälä
Wa_22011186057 (some CCS problem) only affected ADL A-stepping,
which I presume is pre-production hw. Drop the dead code.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 8
1 file changed, 8 deletions(-)
diff --git a/drivers/g
From: Ville Syrjälä
Move the xe AUX neutering out from skl_get_plane_caps() into the
caller so that it'll be easier to refactor skl_get_plane_caps()
into a more readable shape. This isn't really hardware specific
anyway, and just some kind of bug/misfeature of xe.
Signed-off-by: Ville Syrjälä
-
From: Ville Syrjälä
Looks like CCS + async flips has been a thing for a while now.
Enable this for TGL+ render compression modifiers.
Note that we can't update AUX_DIST during async flips we must
check to make sure it remains unchanged.
We also can't do clear color. Supposedly there was some at
From: Ville Syrjälä
Apparently ICL can do async flips with CCS. In fact it already
seems to work on GLK, but apparently can lead to underruns there
so we'll only enable it for ICL.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 21 +++-
1 file c
From: Ville Syrjälä
Split skl_get_plane_caps() into four variants:
skl_plane_caps(), glk_plane_caps(), icl_plane_caps(),
tgl_plane_caps().
Makes it easier to figure out what is actually going on there.
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/skl_universal_plane.c| 81 +++
From: Ville Syrjälä
Rename vlv_primary_min_alignment() to vlv_plane_min_alignment()
and use it to replace vlv_sprite_min_alignment() since the
behaviour is now identical when the plane init doesn't set up
any async flips stuff.
Technically VLV/CHV sprites do support async flips, so this
also mak
From: Ville Syrjälä
TGL+ should no longer need any VT-d scanout workarounds.
Don't apply any.
Not 100% sure whether pre-SNB might also suffer from this. The
workaround did originate on SNB but who knows if it was just
never caught before that. Not that I ever managed to enable
VT-d any older har
From: Ville Syrjälä
Enable async flips with compressed buffers on icl+, disable
the VT-d scanout workarounds for TGL+, and follow up with
some cleanups to make the code less messy.
Ville Syrjälä (9):
drm/i915: Allow async flips with render compression on TGL+
drm/i915: Allow async flips with
Reviewed-by: Clint Taylor
-Clint
On Tue, 2024-10-08 at 15:37 -0700, Matt Atwood wrote:
> From: Suraj Kandpal
>
> From DISPLAY_VER() >= 30 C20 PHY consolidated programming table of
> DP and eDP been merged and now use the same rates and values. eDP
> over TypeC has also been introduced.
> More
-Original Message-
From: Intel-xe On Behalf Of Imre Deak
Sent: Wednesday, October 9, 2024 12:44 PM
To: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
Subject: [PATCH v2 1/4] drm/i915/dp: Assume panel power is off if runtime
suspended
>
> If the device is runtime suspende
== Series Details ==
Series: drm/i915: Async flip + compression, and some plane cleanups
URL : https://patchwork.freedesktop.org/series/139807/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/inc
== Series Details ==
Series: drm/i915: Async flip + compression, and some plane cleanups
URL : https://patchwork.freedesktop.org/series/139807/
State : warning
== Summary ==
Error: dim checkpatch failed
0842b69545cf drm/i915: Allow async flips with render compression on TGL+
5dc9b779514e drm/i
-Original Message-
From: Intel-gfx On Behalf Of Imre Deak
Sent: Wednesday, October 9, 2024 12:44 PM
To: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
Subject: [PATCH v2 2/4] drm/i915/dp: Disable unnecessary HPD polling for eDP
>
> A registered eDP connector is considered
-Original Message-
From: Intel-gfx On Behalf Of Jouni
Högander
Sent: Wednesday, October 9, 2024 6:42 AM
To: intel-gfx@lists.freedesktop.org
Cc: ville.syrj...@linux.intel.com; jani.nik...@linux.intel.com; Hogander, Jouni
Subject: [PATCH v2 1/2] drm/i915/display: Add own counter for Panel
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/display: Add own counter for
Panel Replay vblank workaround
URL : https://patchwork.freedesktop.org/series/139784/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15505 -> Patchwork_139784v1
===
== Series Details ==
Series: drm/i915/display: Remove kstrdup_const() and kfree_const() usage (rev2)
URL : https://patchwork.freedesktop.org/series/139525/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15508 -> Patchwork_139525v2
===
On 10/4/2024 6:31 AM, Vignesh Raman wrote:
Add job that executes the IGT test suite for sm8350-hdk.
Signed-off-by: Vignesh Raman
---
drivers/gpu/drm/ci/arm64.config | 7 +-
drivers/gpu/drm/ci/build.sh | 1 +
drivers/gpu/drm/ci/test.yml
If the device is runtime suspended the eDP panel power is also off.
Ignore a short HPD on eDP if the device is suspended accordingly,
instead of checking the panel power state via the PPS registers for the
same purpose. The latter involves runtime resuming the device
unnecessarily, in a frequent sc
This is v2 of [1], fixing a failure in igt/kms_pm_rpm/universal-planes
reported by CI.
[1] https://lore.kernel.org/all/20241007140531.1044630-1-imre.d...@intel.com
Cc: Rodrigo Vivi
Cc: Jonathan Cavitt
Imre Deak (4):
drm/i915/dp: Assume panel power is off if runtime suspended
drm/i915/dp: D
A registered eDP connector is considered to be always connected, so it's
unnecessary to poll it for a connect/disconnect event. Polling it
involves AUX accesses toggling the panel power, which in turn can
generate a spurious short HPD pulse and possibly a new poll cycle via
the short HPD handler ru
For clarity separate the d3cold and non-d3cold runtime PM handling. The
only change in behavior is disabling polling later during runtime
resume. This shouldn't make a difference, since the poll disabling is
handled from a work, which could run at any point wrt. the runtime
resume handler. The work
Atm the display HPD interrupts that got disabled during runtime
suspend, are re-enabled only if d3cold is enabled. Fix things by
also re-enabling the interrupts if d3cold is disabled.
Cc: Rodrigo Vivi
Reviewed-by: Jonathan Cavitt
Signed-off-by: Imre Deak
---
drivers/gpu/drm/xe/display/xe_displ
== Series Details ==
Series: drm/i915: remove all IS__GT() macros (rev2)
URL : https://patchwork.freedesktop.org/series/139306/
State : warning
== Summary ==
Error: dim checkpatch failed
a59ec96d4cdd drm/i915: remove all IS__GT() macros
-:135: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915'
== Series Details ==
Series: drm/i915: remove all IS__GT() macros (rev2)
URL : https://patchwork.freedesktop.org/series/139306/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
Hi Nitin,
On Thu, Oct 03, 2024 at 07:40:44PM +0530, Nitin Gote wrote:
> From: Chris Wilson
>
> On Haswell, in particular, we see an issue where resets fails because
> the engine resumes from an incorrect RING_HEAD. Since the RING_HEAD
> doesn't point to the remaining requests to re-run, but may
On Wed, Oct 09, 2024 at 10:53:56AM +0300, Jani Nikula wrote:
> On Tue, 08 Oct 2024, Matt Atwood wrote:
> > From: Suraj Kandpal
> >
> > Read PICA register to see if edp over type C is possible and then
> > add the appropriate tables for it.
>
> There's clearly more to be done for the feature than
On Wed, Oct 09, 2024 at 10:57:03AM +0300, Jani Nikula wrote:
> On Tue, 08 Oct 2024, Matt Atwood wrote:
> > From: Suraj Kandpal
> >
> > Add condition for P2.PG power down value.
> >
> > Bspec: 74494
> > Signed-off-by: Suraj Kandpal
> > Signed-off-by: Matt Atwood
> > ---
> > drivers/gpu/drm/i915
== Series Details ==
Series: drm/i915/dmc: Add dmc null check
URL : https://patchwork.freedesktop.org/series/139751/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15496 -> Patchwork_139751v1
Summary
---
**SUCCESS**
> -Original Message-
> From: Ville Syrjälä
> Sent: Wednesday, October 9, 2024 1:01 PM
> To: Golani, Mitulkumar Ajitkumar
> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani ;
> Syrjala, Ville ; Nautiyal, Ankit K
> ; Shankar, Uma
> Subject: Re: [PATCH v13 3/3] drm/i915/panelreplay: Pan
> -Original Message-
> From: Ville Syrjälä
> Sent: Wednesday, October 9, 2024 12:55 PM
> To: Golani, Mitulkumar Ajitkumar
> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani ;
> Syrjala, Ville ; Nautiyal, Ankit K
> ; Shankar, Uma
> Subject: Re: [PATCH v13 1/3] drm/i915/vrr: Add helper
In order to avoid having userspace to use MI_MEM_FENCE,
we are adding a mechanism for userspace to generate a
PCI memory barrier with low overhead (avoiding IOCTL call).
This is implemented by memory-mapping a page as uncached
that is backed by MMIO on the dGPU and thus allowing userspace
to do me
On Wed, 09 Oct 2024, Suraj Kandpal wrote:
> Fix the DSC flag assignment based on the dsc_slice_count returned
> to avoid divide by zero error.
>
> Fixes: 4e0837a8d00a ("drm/i915/dp_mst: Account for FEC and DSC overhead
> during BW allocation")
> Signed-off-by: Suraj Kandpal
> ---
> drivers/gpu/
On 09-10-2024 13:05, Vivekanandan, Balasubramani wrote:
On 26.09.2024 10:52, Pottumuttu, Sai Teja wrote:
On 25-09-2024 19:33, Ville Syrjälä wrote:
On Wed, Sep 25, 2024 at 04:48:02PM +0530, Sai Teja Pottumuttu wrote:
Underrun recovery was defeatured and was never brought into usage.
Thus we c
Please ignore this patch, sent by mistake to wrong mailing list.
Thanks,
Tejas
> -Original Message-
> From: Upadhyay, Tejas
> Sent: Wednesday, October 9, 2024 3:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Upadhyay, Tejas
> Subject: [PATCH] drm/xe/mmap: Add mmap support for PCI mem
== Series Details ==
Series: drm/i915/cdclk: Check cdclk value before division
URL : https://patchwork.freedesktop.org/series/139760/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15498 -> Patchwork_139760v1
Summary
---
ry.h:617)
[ 12.756757][ T116] ? drm_mode_copy
(kbuild/src/consumer/drivers/gpu/drm/drm_modes.c:1422) drm
The kernel config and materials to reproduce are available at:
https://download.01.org/0day-ci/archive/20241009/202410091649.1353a717-oliver.s...@intel.com
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
On Wed, 09 Oct 2024, Jouni Högander wrote:
> We are about to change meaning of vblank_enabled to fix Panel Replay vblank
> workaround. For sake of clarity we need to rename it. Vblank_enabled is
> used for i915gm/i945gm vblank irq workaround as well -> instead of rename
> add new counter named as
On Wed, Oct 09, 2024 at 08:46:20AM +, Kandpal, Suraj wrote:
>
>
> > -Original Message-
> > From: Ville Syrjälä
> > Sent: Wednesday, October 9, 2024 12:25 PM
> > To: Kandpal, Suraj
> > Cc: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org;
> > Shankar,
> > Uma ; Borah,
On Tue, 2024-10-08 at 15:37 -0700, Matt Atwood wrote:
> From: Matt Roper
>
> Xe3's power well handling is similar to previous platforms, but there
> are a few changes that need to be handled to ensure optimal power
> management:
> - PGB now only depends on PG1, not PG2
> - Transcoder B is now i
== Series Details ==
Series: drm/i915/color: Use correct variable to load lut
URL : https://patchwork.freedesktop.org/series/139749/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15496 -> Patchwork_139749v1
Summary
---
On Tue, 08 Oct 2024, Matt Atwood wrote:
> From: Suraj Kandpal
>
> DISPLAY_VER() >= 30 has the HDCP_LINE_REKEY bit redefined from
> bit 12 to bit 14. Create a macro to choose the correct bit based
> on DISPLAY_VER().
>
> Signed-off-by: Suraj Kandpal
> Signed-off-by: Matt Atwood
> ---
> drivers/
On Tue, 08 Oct 2024, Matt Atwood wrote:
> From: Suraj Kandpal
>
> Read PICA register to see if edp over type C is possible and then
> add the appropriate tables for it.
There's clearly more to be done for the feature than this.
>
> Bspec: 68846
> Signed-off-by: Suraj Kandpal
> Signed-off-by: M
On Wed, 09 Oct 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Now that we use the gen3 codepaths also for gen2
> rename everything to gen2_ to match.
This was fine for the gt stuff where there are gen5 and gen6 functions,
but should we just call these something more generic since there are
On Mon, 07 Oct 2024, Luca Coelho wrote:
> This is causing a regression since 6.12-rc1. We are getting the
> following error messages when running flip-vs-suspend* tests:
>
> [222.857770] =
> [222.857771] [ BUG: Invalid wait context ]
> [222.857772] 6.12.0-rc1-xe #1 Not
We want to make sure that direct mmap mapping of physical
page at doorbell space and whole page is accessible in order
to use pci memory barrier effect effectively.
This is basic pci memory barrier test to showcase xe driver
support for feature. In follow up patches we will have more
of corner and
On Tue, Oct 08, 2024 at 08:24:42PM +0300, Jani Nikula wrote:
> On Mon, 07 Oct 2024, Raag Jadav wrote:
> > Host BIOS doesn't enable G8 power mode due to an issue on DG2, so we
> > enable it from kernel with Wa_14022698589. Currently it is enabled for
> > all DG2 devices with the exception of a few,
> -Original Message-
> From: Ville Syrjälä
> Sent: Wednesday, October 9, 2024 12:25 PM
> To: Kandpal, Suraj
> Cc: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; Shankar,
> Uma ; Borah, Chaitanya Kumar
>
> Subject: Re: [PATCH] drm/i915/color: Use correct variable to l
Check cdclk value to avoid a divide by zero error. Since
bxt_cdclk_init_hw has cdclk can end up being 0 and then
we have a call to bxt_set_cdclk where we may end up dividing
this value by 0.
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
1 file changed, 1 ins
On Tue, Oct 01, 2024 at 07:17:01PM +0530, Mitul Golani wrote:
> Add helper to check if vrr is possible based on flipline
> is computed.
>
> Signed-off-by: Mitul Golani
> ---
> drivers/gpu/drm/i915/display/intel_vrr.c | 7 ++-
> drivers/gpu/drm/i915/display/intel_vrr.h | 1 +
> 2 files change
On Wed, 09 Oct 2024, Suraj Kandpal wrote:
> Move dig_port assignment much lower in the sequence to avoid NULL
> pointer deference in case encoder is not present.
Please describe the case exactly. Is this real or a static analyzer
warning?
I see there's commit 6c63e6e14da7 ("drm/i915/hdcp: No HDC
On Wed, 09 Oct 2024, Raag Jadav wrote:
> On Tue, Oct 08, 2024 at 08:24:42PM +0300, Jani Nikula wrote:
>> On Mon, 07 Oct 2024, Raag Jadav wrote:
>> > Host BIOS doesn't enable G8 power mode due to an issue on DG2, so we
>> > enable it from kernel with Wa_14022698589. Currently it is enabled for
>>
Hi Matt,
Probably you missed one change...
On Tue, 2024-10-08 at 15:37 -0700, Matt Atwood wrote:
> From: Matt Roper
>
> There are some minor changes to pmdemand handling on Xe3:
> - Active scalers are no longer tracked. We can simply skip the readout
> and programming of this field.
> - A
> -Original Message-
> From: Cavitt, Jonathan
> Sent: Tuesday, October 1, 2024 7:40 PM
> To: Golani, Mitulkumar Ajitkumar ;
> intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani ; Syrjala, Ville
> ;
> Nautiyal, Ankit K ; Shankar, Uma
> ; Cavitt, Jonathan
> Subject: RE: [PATCH v13 2/3]
> -Original Message-
> From: Cavitt, Jonathan
> Sent: Tuesday, October 1, 2024 8:37 PM
> To: Golani, Mitulkumar Ajitkumar ;
> intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani ; Syrjala, Ville
> ;
> Nautiyal, Ankit K ; Shankar, Uma
> ; Cavitt, Jonathan
> Subject: RE: [PATCH v13 3/3]
On Wed, 09 Oct 2024, Suraj Kandpal wrote:
> Add dmc null check before dereferncing to get the major and minor
> version.
>
> Signed-off-by: Suraj Kandpal
> ---
> drivers/gpu/drm/i915/display/intel_dmc.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm
== Series Details ==
Series: drm/i915: Allow fastset for change in HDR infoframe (rev2)
URL : https://patchwork.freedesktop.org/series/139293/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15498 -> Patchwork_139293v2
Summar
> -Original Message-
> From: Jani Nikula
> Sent: Wednesday, October 9, 2024 3:30 PM
> To: Kandpal, Suraj ; intel-
> x...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K ; Kandpal, Suraj
>
> Subject: Re: [PATCH] drm/i915/dp_mst: Fix dsc mst bw overhead cal
> -Original Message-
> From: Jani Nikula
> Sent: Wednesday, October 9, 2024 3:01 PM
> To: Kandpal, Suraj ; intel-
> x...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Shankar, Uma ; Borah, Chaitanya Kumar
> ; Kandpal, Suraj
>
> Subject: Re: [PATCH] drm/i915/dmc: Add dmc
Hi,
On Tue, 8 Oct 2024, Vinod Govindapillai wrote:
> For a pipe configuration, if no supported audio frequencies are
> found, then start reducing the audio channels and try assess the
> sad audio frequency list again.
s/iterare/iterate/ in patch subject, but otherwise looks good. For this
patch:
Hi,
On Tue, 8 Oct 2024, Vinod Govindapillai wrote:
> Update the reference overhaed values for audio bw calculations
> for MTL onwards
s/overhaed/overhead/ , otherwise looks good:
Reviewed-by: Kai Vehmanen
Br, Kai
Hi,
On Tue, 8 Oct 2024, Vinod Govindapillai wrote:
> After pruning the sad audio frequency list, if there are no
> supported audio frequencies left, audio cannot be supported.
> So mark has_audio accordingly.
[...]
> @@ -823,9 +824,13 @@ bool intel_audio_compute_eld_config(struct
> drm_connector
We are about to change meaning of vblank_enabled to fix Panel Replay vblank
workaround. For sake of clarity we need to rename it. Vblank_enabled is
used for i915gm/i945gm vblank irq workaround as well -> instead of rename
add new counter named as vblank_wa_pipes.
v2:
- s/vblank_wa_pipes/vblank_w
Currently workaround is not applied when vblank is enabled on crtc that
needs the workaround if vblank is already enabled for another crtc that
doesn't need the workaround. Fix this by increasing counter only if crtc
needs the workaround.
Fixes: aa451abcffb5 ("drm/i915/display: Prevent DC6 while v
== Series Details ==
Series: series starting with [1/2] drm/i915/dp_mst: Handle error during DSC BW
overhead/slice calculation
URL : https://patchwork.freedesktop.org/series/139771/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15502 -> Patchwork_139771v1
Quoting Govindapillai, Vinod (2024-10-09 10:09:45-03:00)
>Hi Matt,
>
>Probably you missed one change...
>
>On Tue, 2024-10-08 at 15:37 -0700, Matt Atwood wrote:
>> From: Matt Roper
>>
>> There are some minor changes to pmdemand handling on Xe3:
>> - Active scalers are no longer tracked. We can
On 26.09.2024 10:52, Pottumuttu, Sai Teja wrote:
>
> On 25-09-2024 19:33, Ville Syrjälä wrote:
> > On Wed, Sep 25, 2024 at 04:48:02PM +0530, Sai Teja Pottumuttu wrote:
> > > Underrun recovery was defeatured and was never brought into usage.
> > > Thus we can safely remove the interrupt register bi
== Series Details ==
Series: drm/i915/hdcp: Move dig_port assignment lower in the sequence
URL : https://patchwork.freedesktop.org/series/139744/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15496 -> Patchwork_139744v1
Sum
On Wed, 09 Oct 2024, Kamil Konieczny wrote:
> Hi Tejas,
> On 2024-10-09 at 15:26:08 +0530, Tejas Upadhyay wrote:
>> We want to make sure that direct mmap mapping of physical
>> page at doorbell space and whole page is accessible in order
>> to use pci memory barrier effect effectively.
>>
>> This
Hi Tejas,
On 2024-10-09 at 15:26:08 +0530, Tejas Upadhyay wrote:
> We want to make sure that direct mmap mapping of physical
> page at doorbell space and whole page is accessible in order
> to use pci memory barrier effect effectively.
>
> This is basic pci memory barrier test to showcase xe drive
== Series Details ==
Series: drm/xe/mmap: Add mmap support for PCI memory barrier
URL : https://patchwork.freedesktop.org/series/139768/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15498 -> Patchwork_139768v1
Summary
On Tue, 2024-10-08 at 15:37 -0700, Matt Atwood wrote:
> From: Matt Roper
>
> Xe3 makes a couple minor tweaks to the watermark algorithm's block count
> calculations.
>
> Bspec: 68985
> Signed-off-by: Matt Roper
> Signed-off-by: Matt Atwood
> ---
> drivers/gpu/drm/i915/display/skl_watermark.c
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