On Thu, 19 Sep 2024, Ville Syrjälä wrote:
> On Thu, Sep 19, 2024 at 12:04:27PM +0300, Jani Nikula wrote:
>> The intel_pps_reset_all() function does similar but not quite the same
>> things for VLV/CHV and BXT/GLK. Observe that it's called from platform
>> specific code only, and a split to two fun
Hi
Am 23.09.24 um 08:37 schrieb Borah, Chaitanya Kumar:
Hello Alexander,
We have two gitlab issues[1] where a phantom display is detected by the system
(with i915 driver).
The following patch[2] has been identified as the first bad commit after bisect.
"b49420d6a1 video/aperture: optionally m
On Fri, 20 Sep 2024, Ville Syrjälä wrote:
> On Thu, Sep 12, 2024 at 03:15:52PM +0300, Jani Nikula wrote:
>> On Tue, 10 Sep 2024, Ville Syrjala wrote:
>> > From: Ville Syrjälä
>> >
>> > Replace the three hand rolled "$VBT"s with a vbt_signature[]
>> > to avoid accidents.
>> >
>> > Signed-off-by:
On Fri, 20 Sep 2024, Ville Syrjälä wrote:
> On Thu, Sep 12, 2024 at 03:44:32PM +0300, Jani Nikula wrote:
>> Just nitpicking, but should this (and rom reads above) now sanity check
>> offset+size against rom->size? IDK if it's worth it for such a simple
>> thing. The caller is supposed to know what
On Thu, 12 Sep 2024, "Murthy, Arun R" wrote:
>> -Original Message-
>> From: Jani Nikula
>> Sent: Thursday, September 12, 2024 2:32 PM
>> To: Murthy, Arun R ; intel...@lists.freedesktop.org;
>> intel-gfx@lists.freedesktop.org
>> Cc: Murthy, Arun R ; Srikanth V, NagaVenkata
>>
>> Subject:
> > On Fri, 2024-09-20 at 14:42 +0530, Suraj Kandpal wrote:
> > > To reach PC10 when PKG_C_LATENCY is configure we must do the
> > following
> > > things
> > > 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be
> > > entered
> > > 2) Allow PSR2 deep sleep when DC5 can be entered
> >
On Thu, 12 Sep 2024, Arun R Murthy wrote:
> Aux RD Interval value depends on the value read from the dpcd register
> which is updated from the sink device use flseep thereby we adhere to
> the Documentation/timers/timers-howto.rst
>
> Signed-off-by: Srikanth V NagaVenkata
> Signed-off-by: Arun R
On Thu, 12 Sep 2024, "Murthy, Arun R" wrote:
>> -Original Message-
>> From: Jani Nikula
>> Sent: Thursday, September 12, 2024 2:36 PM
>> To: Murthy, Arun R ; intel...@lists.freedesktop.org;
>> intel-gfx@lists.freedesktop.org
>> Cc: Murthy, Arun R ; Srikanth V, NagaVenkata
>>
>> Subject:
> -Original Message-
> From: Intel-xe On Behalf Of
> Chaitanya Kumar Borah
> Sent: Monday, September 23, 2024 10:22 AM
> To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
> Subject: [PATCH] drm/i915/dp: Add FEC Enable Retry mechanism
>
> From PTL, FEC_DECODE_EN sequen
On Mon, 16 Sep 2024, Alexander Usyskin wrote:
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 39f6614a0a99..b9d4f9be5355 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -34,6 +34,8 @@
>
> #include
>
> +#incl
> Subject: Re: [PATCH v6 08/12] drm/i915/spi: add spi device for discrete
> graphics
>
> On Mon, 16 Sep 2024, Alexander Usyskin
> wrote:
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> > index 39f6614a0a99..b9d4f9be5355 100644
> > --- a/drivers/gpu/drm/i915/
On Mon, 23 Sep 2024, "Srikanth V, NagaVenkata"
wrote:
>> > -Original Message-
>> > From: Intel-xe On Behalf Of
>> > Arun R Murthy
>> > Sent: Thursday, September 12, 2024 10:36 AM
>> > To: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
>> > Cc: Murthy, Arun R ; Srikanth V
On Sat, Sep 21, 2024 at 01:00:52PM +, Winkler, Tomas wrote:
> > On Thu, Sep 19, 2024 at 09:54:24AM +, Winkler, Tomas wrote:
> > > > On Mon, Sep 16, 2024 at 04:49:17PM +0300, Alexander Usyskin wrote:
> > Just do normal open coded allocations, the reference counting is just
> > obscure.
> T
On Mon, Sep 23, 2024 at 01:24:27PM +0300, Jani Nikula wrote:
> On Thu, 12 Sep 2024, Arun R Murthy wrote:
> > Aux RD Interval value depends on the value read from the dpcd register
> > which is updated from the sink device use flseep thereby we adhere to
> > the Documentation/timers/timers-howto.rs
On Mon, Sep 23, 2024 at 09:28:23AM +0530, Raag Jadav wrote:
> Introduce device wedged event, which will notify userspace of wedged
> (hanged/unusable) state of the DRM device through a uevent. This is
> useful especially in cases where the device is no longer operating as
> expected and has become
On 21/09/2024 14:00, Winkler, Tomas wrote:
On Thu, Sep 19, 2024 at 09:54:24AM +, Winkler, Tomas wrote:
On Mon, Sep 16, 2024 at 04:49:17PM +0300, Alexander Usyskin wrote:
@@ -0,0 +1,142 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright(c) 2019-2024, Intel Corporation. All rig
From: Ville Syrjälä
Unify the behaviour of the PCI ROM vs. SPI flash VBT
read codepaths, and relocate out the low level nuts details
from intel_bios.c into a new soc/intel_rom.c file.
v2: Sort out the drm_dbg() vs. drm_dbg_kms() mess
Include terminating '\0' in vbt_signature[]
Drop an un
From: Ville Syrjälä
Replace the few oddball drm_dbg() calls in VBT related code
with drm_dbg_kms() as that is what we generally use for all
display code.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bios.c | 22 +++---
1 file changed, 11 insertions(+), 11
From: Ville Syrjälä
Abstract away the nuts and bolts of the SPI vs. PCI ROM
stuff, and hide it all in soc/intel_rom.c so that the
VBT code doesn't have to care about this stuff.
This leaves intel_bios.c with a single codepath that
can focus on the details related to the VBT layout.
This should
From: Ville Syrjälä
Replace the three hand rolled "$VBT"s with a vbt_signature[]
to avoid accidents.
v2: Include terminating '\0' for safety (Jani)
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bios.c | 15 ---
1 file changed, 12 ins
From: Ville Syrjälä
The SPI VBT codepath only knows how to read 4 bytes at a time.
So to read the 2 byte vbt_size it masks out the unwanted msbs.
Hide that little implementation detail inside a new intel_spi_read16()
helper. Alse rename the existing intel_spi_read() to intel_spi_read32()
to make
From: Ville Syrjälä
Unify the SPI vs. PCI ROM VBT read codepaths a bit by
pulling some size overflow checks from the PCI side
into the SPI side.
v2: s/drm_dbg()/drm_dbg_kms()/
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bios.c | 11 +++
From: Ville Syrjälä
The SPI code rounds the VBT allocation to a multiple of four bytes
(presumably because it reads the VBT 4 bytes at a time). Do the
same for the PCI ROM side to eliminate pointless differences between
the two codepaths. This will make no functional difference.
Reviewed-by: Jan
Quoting Matt Roper (2024-09-18 19:49:27-03:00)
>On Thu, Aug 29, 2024 at 07:00:47PM -0300, Gustavo Sousa wrote:
>> Tracepoints that display frame and scanline counters for all pipes were
>> added with commit 1489bba82433 ("drm/i915: Add cxsr toggle tracepoint")
>> and commit 0b2599a43ca9 ("drm/i915:
On Mon, Sep 23, 2024 at 08:38:35PM +0300, Ville Syrjälä wrote:
> On Mon, Sep 23, 2024 at 08:40:07AM +0530, Suraj Kandpal wrote:
> > Reduce SHPD_CNT to 250us for display version 12 as it lines up
> > with DP1.4a(Table3-4) spec.
> >
> > --v2
> > -Update commit message and comment [Matt]
> >
> > Sig
On Sun, Sep 22, 2024 at 10:40:32AM +, Govindapillai, Vinod wrote:
> On Mon, 2024-09-16 at 19:24 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > As with other watermark calculations, the dodgy pre-g4x
> > update_wm_{pre,post} flag calcultion would like to know
> Typo: calculation
>
On Mon, Sep 23, 2024 at 08:40:07AM +0530, Suraj Kandpal wrote:
> Reduce SHPD_CNT to 250us for display version 12 as it lines up
> with DP1.4a(Table3-4) spec.
>
> --v2
> -Update commit message and comment [Matt]
>
> Signed-off-by: Suraj Kandpal
> ---
> drivers/gpu/drm/i915/display/intel_hotplug_
On Sun, Sep 22, 2024 at 10:34:07AM +, Govindapillai, Vinod wrote:
> On Sun, 2024-09-22 at 12:54 +0300, Govindapillai, Vinod wrote:
> > On Mon, 2024-09-16 at 19:24 +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > intel_wm_need_update() is a mess when it comes to variable
> > >
On Mon, Sep 23, 2024 at 08:38:35PM +0300, Ville Syrjälä wrote:
> On Mon, Sep 23, 2024 at 08:40:07AM +0530, Suraj Kandpal wrote:
> > Reduce SHPD_CNT to 250us for display version 12 as it lines up
> > with DP1.4a(Table3-4) spec.
> >
> > --v2
> > -Update commit message and comment [Matt]
> >
> > Sig
Add a helper to compute the number of pipes required.
This will depend on whether the joiner is required or is forced through
the debugfs. If no joiner is required the helper returns 1.
v2:
-Return 1 if no joiner is required. (Ville)
-Change the suffix from joined_pipes to num_pipes. (Ville)
-Use
Currently debugfs for joiner can take a value of 0->dont care and
2->join 2 pipes. Add option to force to use only 1 pipe.
If debugfs is set to 1, force to exactly one pipe (ie. no
joiner despite what the automagic logic is saying).
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display
From: Stanislav Lisovskiy
Ultrajoiner mode has some new bits and states to be
read out from the hw. Lets make changes accordingly.
v2: Fix checkpatch warnings. (Ankit)
v3: Add separate functions for computing expected secondary_big/ultrajoiner
pipes. (Ankit)
v4:
-Streamline the helpers for ultra
Allow forcing ultrajoiner through debugfs.
v2: Minor refactoring of switch case logic. (Ville)
Signed-off-by: Ankit Nautiyal
Reviewed-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/disp
Currently we support joiner only for DP encoder.
Do not create the debugfs for joiner if DP does not support the joiner.
This will also help avoiding cases where config has eDP MSO, with which
we do not support joiner.
v2: Check for intel_dp_has_joiner and avoid creating debugfs if not
supported.
This patch series attempts to implement basic support
for Ultrajoiner functionality.
Rev6:
-Upgrade the debugfs functionality to enable the joining of a
specified number of pipes.
-Modify the display helpers reliant on the pipe joiner mechanism
to use number of pipes joined, instead of joiner flag
At the moment, the debugfs for joiner allows only to force enable/disable
pipe joiner for 2 pipes. Modify it to force join 'n' number of pipes,
where n is a valid pipe joiner configuration.
This will help in case of ultra joiner where 4 pipes are joined.
v2:
-Fix commit message to state that only
Bigjoiner needs DSC, add a check to reflect that.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_display_device.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
b/drivers/gpu/drm/i915/display/intel_di
From: Stanislav Lisovskiy
Add changes to DSC which are required for Ultrajoiner.
v2:
-Use correct helper for setting bits for bigjoiner secondary. (Ankit)
-Use primary/secondary instead of master/slave. (Suraj)
v3: Add the ultrajoiner helpers and use it for setting ultrajoiner
bits (Ankit)
v4: U
Pass the current pipe into enabled_joiner_pipes(), and let it figure out
the proper bitmasks for us.
v2:
-Simplify helper get_joiner_primary_pipes. (Ville)
-Nuke get_joiner_secondary_pipes. (Ville)
-Add more drm_WARNs and checks for final primary/secondary pipes.
(Ville)
Signed-off-by: Ankit Naut
From: Stanislav Lisovskiy
Add sanity checks for primary and secondary bigjoiner/uncompressed
bitmasks, should make it easier to spot possible issues.
v2:
-Streamline the expected masks and add few more drm_WARNs. (Ville)
-Use %#x format specifier for printing joiner masks. (Ville)
-Use struct in
We need to add a new sanity checks and also do
some preparations for adding ultrajoiner hw state readout.
Lets first split reading of the uncompressed joiner and bigjoiner
bit masks into separate functions.
v2: Fixed checkpatch warnings (Ankit)
v3: Use struct intel_display in the new functions. (A
Add compressed bpp limitations for ultrajoiner.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 24 ++--
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp
From: Stanislav Lisovskiy
Implement required changes for mode validation and compute config,
to support Ultrajoiner.
v2:
-Drop changes for HDMI.
-Separate out DSC changes into another patch.
v3: Fix check in can_ultrajoiner. (Ankit)
v4:
-Unify helper to check joiner requirement. (Ville)
-Split p
Use the check for ultrajoiner while computing maxdotclock.
v2: Add Check for HAS_UNCOMPRESSED_JOINER. (Ville)
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_display.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/int
From: Stanislav Lisovskiy
ultrajoiner needs 2 bigjoiners to be enabled, so modify the helper
intel_dp_dsc_get_slice_count for ultrajoiner.
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 7 +--
1 file changed, 5 insertions(+),
Add macro to check if platform supports Ultrajoiner.
v2:
-Use check for DISPLAY_VER >= 20, and add bmg as a special case. (Ville)
-Add check for HAS_DSC. (Ville)
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_display_device.h | 3 +++
1 file changed, 3 insertions(+)
diff
On Mon, Sep 23, 2024 at 11:09:19AM -0700, Matt Roper wrote:
> On Mon, Sep 23, 2024 at 08:38:35PM +0300, Ville Syrjälä wrote:
> > On Mon, Sep 23, 2024 at 08:40:07AM +0530, Suraj Kandpal wrote:
> > > Reduce SHPD_CNT to 250us for display version 12 as it lines up
> > > with DP1.4a(Table3-4) spec.
> >
On Mon, Sep 23, 2024 at 11:43:21PM +0530, Ankit Nautiyal wrote:
> Bigjoiner needs DSC, add a check to reflect that.
Might want to point out here that DSC can be fused off, hence
the platform check itself is not sufficient.
Reviewed-by: Ville Syrjälä
>
> Signed-off-by: Ankit Nautiyal
> ---
>
Add compressed bpp limitations for ultrajoiner.
v2: Fix the case for 1 pipe. (Ankit)
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 27 +++--
1 file changed, 21 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
On Mon, Sep 23, 2024 at 11:43:22PM +0530, Ankit Nautiyal wrote:
> Currently we support joiner only for DP encoder.
> Do not create the debugfs for joiner if DP does not support the joiner.
> This will also help avoiding cases where config has eDP MSO, with which
> we do not support joiner.
>
> v2:
On Mon, Sep 23, 2024 at 11:43:23PM +0530, Ankit Nautiyal wrote:
> At the moment, the debugfs for joiner allows only to force enable/disable
> pipe joiner for 2 pipes. Modify it to force join 'n' number of pipes,
> where n is a valid pipe joiner configuration.
> This will help in case of ultra joine
On Mon, Sep 23, 2024 at 11:43:25PM +0530, Ankit Nautiyal wrote:
> Currently debugfs for joiner can take a value of 0->dont care and
> 2->join 2 pipes. Add option to force to use only 1 pipe.
>
> If debugfs is set to 1, force to exactly one pipe (ie. no
> joiner despite what the automagic logic is
On Mon, Sep 23, 2024 at 11:43:28PM +0530, Ankit Nautiyal wrote:
> Add macro to check if platform supports Ultrajoiner.
>
> v2:
> -Use check for DISPLAY_VER >= 20, and add bmg as a special case. (Ville)
> -Add check for HAS_DSC. (Ville)
>
> Signed-off-by: Ankit Nautiyal
Reviewed-by: Ville Syrjäl
On Mon, 23 Sep 2024, Chaitanya Kumar Borah
wrote:
> From PTL, FEC_DECODE_EN sequence can be sent to a DPRX independent
> of TRANS_CONF enable. This allows us to re-issue an FEC_DECODE_EN
> sequence without re-doing the whole mode set sequence. This separate
> control over FEC_ECODE_EN/DIS sequenc
On Fri, 20 Sep 2024, Ville Syrjälä wrote:
> On Fri, Sep 20, 2024 at 02:56:42PM +0300, Jani Nikula wrote:
>> Whenever I look at doing anything in intel_dp.c I think it's grown too
>> big. It's over 7k lines.
>>
>> The DP test functionality is fairly isolated, and mostly irrelevant for
>> normal op
On Thu, 19 Sep 2024, Ville Syrjälä wrote:
> On Thu, Sep 19, 2024 at 06:33:54PM +0300, Jani Nikula wrote:
>> The array can be in rodate, make it const.
>>
>> Signed-off-by: Jani Nikula
>
> Reviewed-by: Ville Syrjälä
Thanks, pushed to din.
BR,
Jani.
>
>> ---
>> drivers/gpu/drm/i915/display/in
On Mon, 23 Sep 2024, Francois Dugast wrote:
> On Mon, Sep 23, 2024 at 01:24:27PM +0300, Jani Nikula wrote:
>> On Thu, 12 Sep 2024, Arun R Murthy wrote:
>> > Aux RD Interval value depends on the value read from the dpcd register
>> > which is updated from the sink device use flseep thereby we adhe
On Mon, Sep 23, 2024 at 12:12:39PM +0300, Jani Nikula wrote:
> On Fri, 20 Sep 2024, Ville Syrjälä wrote:
> > On Thu, Sep 12, 2024 at 03:15:52PM +0300, Jani Nikula wrote:
> >> On Tue, 10 Sep 2024, Ville Syrjala wrote:
> >> > From: Ville Syrjälä
> >> >
> >> > Replace the three hand rolled "$VBT"s
On Mon, 23 Sep 2024, Ville Syrjälä wrote:
> On Mon, Sep 23, 2024 at 12:12:39PM +0300, Jani Nikula wrote:
>> On Fri, 20 Sep 2024, Ville Syrjälä wrote:
>> > On Thu, Sep 12, 2024 at 03:15:52PM +0300, Jani Nikula wrote:
>> >> On Tue, 10 Sep 2024, Ville Syrjala wrote:
>> >> > From: Ville Syrjälä
>>
Quoting Matt Roper (2024-09-18 19:37:35-03:00)
>On Thu, Aug 29, 2024 at 07:00:45PM -0300, Gustavo Sousa wrote:
>> The first part[1] of the LWN series on using TRACE_EVENT() mentions
>> about TP_printk():
>>
>> "Do not create new tracepoint-specific helpers, because that will
>> confuse use
On Mon, Sep 23, 2024 at 05:24:46PM +0300, Jani Nikula wrote:
> On Mon, 23 Sep 2024, Ville Syrjälä wrote:
> > On Mon, Sep 23, 2024 at 12:12:39PM +0300, Jani Nikula wrote:
> >> On Fri, 20 Sep 2024, Ville Syrjälä wrote:
> >> > On Thu, Sep 12, 2024 at 03:15:52PM +0300, Jani Nikula wrote:
> >> >> On T
On Mon, Sep 23, 2024 at 11:38:55AM +0300, Andy Shevchenko wrote:
> On Mon, Sep 23, 2024 at 09:28:23AM +0530, Raag Jadav wrote:
> > Introduce device wedged event, which will notify userspace of wedged
> > (hanged/unusable) state of the DRM device through a uevent. This is
> > useful especially in ca
On Wed, Sep 18, 2024 at 05:44:39PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We don't use the block size information for the clear color
> plane. Technically the entire fb is the single block for the
> single 64B clear color surface, so there is just no way to
> delcare that as a cons
On Mon, Sep 23, 2024 at 05:35:23PM +0300, Raag Jadav wrote:
> On Mon, Sep 23, 2024 at 11:38:55AM +0300, Andy Shevchenko wrote:
> > On Mon, Sep 23, 2024 at 09:28:23AM +0530, Raag Jadav wrote:
...
> > > +extern const char *const wedge_recovery_opts[];
> >
> > It's not NULL terminated. How users wi
In DP alt mode, when pin assignment is D, only one PHY lane is owned
by the display. intel_cx0pll_enable currently performs a power cycle
ready on both the lanes in all cases.
Address the todo to perfom power state ready on owned lanes.
Tested on Meteor Lake-P [Intel Arc Graphics] with DP alt mod
[why]
How we determine the dsc_aux used for dsc decompression in
drm_dp_mst_dsc_aux_for_port() today having some defects:
1. The method how we determine a connected peer device is virtual or not
in drm_dp_mst_is_virtual_dpcd() is not always correct. There are DP1.4
products
in the market wh
In DP alt mode, when pin assignment is D, only one PHY lane is owned
by the display. intel_cx0pll_enable currently performs a power state
ready on both the lanes in all cases.
Address the todo to perfom power state ready on owned lanes.
Tested on Meteor Lake-P [Intel Arc Graphics] with DP alt mod
In DP alt mode, when pin assignment is D, only one PHY lane is owned
by the display. intel_cx0pll_enable currently performs a power state
ready on both the lanes in all cases.
Address the todo to perfom power state ready on owned lanes.
Tested on Meteor Lake-P [Intel Arc Graphics] with DP alt mod
To ensure code clarity and prevent potential errors, it's advisable
to employ the ';' as a statement separator, except when ',' are
intentionally used for specific purposes.
Signed-off-by: Shen Lichuan
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 4 ++--
1 file changed, 2 insertions(+), 2 del
On Wed, 18 Sep 2024, Ville Syrjälä wrote:
> On Wed, Sep 18, 2024 at 05:50:42PM +0300, Jani Nikula wrote:
>> diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c
>> b/drivers/gpu/drm/i915/soc/intel_pch.c
>> index 542eea50093c..f7e3745bb1dc 100644
>> --- a/drivers/gpu/drm/i915/soc/intel_pch.c
>> +++ b
On Thu, 12 Sep 2024, Arun R Murthy wrote:
> DP Source should be reading AUX_RD interval after we get adjusted
> TX_FFE_PRESET_VALUE from the DP Sink. (before actually adjusting
> in DP Source)
I don't think that's correct. See below.
> Signed-off-by: Srikanth V NagaVenkata
> Signed-off-by: Arun
On Mon, Sep 23, 2024 at 05:06:00PM -0300, Gustavo Sousa wrote:
> Quoting Ville Syrjälä (2024-09-23 16:23:27-03:00)
> >On Mon, Sep 23, 2024 at 04:02:54PM -0300, Gustavo Sousa wrote:
> >> Tracepoints that display frame and scanline counters for all pipes were
> >> added with commit 1489bba82433 ("drm
Quoting Gustavo Sousa (2024-09-23 17:47:08-03:00)
>Quoting Ville Syrjälä (2024-09-23 17:18:39-03:00)
>>On Mon, Sep 23, 2024 at 05:06:00PM -0300, Gustavo Sousa wrote:
>>> Quoting Ville Syrjälä (2024-09-23 16:23:27-03:00)
>>> >On Mon, Sep 23, 2024 at 04:02:54PM -0300, Gustavo Sousa wrote:
>>> >> Trac
Quoting Ville Syrjälä (2024-09-23 17:18:39-03:00)
>On Mon, Sep 23, 2024 at 05:06:00PM -0300, Gustavo Sousa wrote:
>> Quoting Ville Syrjälä (2024-09-23 16:23:27-03:00)
>> >On Mon, Sep 23, 2024 at 04:02:54PM -0300, Gustavo Sousa wrote:
>> >> Tracepoints that display frame and scanline counters for al
On Sun, Sep 22, 2024 at 09:31:10AM +, Govindapillai, Vinod wrote:
> On Mon, 2024-09-16 at 19:24 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > intel_sprite_set_colorkey_ioctl() lives in intel_sprice_uapi.{c,h}
> > these days. For some reason the old protoype was left behind
> > i
On Mon, Sep 23, 2024 at 08:35:06PM +0300, Ville Syrjälä wrote:
> On Sun, Sep 22, 2024 at 10:40:32AM +, Govindapillai, Vinod wrote:
> > On Mon, 2024-09-16 at 19:24 +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > As with other watermark calculations, the dodgy pre-g4x
> > > up
On Mon, 23 Sep 2024, Andy Shevchenko wrote:
> On Mon, Sep 23, 2024 at 05:35:23PM +0300, Raag Jadav wrote:
>> On Mon, Sep 23, 2024 at 11:38:55AM +0300, Andy Shevchenko wrote:
>> > On Mon, Sep 23, 2024 at 09:28:23AM +0530, Raag Jadav wrote:
>
> ...
>
>> > > +extern const char *const wedge_recovery_o
On Mon, Sep 23, 2024 at 11:43:36PM +0530, Ankit Nautiyal wrote:
> Allow forcing ultrajoiner through debugfs.
>
> v2: Minor refactoring of switch case logic. (Ville)
>
> Signed-off-by: Ankit Nautiyal
> Reviewed-by: Suraj Kandpal
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display
On Mon, Sep 23, 2024 at 11:43:31PM +0530, Ankit Nautiyal wrote:
> From: Stanislav Lisovskiy
>
> Add changes to DSC which are required for Ultrajoiner.
>
> v2:
> -Use correct helper for setting bits for bigjoiner secondary. (Ankit)
> -Use primary/secondary instead of master/slave. (Suraj)
> v3: A
On Mon, Sep 23, 2024 at 11:43:34PM +0530, Ankit Nautiyal wrote:
> From: Stanislav Lisovskiy
>
> Implement required changes for mode validation and compute config,
> to support Ultrajoiner.
>
> v2:
> -Drop changes for HDMI.
> -Separate out DSC changes into another patch.
> v3: Fix check in can_ul
On Mon, Sep 23, 2024 at 04:02:54PM -0300, Gustavo Sousa wrote:
> Tracepoints that display frame and scanline counters for all pipes were
> added with commit 1489bba82433 ("drm/i915: Add cxsr toggle tracepoint")
> and commit 0b2599a43ca9 ("drm/i915: Add pipe enable/disable
> tracepoints"). At that t
On Mon, Sep 23, 2024 at 11:43:29PM +0530, Ankit Nautiyal wrote:
> From: Stanislav Lisovskiy
>
> Ultrajoiner mode has some new bits and states to be
> read out from the hw. Lets make changes accordingly.
>
> v2: Fix checkpatch warnings. (Ankit)
> v3: Add separate functions for computing expected
I recently bumped into some issues while using trace-cmd to inspect i915
display trace events. This series of patches provides fixes for them.
v2:
- Add another patch to zero-initialize frame/scanline counts.
- Add static_assert(PIPE_A == _TRACE_PIPE_A) in "Do not use ids from enum pipe
in
The first part[1] of the LWN series on using TRACE_EVENT() mentions
about TP_printk():
"Do not create new tracepoint-specific helpers, because that will
confuse user-space tools that know about the TRACE_EVENT() helper
macros but will not know how to handle ones created for individual
Tracepoints that display frame and scanline counters for all pipes were
added with commit 1489bba82433 ("drm/i915: Add cxsr toggle tracepoint")
and commit 0b2599a43ca9 ("drm/i915: Add pipe enable/disable
tracepoints"). At that time, we only had pipes A, B and C. Now that we
can also have pipe D, th
In an upcoming change, we will also add support for logging
frame/scanline counts for pipe D in relevant tracepoints.
In [1], Matt mentioned the possibility of having garbage in those counts
for pipe D on a platform containing only 3 pipes. Indeed, it has been
verified that the counts for the extr
Because much of kernel tracepoints is implemented at the C preprocessor
level, C identifiers used in TP_printk() are saved verbatim in the event
format, even when they represent compile-time constant values.
As an example, we can look at the format for the intel_pipe_enable
event:
# cat /sys/
Some display trace events use array members to store frame and scanline
counts for each pipe. However, those arrays are declared with 3 as the
hardcoded size, which cause out-of-bounds access when the trace event is
enabled on a platform that contains pipe D.
For example, when looking at the last
On Mon, Sep 23, 2024 at 11:43:33PM +0530, Ankit Nautiyal wrote:
> From: Stanislav Lisovskiy
>
> ultrajoiner needs 2 bigjoiners to be enabled, so modify the helper
> intel_dp_dsc_get_slice_count for ultrajoiner.
>
> Signed-off-by: Stanislav Lisovskiy
> Signed-off-by: Ankit Nautiyal
> ---
> dri
On Mon, Sep 23, 2024 at 11:43:35PM +0530, Ankit Nautiyal wrote:
> Use the check for ultrajoiner while computing maxdotclock.
>
> v2: Add Check for HAS_UNCOMPRESSED_JOINER. (Ville)
>
> Signed-off-by: Ankit Nautiyal
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 6 --
> 1 file changed
On Mon, Sep 23, 2024 at 05:48:29PM -0300, Gustavo Sousa wrote:
> Quoting Gustavo Sousa (2024-09-23 17:47:08-03:00)
> >Quoting Ville Syrjälä (2024-09-23 17:18:39-03:00)
> >>On Mon, Sep 23, 2024 at 05:06:00PM -0300, Gustavo Sousa wrote:
> >>> Quoting Ville Syrjälä (2024-09-23 16:23:27-03:00)
> >>> >O
On Mon, Sep 23, 2024 at 11:43:30PM +0530, Ankit Nautiyal wrote:
> Pass the current pipe into enabled_joiner_pipes(), and let it figure out
> the proper bitmasks for us.
>
> v2:
> -Simplify helper get_joiner_primary_pipes. (Ville)
> -Nuke get_joiner_secondary_pipes. (Ville)
> -Add more drm_WARNs an
Quoting Ville Syrjälä (2024-09-23 16:23:27-03:00)
>On Mon, Sep 23, 2024 at 04:02:54PM -0300, Gustavo Sousa wrote:
>> Tracepoints that display frame and scanline counters for all pipes were
>> added with commit 1489bba82433 ("drm/i915: Add cxsr toggle tracepoint")
>> and commit 0b2599a43ca9 ("drm/i9
On Tue, 24 Sept 2024 at 04:26, Vignesh Raman
wrote:
>
> Update the documentation to require linking to a relevant GitLab
> issue for each new flake entry instead of an email report. Added
> specific GitLab issue URLs for i915, xe and other drivers.
>
> Signed-off-by: Vignesh Raman
> ---
> Docume
> > > > - /*
> > > > -* The delay may get updated. The transmitter shall
> > > > read the
> > > > -* delay before link status during link training.
> > > > -*/
> > > > - delay_us =
> > > > drm_dp_128b132b_read_aux_rd_inter
> On Thu, 12 Sep 2024, Arun R Murthy wrote:
> > DP Source should be reading AUX_RD interval after we get adjusted
> > TX_FFE_PRESET_VALUE from the DP Sink. (before actually adjusting in DP
> > Source)
>
> I don't think that's correct. See below.
>
Will correct the statement.
> > Signed-off-by:
Update the documentation to require linking to a relevant GitLab
issue for each new flake entry instead of an email report. Added
specific GitLab issue URLs for i915, xe and other drivers.
Signed-off-by: Vignesh Raman
---
Documentation/gpu/automated_testing.rst | 15 ++-
1 file chang
> -Original Message-
> From: Roper, Matthew D
> Sent: Monday, September 23, 2024 11:39 PM
> To: Ville Syrjälä
> Cc: Kandpal, Suraj ; intel-gfx@lists.freedesktop.org;
> Shankar, Uma
> Subject: Re: [PATCH 1/2] drm/i915/hotplug: Reduce SHPD_FLITER_CNT for
> DISPLAY_VER() == 12
>
> On Mo
On Tue, 2024-09-24 at 00:59 +0300, Ville Syrjälä wrote:
> On Mon, Sep 23, 2024 at 08:35:06PM +0300, Ville Syrjälä wrote:
> > On Sun, Sep 22, 2024 at 10:40:32AM +, Govindapillai, Vinod wrote:
> > > On Mon, 2024-09-16 at 19:24 +0300, Ville Syrjala wrote:
> > > > From: Ville Syrjälä
> > > >
> >
Sleeping for < 10us use udelay, for 10us to 20ms use usleep_range() and
for > 10ms use msleep. flseep() will call the particular API based on
the above condition. (Documentation/timers/timers-howto.rst)
Aux RD Interval value depends on the value read from the dpcd register
which is updated from the
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