== Series Details ==
Series: drm: Support per-plane async flip configuration
URL : https://patchwork.freedesktop.org/series/134900/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14943 -> Patchwork_134900v1
Summary
---
> -Original Message-
> From: Hogander, Jouni
> Sent: Thursday, June 13, 2024 3:02 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Kahola, Mika
> ; Hogander, Jouni
> Subject: [PATCH v8 05/20] drm/i915/psr: Disable Panel Replay if PSR mode is
> set via module parameter
>
> -Original Message-
> From: Hogander, Jouni
> Sent: Thursday, June 13, 2024 3:02 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Kahola, Mika
> ; Hogander, Jouni
> Subject: [PATCH v8 06/20] drm/i915/psr: Disable PSR2 SU Region Early
> Transport if psr_enable is set
>
>
> -Original Message-
> From: Hogander, Jouni
> Sent: Thursday, June 13, 2024 3:02 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Kahola, Mika
> ; Hogander, Jouni
> Subject: [PATCH v8 07/20] drm/i915/psr: Disable PSR/Panel Replay on sink
> side for PSR only
>
> Enabling
On Fri, 14 Jun 2024 at 09:21, Linus Torvalds
wrote:
>
> Let's bring in the actual gpu people.. Dave/Jani/others - does any of
> this sound familiar? Pavel says things have gotten much slower in
> 6.10: "something was very wrong with the performance, likely to do
> with graphics"
Actually, maybe i
> -Original Message-
> From: Hogander, Jouni
> Sent: Thursday, June 13, 2024 3:02 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Kahola, Mika
> ; Hogander, Jouni
> Subject: [PATCH v8 08/20] drm/i915/psr: Add new debug bit to disable Panel
> Replay
>
> Add new debug bit
> -Original Message-
> From: Hogander, Jouni
> Sent: Thursday, June 13, 2024 3:02 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Kahola, Mika
> ; Hogander, Jouni
> Subject: [PATCH v8 09/20] Revert "drm/i915/psr: Disable early transport by
> default"
>
> This reverts co
On Fri, Jun 14, 2024 at 12:35:29PM GMT, André Almeida wrote:
> Drivers have different capabilities on what plane types they can or
> cannot perform async flips. Create a plane::async_flip field so each
> driver can choose which planes they allow doing async flips.
>
> Signed-off-by: André Almeida
On Fri, Jun 14, 2024 at 12:35:27PM GMT, André Almeida wrote:
> AMD hardware can do async flips with overlay planes, but currently there's no
> easy way to enable that in DRM. To solve that, this patchset creates a new
> drm_plane field, bool async_flip, that allows drivers to choose which plane
>
Add a DRM core helper to dump the DSC state and take this into use in
the i915 driver to dump the state to dmesg after state computation and
HW readout as well as to the i915_display_info debugfs entry. The state
contains an x16 fixed point value, so also move the corresponding
bpp_x16 helpers from
Add helpers to convert between x16 fixed point and integer/fraction
values. Also add the format/argument macros required to printk x16
fixed point variables.
These are needed by later patches dumping the Display Stream Compression
configuration in DRM core and in the i915 driver to replace the
cor
Replace to_bpp_x16() defined by the driver with the drm_x16_from_int()
defined by DRM core.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_bios.c | 5 +++--
.../gpu/drm/i915/display/intel_display_types.h | 5 -
drivers/gpu/drm/i915/display/intel_dp.c | 17 ++
Add a helper to dump the Display Stream Compression configuration, taken
into use in the i915 driver by a later patch.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/display/drm_dsc_helper.c | 91
include/drm/display/drm_dsc_helper.h | 3 +
2 files changed, 94 inserti
Dump the DSC state to dmesg during HW readout and state computation as
well as the i915_display_info debugfs entry.
Signed-off-by: Imre Deak
---
.../drm/i915/display/intel_crtc_state_dump.c | 3 +++
.../drm/i915/display/intel_display_debugfs.c | 4
drivers/gpu/drm/i915/display/intel_vds
Replace to_bpp_frac() defined by the driver with the equivalent
drm_x16_to_frac() defined by DRM core.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_display_types.h | 7 +--
drivers/gpu/drm/i915/display/intel_dp.c| 4 ++--
drivers/gpu/drm/i915/display/intel_vdsc
Replace to_bpp_int() defined by the driver with the equivalent
drm_x16_from_int() defined by DRM core.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/icl_dsi.c | 9 +
drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
drivers/gpu/drm/i915/display/intel_dis
Replace to_bpp_int_roundup() defined by the driver with the equivalent
drm_x16_to_int_roundup() defined by DRM core.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 4 +++-
drivers/gpu/drm/i915/display/intel_display_types.h | 5 -
drivers/gpu/drm/i915/displa
Replace BPP_X16_FMT()/ARGS() defined by the driver with the equivalent
DRM_X16_FMT()/ARGS() defined by DRM core.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_audio.c | 5 +++--
drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
.../gpu/drm/i915/display/intel_di
The Display Engine's DSC register values are deducted from the DSC
configuration stored in intel_crtc_state::dsc. The latter one is
dumped in a human-readable format, so dumping the register values is
redundant, remove it.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_vdsc.c |
== Series Details ==
Series: drm/i915/dsc: don't mess up splitter state in joiner or dsc config
URL : https://patchwork.freedesktop.org/series/134825/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14935_full -> Patchwork_134825v1_full
==
tree: git://anongit.freedesktop.org/drm-intel for-linux-next-gt
head: 05da7d9f717bcb03c457379fa8a61c1689dab86c
commit: 05da7d9f717bcb03c457379fa8a61c1689dab86c [3/3] drm/i915/gem: Downgrade
stolen lmem setup warning
config: x86_64-randconfig-122-20240614
(https://download.01.org/0day-ci
On Fri, Jun 14, 2024 at 12:35:32PM -0300, André Almeida wrote:
> This driver can perfom async flips on primary planes, so enable it.
>
Cc: Ville Syrjälä
Cc: Naveen Kumar
c: Vandita Kulkarni
> Signed-off-by: André Almeida
> ---
> drivers/gpu/drm/i915/display/i9xx_plane.c | 3 +++
> 1 file ch
== Series Details ==
Series: drm/i915: Dump DSC state to dmesg/debugfs
URL : https://patchwork.freedesktop.org/series/134906/
State : warning
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/134906/revisions/1/mbox/ not
found
== Series Details ==
Series: drm/i915: Dump DSC state to dmesg/debugfs
URL : https://patchwork.freedesktop.org/series/134906/
State : warning
== Summary ==
Error: dim checkpatch failed
f07f771fbdda drm: Add helpers for x16 fixed point values
-:33: WARNING:LONG_LINE: line length of 113 exceeds
== Series Details ==
Series: drm/i915: Dump DSC state to dmesg/debugfs
URL : https://patchwork.freedesktop.org/series/134906/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: Dump DSC state to dmesg/debugfs
URL : https://patchwork.freedesktop.org/series/134906/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14945 -> Patchwork_134906v1
Summary
---
**SU
Hi Dmitry,
Em 14/06/2024 14:32, Dmitry Baryshkov escreveu:
On Fri, Jun 14, 2024 at 12:35:27PM GMT, André Almeida wrote:
AMD hardware can do async flips with overlay planes, but currently there's no
easy way to enable that in DRM. To solve that, this patchset creates a new
drm_plane field, bool
Em 14/06/2024 14:32, Dmitry Baryshkov escreveu:> On Fri, Jun 14, 2024 at
12:35:29PM GMT, André Almeida wrote:
>> Drivers have different capabilities on what plane types they can or
>> cannot perform async flips. Create a plane::async_flip field so each
>> driver can choose which planes they allow
On Fri, Jun 14, 2024 at 03:23:54PM +, Cavitt, Jonathan wrote:
> -Original Message-
> From: Andi Shyti
> Sent: Friday, June 14, 2024 8:22 AM
> To: Andi Shyti
> Cc: intel-gfx ; dri-devel
> ; Harrison, John C
> ; Cavitt, Jonathan
> Subject: Re: [PATCH] drm/i915/gt/uc: Fix typo in com
On Fri, Jun 14, 2024 at 09:55:57AM +0530, Mitul Golani wrote:
> Describe newly added parameter target_rr_divider in struct
> drm_dp_as_sdp.
>
> -v2:
> Remove extra line from commit message.(Lucas)
>
> Fixes: a20c6d954d75 ("drm/dp: Add refresh rate divider to struct representing
> AS SDP")
> Cc:
>
> -Original Message-
From: Vivi, Rodrigo
Sent: Friday, June 14, 2024 12:46 PM
To: Cavitt, Jonathan
Cc: Andi Shyti ; intel-gfx
; dri-devel ;
Harrison, John C
Subject: Re: [PATCH] drm/i915/gt/uc: Fix typo in comment
>
> On Fri, Jun 14, 2024 at 03:23:54PM +, Cavitt, Jonathan wr
Hi!
> > Let's bring in the actual gpu people.. Dave/Jani/others - does any of
> > this sound familiar? Pavel says things have gotten much slower in
> > 6.10: "something was very wrong with the performance, likely to do
> > with graphics"
>
> Actually, maybe it's not graphics at all. Rafael just s
Hi!
> > Let's bring in the actual gpu people.. Dave/Jani/others - does any of
> > this sound familiar? Pavel says things have gotten much slower in
> > 6.10: "something was very wrong with the performance, likely to do
> > with graphics"
>
> Actually, maybe it's not graphics at all. Rafael just s
tree: git://anongit.freedesktop.org/drm-intel for-linux-next-gt
head: 05da7d9f717bcb03c457379fa8a61c1689dab86c
commit: 05da7d9f717bcb03c457379fa8a61c1689dab86c [3/3] drm/i915/gem: Downgrade
stolen lmem setup warning
config: i386-buildonly-randconfig-002-20240615
(https://download.01.org/0day-
On Fri, 2024-06-14 at 16:55 +, Manna, Animesh wrote:
>
>
> > -Original Message-
> > From: Hogander, Jouni
> > Sent: Thursday, June 13, 2024 3:02 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Manna, Animesh ; Kahola, Mika
> > ; Hogander, Jouni
> > Subject: [PATCH v8 06/20] drm/i
On Fri, 2024-06-14 at 16:11 +, Manna, Animesh wrote:
>
>
> > -Original Message-
> > From: Hogander, Jouni
> > Sent: Thursday, June 13, 2024 3:02 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Manna, Animesh ; Kahola, Mika
> > ; Hogander, Jouni
> > Subject: [PATCH v8 02/20] drm/i
== Series Details ==
Series: drm/i915/gt/uc: Evaluate GuC priority within locks (rev4)
URL : https://patchwork.freedesktop.org/series/134525/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14937_full -> Patchwork_134525v4_full
===
== Series Details ==
Series: drm/i915/gt/uc: Fix typo in comment
URL : https://patchwork.freedesktop.org/series/134851/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14937_full -> Patchwork_134851v1_full
Summary
---
On Tue, 2024-05-28 at 14:48 +0300, Vinod Govindapillai wrote:
> Move the handling of the disabling FBC when VT-d is active wa
> as part of the intel_fbc_check_plane(). As the hw is still there,
> intel_fbc_sanitize should be able to handle the state properly.
>
> v2: update the patch description (
On Fri, 2024-04-19 at 17:09 +0300, Vinod Govindapillai wrote:
> Async flip call is not needed. The updated fb mapping is updated
> as part of the fixup_initial_plane_config() call. Otherwise we
> end up updating the PLAN_SURF register twice with the same info.
async_flip is writing PLANE_CTL as we
On Tue, 11 Jun 2024, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/display: Send vrr vsync params whne vrr is enabled
> URL : https://patchwork.freedesktop.org/series/134714/
> State : warning
>
> == Summary ==
>
> Error: dim checkpatch failed
> 711332181393 drm/i915/display: Send
Hi @Jani Nikula
> -Original Message-
> From: Jani Nikula
> Sent: Friday, June 14, 2024 1:09 PM
> To: Patchwork ; Golani, Mitulkumar
> Ajitkumar
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: Send vrr
> vsync params whne vrr is enabl
Hi Dave, Sima,
Got a bit distracted with drm-misc-next-fixes yesterday, so here's a
slightly late drm-misc-fixes.
Cheers,
~Maarten
drm-misc-fixes-2024-06-14:
drm-misc-fixes for v6.10-rc4:
- Kconfig fix for WERROR.
- Add panel quirk for Aya Neo KUN
- Small bugfixes in komeda, bridge/panel, amd
On Fri, 07 Jun 2024, Jani Nikula wrote:
> v2 of https://lore.kernel.org/r/cover.1717757337.git.jani.nik...@intel.com
Thanks for the reviews, pushed to din.
BR,
Jani.
>
> Jani Nikula (6):
> drm/i915/gvt: remove the unused end parameter from calc_index()
> drm/i915/gvt: use proper i915_reg_t
On Fri, 2024-06-14 at 07:11 +, Hogander, Jouni wrote:
> On Fri, 2024-04-19 at 17:09 +0300, Vinod Govindapillai wrote:
> > Async flip call is not needed. The updated fb mapping is updated
> > as part of the fixup_initial_plane_config() call. Otherwise we
> > end up updating the PLAN_SURF registe
On 13/06/2024 11:20, Sebastian Andrzej Siewior wrote:
The !in_atomic() check in _wait_for_atomic() triggers on PREEMPT_RT
because the uncore::lock is a spinlock_t and does not disable
preemption or interrupts.
Changing the uncore:lock to a raw_spinlock_t doubles the worst case
latency on an ot
On Fri, 2024-06-14 at 08:23 +, Govindapillai, Vinod wrote:
> On Fri, 2024-06-14 at 07:11 +, Hogander, Jouni wrote:
> > On Fri, 2024-04-19 at 17:09 +0300, Vinod Govindapillai wrote:
> > > Async flip call is not needed. The updated fb mapping is updated
> > > as part of the fixup_initial_plan
The earlier series [1] had some init order issues in patch 11/14 as
noted by Ville [2].
I'll look into it, but in the mean time, here are the reviewed patches
1-10 and 14 from that series for CI, with 11-13 dropped and to be
revisited and posted later.
BR,
Jani.
[1] https://lore.kernel.org/r/cov
Clarify that the function is specific to PNV, making subsequent changes
slightly easier to grasp.
Reviewed-by: Matt Roper
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/i9xx_wm.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/d
To simplify further changes, add separate functions for reading the fsb
frequency.
This ends up reading CLKCFG register twice, but it's not a big deal.
Reviewed-by: Matt Roper
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/soc/intel_dram.c | 106 +++
Clarify and unify the logging on not finding PNV CxSR latency
config.
Just let the i915->fsb_freq == 0 || i915->mem_freq == 0 case go through
the table instead of checking for it separately.
v2: Do not check for fsb == 0 || mem == 0 separately (Matt)
Reviewed-by: Ville Syrjälä
Signed-off-by: Ja
Split out the PNV DDR3 detection to a distinct step instead of
conflating it with mem freq detection.
Reviewed-by: Matt Roper
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/soc/intel_dram.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff
Follow the same style in mem freq init as in fsb freq init, returning
the value instead of assigning in multiple places.
Reviewed-by: Matt Roper
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/soc/intel_dram.c | 59 ---
1 file changed, 25
It's a bit out of place, and only printed for VLV/CHV.
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm_
We'll want to use fsb frequency for deriving GT clock and rawclk
frequencies in the future. Increase the accuracy by converting to
kHz. Do the same for mem freq to be aligned.
Round the frequencies ending in 666 to 667.
v2: Also handle mem_freq in gen5_rps_init() (Ville)
Reviewed-by: Matt Roper
Initialize fsb frequency for more platforms to be able to use it for GT
clock and rawclk frequency initialization.
Note: There's a discrepancy between existing pnv_fsb_freq() and
i9xx_hrawclk() regarding CLKCFG interpretation. Presume all PNV is
mobile.
Default to 1333 MHz for unknown values, sim
Reuse i9xx_fsb_freq() for GT clock frequency initialization instead of
depending on rawclk_freq.
Note: If the init order was changed, we could use i915->fsb_freq
directly. However, GT clock initialization is done in
i915_driver_mmio_probe(), but intel_dram_detect() later in
i915_driver_hw_probe(),
Instead of duplicating the CLKCFG parsing, reuse i9xx_fsb_freq() to
figure out rawclk_freq where applicable.
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 46 ++
1 file changed, 3 insertions(+), 43 deletions(-)
diff -
Move the comment about FSB straps to where the relevant register is
read.
Suggested-by: Ville Syrjälä
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 11 +--
drivers/gpu/drm/i915/soc/intel_dram.c | 8
2 files changed
== Series Details ==
Series: drm/i915: mem/fsb/rawclk freq cleanups (rev3)
URL : https://patchwork.freedesktop.org/series/134145/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14942 -> Patchwork_134145v3
Summary
---
== Series Details ==
Series: drm/i915: mem/fsb/rawclk freq cleanups (rev3)
URL : https://patchwork.freedesktop.org/series/134145/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitop
This superseeds and includes [1].
BR,
Jani.
[1] https://lore.kernel.org/r/20240613150424.262567-1-jani.nik...@intel.com
Jani Nikula (2):
drm/i915/mso: using joiner is not possible with eDP MSO
drm/i915/dsc: don't mess up splitter state in joiner or dsc config
drivers/gpu/drm/i915/display/
It's not possible to use the joiner at the same time with eDP MSO. When
a panel needs MSO, it's not optional, so MSO trumps joiner.
While just reporting false for intel_dp_has_joiner() should be
sufficient, also skip creation of the joiner force enable debugfs to
better handle this in testing.
Cc
The driver handles splitter (for MSO) and joiner/dsc configuration in
different places. Avoid messing up the splitter hardware state when
enabling/disabling joiner or dsc. It should not be possible to enable
both joiner and splitter at the same time, but add more clarity to the
register use overall
== Series Details ==
Series: drm/i915: fix MSO vs. joiner issue
URL : https://patchwork.freedesktop.org/series/134883/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:116:1:
== Series Details ==
Series: drm/i915: fix MSO vs. joiner issue
URL : https://patchwork.freedesktop.org/series/134883/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14942 -> Patchwork_134883v1
Summary
---
**SUCCESS**
On 2024-06-14 09:32:07 [+0100], Tvrtko Ursulin wrote:
> I think this could be okay-ish in principle, but the commit text is not
> entirely accurate because there is no direct coupling between the wait
> helpers and the uncore lock. They can be used from any atomic context.
>
> Okay-ish in principl
On Fri, Jun 14, 2024 at 01:16:03PM +0300, Jani Nikula wrote:
> It's not possible to use the joiner at the same time with eDP MSO. When
> a panel needs MSO, it's not optional, so MSO trumps joiner.
>
> While just reporting false for intel_dp_has_joiner() should be
> sufficient, also skip creation o
On Fri, Jun 14, 2024 at 01:16:04PM +0300, Jani Nikula wrote:
> The driver handles splitter (for MSO) and joiner/dsc configuration in
> different places. Avoid messing up the splitter hardware state when
> enabling/disabling joiner or dsc. It should not be possible to enable
> both joiner and splitt
On 14/06/2024 12:05, Sebastian Andrzej Siewior wrote:
On 2024-06-14 09:32:07 [+0100], Tvrtko Ursulin wrote:
I think this could be okay-ish in principle, but the commit text is not
entirely accurate because there is no direct coupling between the wait
helpers and the uncore lock. They can be us
Add offset and size parameters to ttm_bo_vmap() to allow for partial
mappings of a buffer object. This brings the functionality on par with
ttm_bo_kmap().
Callers pass the byte offset and size within the buffer object and
receive a page-aligned mapping of the buffer object's memory for the
specifi
Use the newer ttm_bo_vmap() instead of ttm_bo_kmap(). The new interface
uses struct iomap_map, which helps with pointer setup and memcpy() ops.
Removes a TODO item and quite a bit of workarounds from the code.
Signed-off-by: Thomas Zimmermann
---
.../compat-i915-headers/gem/i915_gem_object.h | 1
On Mon, 10 Jun 2024, "Kandpal, Suraj" wrote:
>> Subject: Re: [PATCH 2/2] drm/i915/psr: Implment WA to help reach PC10
>>
>> On Thu, 06 Jun 2024, Suraj Kandpal wrote:
>> > To reach PC10 when PKG_C_LATENCY is configure we must do the following
>> > things
>> > 1) Enter PSR1 only when delayed_vblan
In ttm_bo_vmap(), set up single-page mappings with kmap() in certain
cases. The feature is already present in ttm_bo_kmap().
This functionality is require by DRM's xe driver, which claims that
using kmap() is an optimization over vmap(). [1] Reading the commit
at [2] indicates otherwise. It is not
Move calls to unmap the buffer-object memory from the object-release
code in xe_gem_object_free() to the caller of the release.
Doing an unmap for a BO requires holding the reservation lock, which
is not allowed while releasing a GEM object. Without the reservation
lock, TTM can concurrently evict
Add the public field alloc_flags to struct iosys_map. It allows for
the allocator of the mapping to store additional flags, such details
about the internal alloctor operations. This will be helpful with
DRM's TTM memory manager, which supports various types of memory in
it's vmap functions.
The ne
For each instances of struct iosys_map set up by ttm_bo_vmap(), store
the type of allocation in the instance. Use this information to unmap
the memory in ttm_bo_vunmap(). This change simplifies the unmap code
and puts the complicated logic entirely into the map code.
Signed-off-by: Thomas Zimmerma
Add ttm_bo_kmap()'s features to ttm_bo_vmap() and convert xe to
use the latter helper. ttm_bo_vmap() returns mappings in an instance
of struct iosys_map, which simplifies driver code in several places.
Patches 1 and 2 allow ttm_bo_vmap() to store the method of allocation
in the iosys_map instance.
On Fri, 14 Jun 2024, Ville Syrjälä wrote:
> On Fri, Jun 14, 2024 at 01:16:03PM +0300, Jani Nikula wrote:
>> It's not possible to use the joiner at the same time with eDP MSO. When
>> a panel needs MSO, it's not optional, so MSO trumps joiner.
>>
>> While just reporting false for intel_dp_has_join
On Fri, 14 Jun 2024, Ville Syrjälä wrote:
> On Fri, Jun 14, 2024 at 01:16:04PM +0300, Jani Nikula wrote:
>> The driver handles splitter (for MSO) and joiner/dsc configuration in
>> different places. Avoid messing up the splitter hardware state when
>> enabling/disabling joiner or dsc. It should no
== Series Details ==
Series: drm/{ttm,xe}: Improve ttm_bo_vmap() and update xe
URL : https://patchwork.freedesktop.org/series/134891/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Fri, Jun 14, 2024 at 10:12:13AM GMT, Mitul Golani wrote:
Update calculation to avoid overflow.
-v2:
Remove extra line between cc and signed-off.
Fixes: 1676ecd303ac ("drm/i915: Compute CMRR and calculate vtotal")
Cc: Mitul Golani
Cc: Ankit Nautiyal
Cc: Suraj Kandpal
Cc: Jani Nikula
Cc: S
== Series Details ==
Series: drm/{ttm,xe}: Improve ttm_bo_vmap() and update xe
URL : https://patchwork.freedesktop.org/series/134891/
State : warning
== Summary ==
Error: dim checkpatch failed
9e6b478225b7 iosys-map: Add allocator flags
77686d1beaaf drm/ttm: Store the bo_kmap_type in struct io
Am 14.06.24 um 15:21 schrieb Thomas Zimmermann:
For each instances of struct iosys_map set up by ttm_bo_vmap(), store
the type of allocation in the instance. Use this information to unmap
the memory in ttm_bo_vunmap(). This change simplifies the unmap code
and puts the complicated logic entirely
== Series Details ==
Series: drm/{ttm,xe}: Improve ttm_bo_vmap() and update xe
URL : https://patchwork.freedesktop.org/series/134891/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14943 -> Patchwork_134891v1
Summary
---
It's not possible to use the joiner at the same time with eDP MSO. When
a panel needs MSO, it's not optional, so MSO trumps joiner.
v3: Only change intel_dp_has_joiner(), leave debugfs alone (Ville)
Cc: sta...@vger.kernel.org
Cc: Ville Syrjala
Closes: https://gitlab.freedesktop.org/drm/xe/kernel
On Fri, Jun 14, 2024 at 05:17:51PM +0300, Jani Nikula wrote:
> On Fri, 14 Jun 2024, Ville Syrjälä wrote:
> > On Fri, Jun 14, 2024 at 01:16:04PM +0300, Jani Nikula wrote:
> >> The driver handles splitter (for MSO) and joiner/dsc configuration in
> >> different places. Avoid messing up the splitter
Am 14.06.24 um 15:21 schrieb Thomas Zimmermann:
Add offset and size parameters to ttm_bo_vmap() to allow for partial
mappings of a buffer object. This brings the functionality on par with
ttm_bo_kmap().
Well the long term plan was to remove this functionality from
ttm_bo_kmap() and nuke that f
On Fri, Jun 14, 2024 at 05:23:11PM +0300, Jani Nikula wrote:
> It's not possible to use the joiner at the same time with eDP MSO. When
> a panel needs MSO, it's not optional, so MSO trumps joiner.
>
> v3: Only change intel_dp_has_joiner(), leave debugfs alone (Ville)
>
> Cc: sta...@vger.kernel.or
== Series Details ==
Series: drm/i915/mso: using joiner is not possible with eDP MSO
URL : https://patchwork.freedesktop.org/series/134893/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14943 -> Patchwork_134893v1
Summary
-
I guess sparse and potential CI errors won't minimally relate to
this patch.
Adding also Jonathan in Cc :-)
Thanks,
Andi
On Fri, Jun 14, 2024 at 12:28:37AM +0200, Andi Shyti wrote:
> Replace "dynmically" with "dynamically".
>
> Signed-off-by: Andi Shyti
> Cc: John Harrison
> ---
> drivers/gp
-Original Message-
From: Andi Shyti
Sent: Friday, June 14, 2024 8:22 AM
To: Andi Shyti
Cc: intel-gfx ; dri-devel
; Harrison, John C
; Cavitt, Jonathan
Subject: Re: [PATCH] drm/i915/gt/uc: Fix typo in comment
>
> I guess sparse and potential CI errors won't minimally relate to
> this
Drivers have different capabilities on what plane types they can or
cannot perform async flips. Create a plane::async_flip field so each
driver can choose which planes they allow doing async flips.
Signed-off-by: André Almeida
---
drivers/gpu/drm/drm_atomic_uapi.c | 4 ++--
include/drm/drm_plane
AMD hardware can do async flips with overlay planes, but currently there's no
easy way to enable that in DRM. To solve that, this patchset creates a new
drm_plane field, bool async_flip, that allows drivers to choose which plane can
or cannot do async flips. This is latter used on drm_atomic_set_pr
This driver can perfom async flips on primary planes, so enable it.
Signed-off-by: André Almeida
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
b/drivers/gpu/drm/amd/display/
This driver can perfom async flips on primary planes, so enable it.
Signed-off-by: André Almeida
---
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c
b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_p
This driver can perfom async flips on primary planes, so enable it.
Signed-off-by: André Almeida
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 0279c
This driver can perfom async flips on primary planes, so enable it.
Signed-off-by: André Almeida
---
drivers/gpu/drm/nouveau/dispnv04/crtc.c | 4
drivers/gpu/drm/nouveau/dispnv50/wndw.c | 4
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/nouveau/dispnv04/crtc.c
b/drive
This driver can perfom async flips on primary planes, so enable it.
Signed-off-by: André Almeida
---
drivers/gpu/drm/vc4/vc4_plane.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
index 07caf2a47c6c..e3d41d
Allow userspace to use explicit synchronization with atomic async flips.
That means that the flip will wait for some hardware fence, and then
will flip as soon as possible (async) in regard of the vblank.
Signed-off-by: André Almeida
---
drivers/gpu/drm/drm_atomic_uapi.c | 4 +++-
1 file changed
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