[Intel-gfx] ✗ Fi.CI.BUILD: failure for Refactor i915 HDCP for XE

== Series Details == Series: Refactor i915 HDCP for XE URL : https://patchwork.freedesktop.org/series/123955/ State : failure == Summary == Error: make failed CALLscripts/checksyscalls.sh DESCEND objtool INSTALL libsubcmd_headers CC [M] drivers/gpu/drm/i915/display/intel_hdcp_gsc.

Re: [Intel-gfx] [PATCH 2/2] drm/i915/hdcp: Move common message filling function to its own file

Hi Suraj, kernel test robot noticed the following build errors: [auto build test ERROR on drm-tip/drm-tip] url: https://github.com/intel-lab-lkp/linux/commits/Suraj-Kandpal/drm-i915-hdcp-Move-checks-for-gsc-health-status/20230920-143839 base: git://anongit.freedesktop.org/drm/drm-tip drm

[Intel-gfx] [PATCH 2/2] drm/i915/hdcp: Move common message filling function to its own file

Create a new file intel_hdcp_gsc_message that contain functions which fill the hdcp messages we send to gsc cs this refactor will help us reuse code for Xe later on --v2 -add the missed file for proper build Signed-off-by: Suraj Kandpal --- drivers/gpu/drm/i915/Makefile | 1 +

[Intel-gfx] [PATCH] drm/i915: Zap some empty lines

From: Tvrtko Ursulin Recent refactoring left an unsightly block of empty lines. Remove them. Signed-off-by: Tvrtko Ursulin Cc: Dnyaneshwar Bhadane Cc: Anusha Srivatsa Cc: Radhakrishna Sripada --- drivers/gpu/drm/i915/i915_drv.h | 7 --- 1 file changed, 7 deletions(-) diff --git a/drive

[Intel-gfx] [PATCH v2] drm/i915/gt: Update RC6 mask for mtl_drpc

It is seen that for RC6 status register is sometimes setting unused bits without affecting functionality. So updated the mask with used bits. As mtl_drpc is debug fs function removing MISSING_CASE from default case as it doesn't make sense to panic (panic_on_warn=1) the system if register is report

Re: [Intel-gfx] [PATCH 7/7] drm/i915: Enable GGTT updates with binder in MTL

Hi Nirmoy, https://gfxspecs.intel.com/Predator/Home/Index/52885?dstFilter=MTL&mode=Filter I can't find Wa_13010847436 and Wa_14019519902 in the above link, where can I check these WA? Br, G.G. On 9/18/23 8:02 PM, Nirmoy Das wrote: MTL can hang because of a HW bug while parallel reading/wri

Re: [Intel-gfx] [PATCH 1/7] drm/i915: Lift runtime-pm acquire callbacks out of intel_wakeref.mutex

On Mon, 18 Sep 2023, Nirmoy Das wrote: > From: Chris Wilson > > When runtime pm is first woken, it will synchronously call the > registered callbacks for the device. These callbacks > may pull in their own forest of locks, which we do not want to > conflate with the intel_wakeref.mutex. A second

Re: [Intel-gfx] [PATCH] drm/i915: Zap some empty lines

On Wed, 20 Sep 2023, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin > > Recent refactoring left an unsightly block of empty lines. Remove them. > > Signed-off-by: Tvrtko Ursulin > Cc: Dnyaneshwar Bhadane > Cc: Anusha Srivatsa > Cc: Radhakrishna Sripada One of the harder patches I've reviewed t

Re: [Intel-gfx] [PATCH v3 17/25] drm/i915/dp_mst: Fix PBN calculation with FEC overhead

On Thu, Sep 14, 2023 at 10:26:51PM +0300, Imre Deak wrote: > On 8b/10b MST links the PBN value for DSC streams must be calculated > accounting for the FEC overhead. The same applies to 8b/10b non-DSC > streams if there is another DSC stream on the same link. Fix up the PBN > calculation accordingly

Re: [Intel-gfx] [PATCH v3 18/25] drm/i915/dp_mst: Add atomic state for all streams on pre-tgl platforms

On Thu, Sep 14, 2023 at 10:26:52PM +0300, Imre Deak wrote: > If an MST stream is modeset, its state must be checked along all the > other streams on the same MST link, for instance to resolve a BW > overallocation of a non-sink MST port or to make sure that the FEC is > enabled/disabled the same wa

Re: [Intel-gfx] [PATCH 2/2] drm/i915/hdcp: Move common message filling function to its own file

On Wed, 20 Sep 2023, Suraj Kandpal wrote: > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.h > b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.h > index eba2057c5a9e..e53dbe8d9048 100644 > --- a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.h > +++ b/drivers/gpu/drm/i915/display/intel_hdcp_

[Intel-gfx] ✗ Fi.CI.IGT: failure for MAINTAINERS: drm/ci: add entries for xfail files

== Series Details == Series: MAINTAINERS: drm/ci: add entries for xfail files URL : https://patchwork.freedesktop.org/series/123932/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13652_full -> Patchwork_123932v1_full Summar

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Require FEC for DSC on DP-MST

On Wed, 13 Sep 2023, Ville Syrjala wrote: > From: Ville Syrjälä > > The current check just asserts that we need FEC to use DSC > with (non-eDP) DP-SST. But MST also needs FEC for DSC. Just > check for !eDP instead to cover all the cases correctly. 128b/132b won't have crtc->fec_enable set, as it

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Check lane count when determining FEC support

On Wed, 13 Sep 2023, Ville Syrjala wrote: > From: Ville Syrjälä > > ICL doesn't support FEC with a x1 DP link. Make sure > we don't try to enable FEC in such cases. The question is, should we rather require x2 link for FEC? I suppose x1 link with DSC+FEC is an unlikely scenario with our current

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Refactor i915 HDCP for XE (rev2)

== Series Details == Series: Refactor i915 HDCP for XE (rev2) URL : https://patchwork.freedesktop.org/series/123955/ State : warning == Summary == Error: dim checkpatch failed 86d0a82a07c2 drm/i915/hdcp: Move checks for gsc health status c896414f7fe9 drm/i915/hdcp: Move common message filling

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Refactor i915 HDCP for XE (rev2)

== Series Details == Series: Refactor i915 HDCP for XE (rev2) URL : https://patchwork.freedesktop.org/series/123955/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:117:1: wa

Re: [Intel-gfx] [PATCH 2/2] drm/i915/hdcp: Move common message filling function to its own file

> Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915/hdcp: Move common message > filling function to its own file > > On Wed, 20 Sep 2023, Suraj Kandpal wrote: > > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.h > > b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.h > > index eba2057c5a9e..e53

Re: [Intel-gfx] [PATCH 2/2] drm/i915/hdcp: Move common message filling function to its own file

Hi Suraj, kernel test robot noticed the following build errors: [auto build test ERROR on drm-tip/drm-tip] url: https://github.com/intel-lab-lkp/linux/commits/Suraj-Kandpal/drm-i915-hdcp-Move-checks-for-gsc-health-status/20230920-143839 base: git://anongit.freedesktop.org/drm/drm-tip drm

[Intel-gfx] ✓ Fi.CI.BAT: success for Refactor i915 HDCP for XE (rev2)

== Series Details == Series: Refactor i915 HDCP for XE (rev2) URL : https://patchwork.freedesktop.org/series/123955/ State : success == Summary == CI Bug Log - changes from CI_DRM_13653 -> Patchwork_123955v2 Summary --- **SUCCESS**

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Zap some empty lines

== Series Details == Series: drm/i915: Zap some empty lines URL : https://patchwork.freedesktop.org/series/123963/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Zap some empty lines

== Series Details == Series: drm/i915: Zap some empty lines URL : https://patchwork.freedesktop.org/series/123963/ State : success == Summary == CI Bug Log - changes from CI_DRM_13653 -> Patchwork_123963v1 Summary --- **SUCCESS**

Re: [Intel-gfx] [PATCH] drm/i915: Zap some empty lines

> -Original Message- > From: dri-devel On Behalf Of Tvrtko > Ursulin > Sent: Wednesday, September 20, 2023 2:27 PM > To: Intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org > Cc: Srivatsa, Anusha ; Bhadane, Dnyaneshwar > ; Sripada, Radhakrishna > ; Ursulin, Tvrtko > Subjec

[Intel-gfx] [PATCH v3 2/2] drm/i915/hdcp: Move common message filling function to its own file

Create a new file intel_hdcp_gsc_message that contain functions which fill the hdcp messages we send to gsc cs this refactor will help us reuse code for Xe later on --v2 -add the missed file for proper build --v3 -use forward declarations instead of #includes [Jani] Signed-off-by: Suraj Kandpal

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Update RC6 mask for mtl_drpc (rev2)

== Series Details == Series: drm/i915/gt: Update RC6 mask for mtl_drpc (rev2) URL : https://patchwork.freedesktop.org/series/123775/ State : success == Summary == CI Bug Log - changes from CI_DRM_13653 -> Patchwork_123775v2 Summary ---

Re: [Intel-gfx] [PATCH v3 17/25] drm/i915/dp_mst: Fix PBN calculation with FEC overhead

On Thu, Sep 14, 2023 at 10:26:51PM +0300, Imre Deak wrote: > On 8b/10b MST links the PBN value for DSC streams must be calculated > accounting for the FEC overhead. The same applies to 8b/10b non-DSC > streams if there is another DSC stream on the same link. Fix up the PBN > calculation accordingly

Re: [Intel-gfx] [PATCH v3 18/25] drm/i915/dp_mst: Add atomic state for all streams on pre-tgl platforms

On Wed, Sep 20, 2023 at 12:11:58PM +0300, Lisovskiy, Stanislav wrote: > On Thu, Sep 14, 2023 at 10:26:52PM +0300, Imre Deak wrote: > > If an MST stream is modeset, its state must be checked along all the > > other streams on the same MST link, for instance to resolve a BW > > overallocation of a no

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Require FEC for DSC on DP-MST

On Wed, Sep 20, 2023 at 12:20:51PM +0300, Jani Nikula wrote: > On Wed, 13 Sep 2023, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > The current check just asserts that we need FEC to use DSC > > with (non-eDP) DP-SST. But MST also needs FEC for DSC. Just > > check for !eDP instead to cover a

[Intel-gfx] [PATCH] drm/i915: Remove unnecessary memory quiescing for aux inval

i915 already does memory quiesce before signaling breadcrumb so remove extra memory quiescing for aux invalidation which can cause unnecessary side effects. Fixes: 78a6ccd65fa3 ("drm/i915/gt: Ensure memory quiesced before invalidation") Cc: Jonathan Cavitt Cc: Andi Shyti Cc: # v5.8+ Cc: Andrzej

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Check lane count when determining FEC support

On Wed, Sep 20, 2023 at 12:23:34PM +0300, Jani Nikula wrote: > On Wed, 13 Sep 2023, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > ICL doesn't support FEC with a x1 DP link. Make sure > > we don't try to enable FEC in such cases. > > The question is, should we rather require x2 link for FE

Re: [Intel-gfx] [PATCH] drm/i915: Fix aux invalidation with proper pipe_control flag

Sent out https://patchwork.freedesktop.org/series/123975/ to replace this one as this not really fixing the issue. Thanks, Nirmoy On 9/19/2023 2:19 PM, Tapani Pälli wrote: On 19.9.2023 15.11, Andi Shyti wrote: Hi Nirmoy, On Tue, Sep 19, 2023 at 01:47:16PM +0200, Nirmoy Das wrote: The sug

Re: [Intel-gfx] [PATCH v3 18/25] drm/i915/dp_mst: Add atomic state for all streams on pre-tgl platforms

On Wed, Sep 20, 2023 at 01:59:53PM +0300, Ville Syrjälä wrote: > On Wed, Sep 20, 2023 at 12:11:58PM +0300, Lisovskiy, Stanislav wrote: > > On Thu, Sep 14, 2023 at 10:26:52PM +0300, Imre Deak wrote: > > > If an MST stream is modeset, its state must be checked along all the > > > other streams on the

[Intel-gfx] [PATCH] drm/i915: add a note about fec_enable with 128b/132b

Add a note that fec_enable actually means FEC is to be enabled explicitly. 128b/132b always has FEC enabled, the driver doesn't need to enable it separately, and fec_enable will be false. Cc: Ville Syrjälä Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_types.h | 7 +++

Re: [Intel-gfx] [PATCH v3 17/25] drm/i915/dp_mst: Fix PBN calculation with FEC overhead

On Wed, Sep 20, 2023 at 01:58:43PM +0300, Ville Syrjälä wrote: > On Thu, Sep 14, 2023 at 10:26:51PM +0300, Imre Deak wrote: > > On 8b/10b MST links the PBN value for DSC streams must be calculated > > accounting for the FEC overhead. The same applies to 8b/10b non-DSC > > streams if there is anothe

Re: [Intel-gfx] [PATCH] drm/i915: Do not disable preemption for resets

On 13/09/2023 18:04, Valentin Schneider wrote: On Wed, 13 Sept 2023 at 18:48, Sebastian Andrzej Siewior wrote: On 2023-07-05 10:30:25 [+0100], Tvrtko Ursulin wrote: From: Tvrtko Ursulin Commit ade8a0f59844 ("drm/i915: Make all GPU resets atomic") added a preempt disable section over the h

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Check lane count when determining FEC support

On Wed, 20 Sep 2023, Ville Syrjälä wrote: > On Wed, Sep 20, 2023 at 12:23:34PM +0300, Jani Nikula wrote: >> On Wed, 13 Sep 2023, Ville Syrjala wrote: >> > From: Ville Syrjälä >> > >> > ICL doesn't support FEC with a x1 DP link. Make sure >> > we don't try to enable FEC in such cases. >> >> The

Re: [Intel-gfx] [PATCH] drm/i915: add a note about fec_enable with 128b/132b

On Wed, Sep 20, 2023 at 02:29:01PM +0300, Jani Nikula wrote: > Add a note that fec_enable actually means FEC is to be enabled > explicitly. 128b/132b always has FEC enabled, the driver doesn't need to > enable it separately, and fec_enable will be false. > > Cc: Ville Syrjälä > Signed-off-by: Jan

Re: [Intel-gfx] [PATCH v3 2/2] drm/i915/hdcp: Move common message filling function to its own file

On Wed, 20 Sep 2023, Suraj Kandpal wrote: > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.h > b/drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.h > new file mode 100644 > index ..1096dd36823f > --- /dev/null > +++ b/drivers/gpu/drm/i915/display/intel_hdcp_gsc_me

Re: [Intel-gfx] [PATCH] drm/i915: Remove unnecessary memory quiescing for aux inval

I tested this first against tests that were failing for Mesa and it fixes all of the regressed cases (TGL LP). Also did a full run of all KHR-GLES31* and KHR-GLES32* test groups in the Khronos CTS suite, no regressions observed. Tested-by: Tapani Pälli On 20.9.2023 14.11, Nirmoy Das wrote:

Re: [Intel-gfx] [PATCH v3 18/25] drm/i915/dp_mst: Add atomic state for all streams on pre-tgl platforms

On Wed, Sep 20, 2023 at 02:25:14PM +0300, Lisovskiy, Stanislav wrote: > On Wed, Sep 20, 2023 at 01:59:53PM +0300, Ville Syrjälä wrote: > > On Wed, Sep 20, 2023 at 12:11:58PM +0300, Lisovskiy, Stanislav wrote: > > > On Thu, Sep 14, 2023 at 10:26:52PM +0300, Imre Deak wrote: > > > > If an MST stream

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Refactor i915 HDCP for XE (rev3)

== Series Details == Series: Refactor i915 HDCP for XE (rev3) URL : https://patchwork.freedesktop.org/series/123955/ State : warning == Summary == Error: dim checkpatch failed 004d02f4d754 drm/i915/hdcp: Move checks for gsc health status 39677cfad370 drm/i915/hdcp: Move common message filling

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Refactor i915 HDCP for XE (rev3)

== Series Details == Series: Refactor i915 HDCP for XE (rev3) URL : https://patchwork.freedesktop.org/series/123955/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:117:1: wa

[Intel-gfx] ✓ Fi.CI.BAT: success for Refactor i915 HDCP for XE (rev3)

== Series Details == Series: Refactor i915 HDCP for XE (rev3) URL : https://patchwork.freedesktop.org/series/123955/ State : success == Summary == CI Bug Log - changes from CI_DRM_13655 -> Patchwork_123955v3 Summary --- **SUCCESS**

Re: [Intel-gfx] [PATCH v2] drm: Update file owner during use

On 28/08/2023 20:58, Rob Clark wrote: On Wed, Jun 21, 2023 at 2:48 AM Tvrtko Ursulin wrote: From: Tvrtko Ursulin With the typical model where the display server opens the file descriptor and then hands it over to the client(*), we were showing stale data in debugfs. Fix it by updating the

Re: [Intel-gfx] [PATCH v2] drm: Update file owner during use

Am 20.09.23 um 15:21 schrieb Tvrtko Ursulin: On 28/08/2023 20:58, Rob Clark wrote: On Wed, Jun 21, 2023 at 2:48 AM Tvrtko Ursulin wrote: From: Tvrtko Ursulin With the typical model where the display server opens the file descriptor and then hands it over to the client(*), we were showing

Re: [Intel-gfx] [PATCH] drm/i915: Add Wa_18028616096

Quoting Shekhar Chauhan (2023-09-20 01:05:47-03:00) >Drop UGM per set fragment threshold to 3 > >BSpec: 54833 >Signed-off-by: Shekhar Chauhan >--- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + > drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ > 2 files changed, 4 insertions(+) > >diff --

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Remove unnecessary memory quiescing for aux inval

== Series Details == Series: drm/i915: Remove unnecessary memory quiescing for aux inval URL : https://patchwork.freedesktop.org/series/123975/ State : success == Summary == CI Bug Log - changes from CI_DRM_13655 -> Patchwork_123975v1 Summa

Re: [Intel-gfx] [PATCH 00/10] drm/i915/spi: spi access for discrete graphics

> > > > No SPI controllers are directly visible to userspace, some SPI devices > > > > are selectively exposed but that needs to be explicitly requested and is > > > > generally discouraged. > > > > What are the options here? Explicitly request exception is the one. > > > Any other way to add acce

Re: [Intel-gfx] [PATCH v3 18/25] drm/i915/dp_mst: Add atomic state for all streams on pre-tgl platforms

On Wed, Sep 20, 2023 at 03:38:05PM +0300, Imre Deak wrote: > On Wed, Sep 20, 2023 at 02:25:14PM +0300, Lisovskiy, Stanislav wrote: > > On Wed, Sep 20, 2023 at 01:59:53PM +0300, Ville Syrjälä wrote: > > > On Wed, Sep 20, 2023 at 12:11:58PM +0300, Lisovskiy, Stanislav wrote: > > > > On Thu, Sep 14, 2

Re: [Intel-gfx] [PATCH i-g-t] tests/i915_pm_freq_api: Set min/max to expected values

On Mon, Sep 18, 2023 at 12:02:59PM -0700, Vinay Belgaumkar wrote: > A prior(rps) test leaves the system in a bad state causing failures > in the basic test. Why? What was the freq immediately before the failure that made the machine to be busted and not accept the new freq request? Maybe we shou

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] tests/i915_pm_freq_api: Set min/max to expected values

On 9/19/2023 12:32 AM, Vinay Belgaumkar wrote: A prior(rps) test leaves the system in a bad state causing failures in the basic test. Set min/max to expected values before running it. Test will restore values at the end. Link: https://gitlab.freedesktop.org/drm/intel/-/issues/8670 Signed-off

Re: [Intel-gfx] [PATCH 5/5] drm/i915: Implement fdinfo memory stats printing

On 24/08/2023 12:35, Upadhyay, Tejas wrote: -Original Message- From: Intel-gfx On Behalf Of Tvrtko Ursulin Sent: Friday, July 7, 2023 6:32 PM To: Intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org Subject: [Intel-gfx] [PATCH 5/5] drm/i915: Implement fdinfo memory stats pr

Re: [Intel-gfx] [PATCH 5/5] drm/i915: Implement fdinfo memory stats printing

On Wed, Sep 20, 2023 at 7:35 AM Tvrtko Ursulin wrote: > > > On 24/08/2023 12:35, Upadhyay, Tejas wrote: > >> -Original Message- > >> From: Intel-gfx On Behalf Of > >> Tvrtko > >> Ursulin > >> Sent: Friday, July 7, 2023 6:32 PM > >> To: Intel-gfx@lists.freedesktop.org; dri-de...@lists.fre

Re: [Intel-gfx] [PATCH 1/1] drm/i915/uapi: Enable L3 Bank Count Querying

On Thu, Sep 14, 2023 at 11:32:49AM -0700, Jonathan Cavitt wrote: > Extend the query ioctl to allow querying the count of the available L3 > Banks on a given engine. Why do you need this? Who is using? Where's the pull request for the UMDs and IGTs? > > Signed-off-by: Jonathan Cavitt > --- Plea

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: add a note about fec_enable with 128b/132b

== Series Details == Series: drm/i915: add a note about fec_enable with 128b/132b URL : https://patchwork.freedesktop.org/series/123977/ State : success == Summary == CI Bug Log - changes from CI_DRM_13656 -> Patchwork_123977v1 Summary

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Do not disable preemption for resets (rev2)

== Series Details == Series: drm/i915: Do not disable preemption for resets (rev2) URL : https://patchwork.freedesktop.org/series/120218/ State : warning == Summary == Error: dim checkpatch failed 8595cf4574a7 drm/i915: Do not disable preemption for resets -:14: ERROR:GIT_COMMIT_ID: Please use

Re: [Intel-gfx] [PATCH 1/7] drm/i915: Lift runtime-pm acquire callbacks out of intel_wakeref.mutex

Hi Jani, On 9/20/2023 11:03 AM, Jani Nikula wrote: On Mon, 18 Sep 2023, Nirmoy Das wrote: From: Chris Wilson When runtime pm is first woken, it will synchronously call the registered callbacks for the device. These callbacks may pull in their own forest of locks, which we do not want to conf

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Do not disable preemption for resets (rev2)

== Series Details == Series: drm/i915: Do not disable preemption for resets (rev2) URL : https://patchwork.freedesktop.org/series/120218/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13656 -> Patchwork_120218v2 Summary ---

Re: [Intel-gfx] [PATCH 00/10] drm/i915/spi: spi access for discrete graphics

On Wed, Sep 20, 2023 at 01:52:07PM +, Usyskin, Alexander wrote: > I've tried to register spi controller with a spi-mem ops, but I can't find a > way to connect to mtd subsystem. > I took spi-intel as example, which connects to spi-nor but it relies on JDEC > ID of flash to configure itself.

Re: [Intel-gfx] [PATCH v3 2/2] drm/i915/hdcp: Move common message filling function to its own file

> Subject: Re: [PATCH v3 2/2] drm/i915/hdcp: Move common message filling > function to its own file > > On Wed, 20 Sep 2023, Suraj Kandpal wrote: > > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.h > > b/drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.h > > new file mode 1

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,01/22] drm/i915/xelpdp: Add XE_LPDP_FEATURES (rev2)

== Series Details == Series: series starting with [CI,01/22] drm/i915/xelpdp: Add XE_LPDP_FEATURES (rev2) URL : https://patchwork.freedesktop.org/series/123938/ State : warning == Summary == Error: dim checkpatch failed 90dd23f88c0a drm/i915/xelpdp: Add XE_LPDP_FEATURES 6330ee8e7216 drm/i915/

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,01/22] drm/i915/xelpdp: Add XE_LPDP_FEATURES (rev2)

== Series Details == Series: series starting with [CI,01/22] drm/i915/xelpdp: Add XE_LPDP_FEATURES (rev2) URL : https://patchwork.freedesktop.org/series/123938/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separatel

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,01/22] drm/i915/xelpdp: Add XE_LPDP_FEATURES (rev2)

== Series Details == Series: series starting with [CI,01/22] drm/i915/xelpdp: Add XE_LPDP_FEATURES (rev2) URL : https://patchwork.freedesktop.org/series/123938/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13656 -> Patchwork_123938v2 =

Re: [Intel-gfx] [PATCH i-g-t] tests/i915_pm_freq_api: Set min/max to expected values

On 9/20/2023 7:07 AM, Rodrigo Vivi wrote: On Mon, Sep 18, 2023 at 12:02:59PM -0700, Vinay Belgaumkar wrote: A prior(rps) test leaves the system in a bad state causing failures in the basic test. Why? What was the freq immediately before the failure that made the machine to be busted and not

Re: [Intel-gfx] [PATCH] drm/i915: Remove unnecessary memory quiescing for aux inval

On Wed, Sep 20, 2023 at 01:11:31PM +0200, Nirmoy Das wrote: > i915 already does memory quiesce before signaling > breadcrumb so remove extra memory quiescing for aux > invalidation which can cause unnecessary side effects. This explanation seems confusing to me. If we've already performed the nec

Re: [Intel-gfx] [PATCH] drm/edid: Fixup h/vsync_end instead of h/vtotal

On Thu, 14 Sep 2023, Ville Syrjala wrote: > From: Ville Syrjälä > > There are some weird EDIDs floating around that have the sync > pulse extending beyond the end of the blanking period. > > On the currently problemtic machine (HP Omni 120) EDID reports > the following mode: > "1600x900": 60 1080

Re: [Intel-gfx] [PATCH v2] drm/i915/dsi: let HW maintain CLK_POST

On Thu, 14 Sep 2023, William Tseng wrote: > This change is to adjust TCLK-POST timing so DSI signaling can > meet CTS specification. > > For clock lane, the TCLK-POST timing may be changed from > 133.44 ns to 178.72 ns, which is greater than (60 ns+52*UI) > and is conformed to the CTS standard. >

Re: [Intel-gfx] [PATCH i-g-t v3 15/17] lib/kunit: Parse KTAP report from the main process thread

On Mon, 18 Sep 2023 15:43:05 +0200 Janusz Krzysztofik wrote: > There was an attempt to parse KTAP reports in the background while a kunit > test module is loading. However, since dynamic sub-subtests can be > executed only from the main thread, that attempt was not quite successful, > as IGT res

[Intel-gfx] ✗ Fi.CI.IGT: failure for Refactor i915 HDCP for XE (rev3)

== Series Details == Series: Refactor i915 HDCP for XE (rev3) URL : https://patchwork.freedesktop.org/series/123955/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13655_full -> Patchwork_123955v3_full Summary --- **F

Re: [Intel-gfx] [PATCH v2 12/12] drm/i915: Implement transcoder LRR for TGL+

Hi Ville, Quick question here on the use case and the trigger for the LRR case which is within VRR range. Could this perhaps be used if we had a virtual mode say 40Hz that now falls in the VRR range (30 -120Hz) that is exposed through the connector mode list and then if we do a modest to 40Hz that

Re: [Intel-gfx] [PATCH 00/12] drm/i915: VRR, LRR, and M/N stuff

Hi Ville, After the comments have been addressed, I have completed reviewing the patches. Is there anything else blocking this from getting merged? Could we get this merged if everything looks good? Regards Manasi On Fri, Sep 1, 2023 at 6:04 AM Ville Syrjala wrote: > > From: Ville Syrjälä > >

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Remove unnecessary memory quiescing for aux inval

== Series Details == Series: drm/i915: Remove unnecessary memory quiescing for aux inval URL : https://patchwork.freedesktop.org/series/123975/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13655_full -> Patchwork_123975v1_full =

Re: [Intel-gfx] [PATCH] drm/edid: Fixup h/vsync_end instead of h/vtotal

On Wed, Sep 20, 2023 at 08:40:00PM +0300, Jani Nikula wrote: > On Thu, 14 Sep 2023, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > There are some weird EDIDs floating around that have the sync > > pulse extending beyond the end of the blanking period. > > > > On the currently problemtic mac

Re: [Intel-gfx] [PATCH v2 12/12] drm/i915: Implement transcoder LRR for TGL+

On Wed, Sep 20, 2023 at 11:47:05AM -0700, Manasi Navare wrote: > Hi Ville, > > Quick question here on the use case and the trigger for the LRR case > which is within VRR range. > Could this perhaps be used if we had a virtual mode say 40Hz that now > falls in the VRR range (30 -120Hz) that is > ex

Re: [Intel-gfx] [PATCH 0/4] drm/i915/vlv_dsi: Add quirks for x86 android tablets (v2)

Hi Ville, On 9/18/23 10:00, Ville Syrjälä wrote: > On Sat, Sep 16, 2023 at 02:54:51PM +0200, Hans de Goede wrote: >> Hi All, >> >> Some vlv/chv tablets ship with Android as factory OS. The factory OS >> BSP style kernel on these tablets does not use the normal x86 hw >> autodetection instead it ha

[Intel-gfx] [PATCH v2] drm/i915/irq: Clear GFX_MSTR_IRQ as part of IRQ reset

Starting with Xe_LP+, GFX_MSTR_IRQ contains status bits that have W1C behavior. If we do not properly reset them, we would miss delivery of interrupts if a pending bit is set when enabling IRQs. As an example, the display part of our probe routine contains paths where we wait for vblank interrupts

[Intel-gfx] [PATCH 0/4] drm/i915/vlv_dsi: Add quirks for x86 android tablets (v3)

Hi All, Some vlv/chv tablets ship with Android as factory OS. The factory OS BSP style kernel on these tablets does not use the normal x86 hw autodetection instead it hardcodes a whole bunch of things including using panel drivers instead of relying on VBT MIPI sequences to turn the panel/backligh

[Intel-gfx] [PATCH 1/4] drm/i915/vlv_dsi: Add DMI quirk for wrong panel modeline in BIOS on Asus TF103C (v3)

Vtotal is wrong in the BIOS supplied modeline for the DSI panel on the Asus TF103C leading to the last line of the display being shown as the first line. Original: "1280x800": 60 67700 1280 1312 1328 1376 800 808 812 820 0x8 0xa Fixed:"1280x800": 60 67700 1280 1312 1328 1376 800 808 812 816 0x

[Intel-gfx] [PATCH 4/4] drm/i915/dsi: Add some debug logging to mipi_exec_i2c (v2)

Add some debug logging to mipi_exec_i2c, to make debugging various issues seen with it easier. Changes in v2: - Drop unnecessary __func__ drm_dbg_kms() argument Signed-off-by: Hans de Goede --- drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/d

[Intel-gfx] [PATCH 3/4] drm/i915/vlv_dsi: Add DMI quirk for backlight control issues on Lenovo Yoga Tab 3 (v2)

On the Lenovo Yoga Tab 3 Pro YT3-X90F there are 2 issues with the backlight on/off MIPI sequences: 1. The backlight on sequence has an I2C MIPI sequence element which uses bus 0, but there is a bogus I2cSerialBus resource under the GPU in the DSDT which causes i2c_acpi_find_adapter() to pick

[Intel-gfx] [PATCH 2/4] drm/i915/vlv_dsi: Add DMI quirk for wrong I2C bus and panel size on Lenovo Yoga Tablet 2 series (v3)

On the Lenovo Yoga Tablet 2 830 / 1050 there are 2 problems: 1. The I2C MIPI sequence elements reference bus 3. ACPI has I2C1 - I2C7 which under Linux become bus 0 - 6. And the MIPI sequence reference to bus 3 is indented for I2C3 which is bus 2 under Linux. This leads to errors like the

Re: [Intel-gfx] [PATCH v2] drm/i915/irq: Clear GFX_MSTR_IRQ as part of IRQ reset

On Wed, Sep 20, 2023 at 04:53:52PM -0300, Gustavo Sousa wrote: > Starting with Xe_LP+, GFX_MSTR_IRQ contains status bits that have W1C > behavior. If we do not properly reset them, we would miss delivery of > interrupts if a pending bit is set when enabling IRQs. > > As an example, the display par

Re: [Intel-gfx] [PATCH v2] drm/i915/irq: Clear GFX_MSTR_IRQ as part of IRQ reset

Quoting Ville Syrjälä (2023-09-20 17:00:07-03:00) >On Wed, Sep 20, 2023 at 04:53:52PM -0300, Gustavo Sousa wrote: >> Starting with Xe_LP+, GFX_MSTR_IRQ contains status bits that have W1C >> behavior. If we do not properly reset them, we would miss delivery of >> interrupts if a pending bit is set w

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/perf: Remove gtt_offset from stream->oa_buffer.head/.tail (rev2)

== Series Details == Series: drm/i915/perf: Remove gtt_offset from stream->oa_buffer.head/.tail (rev2) URL : https://patchwork.freedesktop.org/series/123949/ State : success == Summary == CI Bug Log - changes from CI_DRM_13658 -> Patchwork_123949v2

Re: [Intel-gfx] [PATCH v2] drm/i915/irq: Clear GFX_MSTR_IRQ as part of IRQ reset

On Wed, Sep 20, 2023 at 05:13:36PM -0300, Gustavo Sousa wrote: > Quoting Ville Syrjälä (2023-09-20 17:00:07-03:00) > >On Wed, Sep 20, 2023 at 04:53:52PM -0300, Gustavo Sousa wrote: > >> Starting with Xe_LP+, GFX_MSTR_IRQ contains status bits that have W1C > >> behavior. If we do not properly reset

Re: [Intel-gfx] [PATCH i-g-t] tests/i915_pm_freq_api: Set min/max to expected values

On Wed, Sep 20, 2023 at 09:18:07AM -0700, Belgaumkar, Vinay wrote: > > On 9/20/2023 7:07 AM, Rodrigo Vivi wrote: > > On Mon, Sep 18, 2023 at 12:02:59PM -0700, Vinay Belgaumkar wrote: > > > A prior(rps) test leaves the system in a bad state causing failures > > > in the basic test. > > Why? > > >

Re: [Intel-gfx] [PATCH v2 12/12] drm/i915: Implement transcoder LRR for TGL+

On Wed, Sep 20, 2023 at 12:40 PM Ville Syrjälä wrote: > > On Wed, Sep 20, 2023 at 11:47:05AM -0700, Manasi Navare wrote: > > Hi Ville, > > > > Quick question here on the use case and the trigger for the LRR case > > which is within VRR range. > > Could this perhaps be used if we had a virtual mode

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Update GGTT with MI_UPDATE_GTT on MTL (rev8)

== Series Details == Series: Update GGTT with MI_UPDATE_GTT on MTL (rev8) URL : https://patchwork.freedesktop.org/series/123329/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Update GGTT with MI_UPDATE_GTT on MTL (rev8)

== Series Details == Series: Update GGTT with MI_UPDATE_GTT on MTL (rev8) URL : https://patchwork.freedesktop.org/series/123329/ State : warning == Summary == Error: dim checkpatch failed a1b7a590c8ed drm/i915: Lift runtime-pm acquire callbacks out of intel_wakeref.mutex -:57: WARNING:AVOID_B

Re: [Intel-gfx] [PATCH 00/12] drm/i915: VRR, LRR, and M/N stuff

On Wed, Sep 20, 2023 at 11:54:41AM -0700, Manasi Navare wrote: > Hi Ville, > > After the comments have been addressed, I have completed reviewing the > patches. Is there anything > else blocking this from getting merged? Could we get this merged if > everything looks good? Series pushed to drm-in

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for i915: Limit the length of an sg list to the requested length

On 20.09.2023 14:00, Patchwork wrote: *Patch Details* *Series:* i915: Limit the length of an sg list to the requested length *URL:* https://patchwork.freedesktop.org/series/123940/ *State:*failure *Details:* https://intel-gfx-ci.

Re: [Intel-gfx] [PATCH 00/10] drm/i915/spi: spi access for discrete graphics

> > On Wed, Sep 20, 2023 at 01:52:07PM +, Usyskin, Alexander wrote: > > > I've tried to register spi controller with a spi-mem ops, but I can't find > > a way > to connect to mtd subsystem. > > I took spi-intel as example, which connects to spi-nor but it relies on > > JDEC ID > of flash

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: add a note about fec_enable with 128b/132b

== Series Details == Series: drm/i915: add a note about fec_enable with 128b/132b URL : https://patchwork.freedesktop.org/series/123977/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13656_full -> Patchwork_123977v1_full Su

[Intel-gfx] ✓ Fi.CI.BAT: success for Update GGTT with MI_UPDATE_GTT on MTL (rev8)

== Series Details == Series: Update GGTT with MI_UPDATE_GTT on MTL (rev8) URL : https://patchwork.freedesktop.org/series/123329/ State : success == Summary == CI Bug Log - changes from CI_DRM_13658 -> Patchwork_123329v8 Summary --- *

Re: [Intel-gfx] [PATCH v2] drm/i915: refactor deprecated strncpy

On Tue, Sep 19, 2023 at 04:45:31AM +, Justin Stitt wrote: > `strncpy` is deprecated for use on NUL-terminated destination strings [1]. > > We should prefer more robust and less ambiguous string interfaces. > > A suitable replacement is `strscpy` [2] due to the fact that it > guarantees NUL-te

[Intel-gfx] [PATCH v12 0/4] Apply Wa_16018031267 / Wa_16018063123

Apply Wa_16018031267 / Wa_16018063123. This necessitates submitting a fastcolor blit as WABB and setting the copy engine arbitration to round-robin mode. v2: - Rename old platform check in second patch to match declaration in first patch. - Refactor second patch name to match first patch. v3:

[Intel-gfx] [PATCH v12 2/4] drm/i915: Reserve some kernel space per vm

Reserve two pages in each vm for kernel space to use for things such as workarounds. Signed-off-by: Jonathan Cavitt Suggested-by: Chris Wilson --- drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 7 +++ drivers/gpu/drm/i915/gt/intel_gtt.h | 1 + 2 files changed, 8 insertions(+) diff --git a/drivers

[Intel-gfx] [PATCH v12 1/4] drm/i915: Enable NULL PTE support for vm scratch

Enable NULL PTE support for vm scratch pages. The use of NULL PTEs in teh vm scratch pages requires us to change how the i915 gem_contexts live selftest perform vm_isolation: instead of checking the scratch pages are isolated and don't affect each other, we check that all changes to the scratch pa

[Intel-gfx] [PATCH v12 4/4] drm/i915: Set copy engine arbitration for Wa_16018031267 / Wa_16018063123

Set copy engine arbitration into round robin mode for part of Wa_16018031267 / Wa_16018063123 mitigation. Signed-off-by: Nirmoy Das Signed-off-by: Jonathan Cavitt --- drivers/gpu/drm/i915/gt/intel_engine_regs.h | 3 +++ drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 + 2 files changed, 8 i

[Intel-gfx] [PATCH v12 3/4] drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123

Apply WABB blit for Wa_16018031267 / Wa_16018063123. Additionally, update the lrc selftest to exercise the new WABB changes. Co-developed-by: Nirmoy Das Signed-off-by: Jonathan Cavitt --- drivers/gpu/drm/i915/gt/intel_engine_regs.h | 3 + drivers/gpu/drm/i915/gt/intel_gt.h | 4 + d

[Intel-gfx] [PATCH v2 1/2] drm/edid: Fixup h/vsync_end instead of h/vtotal

From: Ville Syrjälä There are some weird EDIDs floating around that have the sync pulse extending beyond the end of the blanking period. On the currently problemtic machine (HP Omni 120) EDID reports the following mode: "1600x900": 60 108000 1600 1780 1860 1800 900 910 913 1000 0x40 0x5 which is

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