[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tc: Add a workaround for an IOM/TCSS firmware hang issue (rev13)

== Series Details == Series: drm/i915/tc: Add a workaround for an IOM/TCSS firmware hang issue (rev13) URL : https://patchwork.freedesktop.org/series/117004/ State : success == Summary == CI Bug Log - changes from CI_DRM_13143 -> Patchwork_117004v13 ===

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/hwmon: Silence UBSAN uninitialized bool variable warning (rev2)

== Series Details == Series: drm/i915/hwmon: Silence UBSAN uninitialized bool variable warning (rev2) URL : https://patchwork.freedesktop.org/series/117591/ State : success == Summary == CI Bug Log - changes from CI_DRM_13143 -> Patchwork_117591v2 ==

Re: [Intel-gfx] [PATCH 4/6] drm/i915/pmu: Add reference counting to the sampling timer

On Fri, 05 May 2023 17:58:14 -0700, Umesh Nerlige Ramappa wrote: > Hi Umesh/Tvrtko, > From: Tvrtko Ursulin > > We do not want to have timers per tile and waste CPU cycles and energy via > multiple wake-up sources, for a relatively un-important task of PMU > sampling, so keeping a single timer wo

Re: [Intel-gfx] [PATCH 5/6] drm/i915/pmu: Prepare for multi-tile non-engine counters

On Fri, May 12, 2023 at 01:57:59PM -0700, Umesh Nerlige Ramappa wrote: On Fri, May 12, 2023 at 11:56:18AM +0100, Tvrtko Ursulin wrote: On 12/05/2023 02:08, Dixit, Ashutosh wrote: On Fri, 05 May 2023 17:58:15 -0700, Umesh Nerlige Ramappa wrote: From: Tvrtko Ursulin Reserve some bits in the

Re: [Intel-gfx] [PATCH 4/6] drm/i915/pmu: Add reference counting to the sampling timer

On Fri, May 12, 2023 at 03:29:03PM -0700, Dixit, Ashutosh wrote: On Fri, 05 May 2023 17:58:14 -0700, Umesh Nerlige Ramappa wrote: Hi Umesh/Tvrtko, From: Tvrtko Ursulin We do not want to have timers per tile and waste CPU cycles and energy via multiple wake-up sources, for a relatively un-

Re: [Intel-gfx] [PATCH] drm/i915: RFC: Introduce Wa_14011282866

On Wed, May 10, 2023 at 02:58:11PM -0700, Matt Atwood wrote: > From: Tilak Tangudu > > Wa_14011282866 applies to RKL, ADL-S, ADL-P and TGL. Wa_14011282866 isn't a valid workaround number. > > Allocate buffer pinned to GGTT and add WA to restore sampler power > context. > > Bspec: 46247 > > S

Re: [Intel-gfx] [PATCH 4/6] drm/i915/pmu: Add reference counting to the sampling timer

On Fri, 12 May 2023 15:44:00 -0700, Umesh Nerlige Ramappa wrote: > > On Fri, May 12, 2023 at 03:29:03PM -0700, Dixit, Ashutosh wrote: > > On Fri, 05 May 2023 17:58:14 -0700, Umesh Nerlige Ramappa wrote: > >> > > > > Hi Umesh/Tvrtko, > > > >> From: Tvrtko Ursulin > >> > >> We do not want to have ti

[Intel-gfx] [PATCH v8 0/2] drm/i915: Allow user to set cache at BO creation

From: Fei Yang The first three patches in this series are taken from https://patchwork.freedesktop.org/series/116868/ These patches are included here because the last patch has dependency on the pat_index refactor. This series is focusing on uAPI changes, 1. end support for set caching ioctl [PA

[Intel-gfx] [PATCH v8 2/2] drm/i915: Allow user to set cache at BO creation

From: Fei Yang To comply with the design that buffer objects shall have immutable cache setting through out their life cycle, {set, get}_caching ioctl's are no longer supported from MTL onward. With that change caching policy can only be set at object creation time. The current code applies a def

[Intel-gfx] [PATCH v8 1/2] drm/i915/mtl: end support for set caching ioctl

From: Fei Yang The design is to keep Buffer Object's caching policy immutable through out its life cycle. This patch ends the support for set caching ioctl from MTL onward. While doing that we also set BO's to be 1-way coherent at creation time because GPU is no longer automatically snooping CPU

Re: [Intel-gfx] [PATCH v7 4/4] drm/i915: Allow user to set cache at BO creation

> On 2023-05-10 15:14:16, Andi Shyti wrote: >> Hi, >> >> On Tue, May 09, 2023 at 09:59:42AM -0700, fei.y...@intel.com wrote: >>> From: Fei Yang >>> >>> To comply with the design that buffer objects shall have immutable >>> cache setting through out their life cycle, {set, get}_caching ioctl's >>>

Re: [Intel-gfx] [PATCH 4/6] drm/i915/pmu: Add reference counting to the sampling timer

On Fri, May 12, 2023 at 04:20:19PM -0700, Dixit, Ashutosh wrote: On Fri, 12 May 2023 15:44:00 -0700, Umesh Nerlige Ramappa wrote: On Fri, May 12, 2023 at 03:29:03PM -0700, Dixit, Ashutosh wrote: > On Fri, 05 May 2023 17:58:14 -0700, Umesh Nerlige Ramappa wrote: >> > > Hi Umesh/Tvrtko, > >> From

[Intel-gfx] [PATCH] drm/i915/guc/slpc: Disable rps_boost debugfs

rps_boost debugfs shows host turbo related info. This is not valid when SLPC is enabled. guc_slpc_info already shows the number of boosts. Add num_waiters there as well and disable rps_boost when SLPC is enabled. Bug: https://gitlab.freedesktop.org/drm/intel/-/issues/7632 Signed-off-by: Vinay Belg

[Intel-gfx] [PATCH] drm/i915/selftest/gsc: Ensure GSC Proxy init completes before selftests

On MTL, if the GSC Proxy init flows haven't completed, submissions to the GSC engine will fail. Those init flows are dependent on the mei's gsc_proxy component that is loaded in parallel with i915 and a worker that could potentially start after i915 driver init is done. That said, all subsytems th

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/4] drm/i915/dpll: drop a useless I915_STATE_WARN_ON() (rev2)

== Series Details == Series: series starting with [1/4] drm/i915/dpll: drop a useless I915_STATE_WARN_ON() (rev2) URL : https://patchwork.freedesktop.org/series/117685/ State : success == Summary == CI Bug Log - changes from CI_DRM_13143_full -> Patchwork_117685v2_full ===

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Allow user to set cache at BO creation (rev8)

== Series Details == Series: drm/i915: Allow user to set cache at BO creation (rev8) URL : https://patchwork.freedesktop.org/series/116870/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] [linux-next:master] BUILD SUCCESS WITH WARNING e922ba281a8d84f640d8c8e18a385d032c19e185

tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master branch HEAD: e922ba281a8d84f640d8c8e18a385d032c19e185 Add linux-next specific files for 20230512 Warning reports: https://lore.kernel.org/oe-kbuild-all/202305130809.sjnm01fl-...@intel.com Warning

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Allow user to set cache at BO creation (rev8)

== Series Details == Series: drm/i915: Allow user to set cache at BO creation (rev8) URL : https://patchwork.freedesktop.org/series/116870/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13143 -> Patchwork_116870v8 Summary -

[Intel-gfx] [PATCH v3 00/28] drm/i915/gvt: KVM: KVMGT fixes and page-track cleanups

Fix a variety of found-by-inspection bugs in KVMGT, and overhaul KVM's page-track APIs to provide a leaner and cleaner interface. The motivation for this series is to (significantly) reduce the number of KVM APIs that KVMGT uses, with a long-term goal of making all kvm_host.h headers KVM-internal.

[Intel-gfx] [PATCH v3 01/28] drm/i915/gvt: Verify pfn is "valid" before dereferencing "struct page"

Check that the pfn found by gfn_to_pfn() is actually backed by "struct page" memory prior to retrieving and dereferencing the page. KVM supports backing guest memory with VM_PFNMAP, VM_IO, etc., and so there is no guarantee the pfn returned by gfn_to_pfn() has an associated "struct page". Fixes:

[Intel-gfx] [PATCH v3 02/28] drm/i915/gvt: remove interface intel_gvt_is_valid_gfn

From: Yan Zhao Currently intel_gvt_is_valid_gfn() is called in two places: (1) shadowing guest GGTT entry (2) shadowing guest PPGTT leaf entry, which was introduced in commit cc753fbe1ac4 ("drm/i915/gvt: validate gfn before set shadow page entry"). However, now it's not necessary to call this in

[Intel-gfx] [PATCH v3 03/28] drm/i915/gvt: Verify hugepages are contiguous in physical address space

When shadowing a GTT entry with a 2M page, verify that the pfns are contiguous, not just that the struct page pointers are contiguous. The memory map is virtual contiguous if "CONFIG_FLATMEM=y || CONFIG_SPARSEMEM_VMEMMAP=y", but not for "CONFIG_SPARSEMEM=y && CONFIG_SPARSEMEM_VMEMMAP=n", so theore

[Intel-gfx] [PATCH v3 04/28] drm/i915/gvt: Put the page reference obtained by KVM's gfn_to_pfn()

Put the struct page reference acquired by gfn_to_pfn(), KVM's API is that the caller is ultimately responsible for dropping any reference. Note, kvm_release_pfn_clean() ensures the pfn is actually a refcounted struct page before trying to put any references. Fixes: b901b252b6cf ("drm/i915/gvt: Ad

[Intel-gfx] [PATCH v3 05/28] drm/i915/gvt: Explicitly check that vGPU is attached before shadowing

Move the check that a vGPU is attacked from is_2MB_gtt_possible() to its sole caller, ppgtt_populate_shadow_entry(). All of the paths in ppgtt_populate_shadow_entry() eventually check for attachment by way of intel_gvt_dma_map_guest_page(), but explicitly checking can avoid unnecessary work and wi

[Intel-gfx] [PATCH v3 06/28] drm/i915/gvt: Error out on an attempt to shadowing an unknown GTT entry type

Bail from ppgtt_populate_shadow_entry() if an unexpected GTT entry type is encountered instead of subtly falling through to the common "direct shadow" path. Eliminating the default/error path's reliance on the common handling will allow hoisting intel_gvt_dma_map_guest_page() into the case stateme

[Intel-gfx] [PATCH v3 08/28] drm/i915/gvt: Use an "unsigned long" to iterate over memslot gfns

Use an "unsigned long" instead of an "int" when iterating over the gfns in a memslot. The number of pages in the memslot is tracked as an "unsigned long", e.g. KVMGT could theoretically break if a KVM memslot larger than 16TiB were deleted (2^32 * 4KiB). Reviewed-by: Yan Zhao Signed-off-by: Sean

[Intel-gfx] [PATCH v3 07/28] drm/i915/gvt: Don't rely on KVM's gfn_to_pfn() to query possible 2M GTT

Now that gvt_pin_guest_page() explicitly verifies the pinned PFN is a transparent hugepage page, don't use KVM's gfn_to_pfn() to pre-check if a 2MiB GTT entry is possible and instead just try to map the GFN with a 2MiB entry. Using KVM to query pfn that is ultimately managed through VFIO is odd, a

[Intel-gfx] [PATCH v3 11/28] KVM: x86/mmu: Move kvm_arch_flush_shadow_{all, memslot}() to mmu.c

Move x86's implementation of kvm_arch_flush_shadow_{all,memslot}() into mmu.c, and make kvm_mmu_zap_all() static as it was globally visible only for kvm_arch_flush_shadow_all(). This will allow refactoring kvm_arch_flush_shadow_memslot() to call kvm_mmu_zap_all() directly without having to expose

[Intel-gfx] [PATCH v3 10/28] drm/i915/gvt: Protect gfn hash table with vgpu_lock

Use vgpu_lock instead of KVM's mmu_lock to protect accesses to the hash table used to track which gfns are write-protected when shadowing the guest's GTT, and hoist the acquisition of vgpu_lock from intel_vgpu_page_track_handler() out to its sole caller, kvmgt_page_track_write(). This fixes a bug

[Intel-gfx] [PATCH v3 12/28] KVM: x86/mmu: Don't rely on page-track mechanism to flush on memslot change

Call kvm_mmu_zap_all_fast() directly when flushing a memslot instead of bouncing through the page-track mechanism. KVM (unfortunately) needs to zap and flush all page tables on memslot DELETE/MOVE irrespective of whether KVM is shadowing guest page tables. This will allow changing KVM to register

[Intel-gfx] [PATCH v3 09/28] drm/i915/gvt: Drop unused helper intel_vgpu_reset_gtt()

Drop intel_vgpu_reset_gtt() as it no longer has any callers. In addition to eliminating dead code, this eliminates the last possible scenario where __kvmgt_protect_table_find() can be reached without holding vgpu_lock. Requiring vgpu_lock to be held when calling __kvmgt_protect_table_find() will a

[Intel-gfx] [PATCH v3 14/28] KVM: drm/i915/gvt: Drop @vcpu from KVM's ->track_write() hook

Drop @vcpu from KVM's ->track_write() hook provided for external users of the page-track APIs now that KVM itself doesn't use the page-track mechanism. Reviewed-by: Yan Zhao Signed-off-by: Sean Christopherson --- arch/x86/include/asm/kvm_page_track.h | 5 ++--- arch/x86/kvm/mmu/page_track.c

[Intel-gfx] [PATCH v3 13/28] KVM: x86/mmu: Don't bounce through page-track mechanism for guest PTEs

Don't use the generic page-track mechanism to handle writes to guest PTEs in KVM's MMU. KVM's MMU needs access to information that should not be exposed to external page-track users, e.g. KVM needs (for some definitions of "need") the vCPU to query the current paging mode, whereas external users,

[Intel-gfx] [PATCH v3 16/28] drm/i915/gvt: Don't bother removing write-protection on to-be-deleted slot

When handling a slot "flush", don't call back into KVM to drop write protection for gfns in the slot. Now that KVM rejects attempts to move memory slots while KVMGT is attached, the only time a slot is "flushed" is when it's being removed, i.e. the memslot and all its write-tracking metadata is ab

[Intel-gfx] [PATCH v3 18/28] drm/i915/gvt: switch from ->track_flush_slot() to ->track_remove_region()

From: Yan Zhao Switch from the poorly named and flawed ->track_flush_slot() to the newly introduced ->track_remove_region(). From KVMGT's perspective, the two hooks are functionally equivalent, the only difference being that ->track_remove_region() is called only when KVM is 100% certain the mem

[Intel-gfx] [PATCH v3 19/28] KVM: x86: Remove the unused page-track hook track_flush_slot()

From: Yan Zhao Remove ->track_remove_slot(), there are no longer any users and it's unlikely a "flush" hook will ever be the correct API to provide to an external page-track user. Cc: Zhenyu Wang Suggested-by: Sean Christopherson Signed-off-by: Yan Zhao Signed-off-by: Sean Christopherson ---

[Intel-gfx] [PATCH v3 15/28] KVM: x86: Reject memslot MOVE operations if KVMGT is attached

Disallow moving memslots if the VM has external page-track users, i.e. if KVMGT is being used to expose a virtual GPU to the guest, as KVMGT doesn't correctly handle moving memory regions. Note, this is potential ABI breakage! E.g. userspace could move regions that aren't shadowed by KVMGT withou

[Intel-gfx] [PATCH v3 17/28] KVM: x86: Add a new page-track hook to handle memslot deletion

From: Yan Zhao Add a new page-track hook, track_remove_region(), that is called when a memslot DELETE operation is about to be committed. The "remove" hook will be used by KVMGT and will effectively replace the existing track_flush_slot() altogether now that KVM itself doesn't rely on the "flush

[Intel-gfx] [PATCH v3 23/28] KVM: x86/mmu: Rename page-track APIs to reflect the new reality

Rename the page-track APIs to capture that they're all about tracking writes, now that the facade of supporting multiple modes is gone. Opportunstically replace "slot" with "gfn" in anticipation of removing the @slot param from the external APIs. No functional change intended. Signed-off-by: Sea

[Intel-gfx] [PATCH v3 20/28] KVM: x86/mmu: Move KVM-only page-track declarations to internal header

Bury the declaration of the page-track helpers that are intended only for internal KVM use in a "private" header. In addition to guarding against unwanted usage of the internal-only helpers, dropping their definitions avoids exposing other structures that should be KVM-internal, e.g. for memslots.

[Intel-gfx] [PATCH v3 24/28] KVM: x86/mmu: Assert that correct locks are held for page write-tracking

When adding/removing gfns to/from write-tracking, assert that mmu_lock is held for write, and that either slots_lock or kvm->srcu is held. mmu_lock must be held for write to protect gfn_write_track's refcount, and SRCU or slots_lock must be held to protect the memslot itself. Tested-by: Yan Zhao

[Intel-gfx] [PATCH v3 21/28] KVM: x86/mmu: Use page-track notifiers iff there are external users

Disable the page-track notifier code at compile time if there are no external users, i.e. if CONFIG_KVM_EXTERNAL_WRITE_TRACKING=n. KVM itself now hooks emulated writes directly instead of relying on the page-track mechanism. Provide a stub for "struct kvm_page_track_notifier_node" so that includi

[Intel-gfx] [PATCH v3 26/28] KVM: x86/mmu: Drop @slot param from exported/external page-track APIs

Refactor KVM's exported/external page-track, a.k.a. write-track, APIs to take only the gfn and do the required memslot lookup in KVM proper. Forcing users of the APIs to get the memslot unnecessarily bleeds KVM internals into KVMGT and complicates usage of the APIs. No functional change intended.

[Intel-gfx] [PATCH v3 28/28] drm/i915/gvt: Drop final dependencies on KVM internal details

Open code gpa_to_gfn() in kvmgt_page_track_write() and drop KVMGT's dependency on kvm_host.h, i.e. include only kvm_page_track.h. KVMGT assumes "gfn == gpa >> PAGE_SHIFT" all over the place, including a few lines below in the same function with the same gpa, i.e. there's no reason to use KVM's hel

[Intel-gfx] [PATCH v3 22/28] KVM: x86/mmu: Drop infrastructure for multiple page-track modes

Drop "support" for multiple page-track modes, as there is no evidence that array-based and refcounted metadata is the optimal solution for other modes, nor is there any evidence that other use cases, e.g. for access-tracking, will be a good fit for the page-track machinery in general. E.g. one pot

[Intel-gfx] [PATCH v3 25/28] KVM: x86/mmu: Bug the VM if write-tracking is used but not enabled

Bug the VM if something attempts to write-track a gfn, but write-tracking isn't enabled. The VM is doomed (and KVM has an egregious bug) if KVM or KVMGT wants to shadow guest page tables but can't because write-tracking isn't enabled. Signed-off-by: Sean Christopherson --- arch/x86/kvm/mmu/page

[Intel-gfx] [PATCH v3 27/28] KVM: x86/mmu: Handle KVM bookkeeping in page-track APIs, not callers

Get/put references to KVM when a page-track notifier is (un)registered instead of relying on the caller to do so. Forcing the caller to do the bookkeeping is unnecessary and adds one more thing for users to get wrong, e.g. see commit 9ed1fdee9ee3 ("drm/i915/gvt: Get reference to KVM iff attachment

Re: [Intel-gfx] [PATCH v2] drm/i915/huc: Parse the GSC-enabled HuC binary

On Tue, 2023-05-02 at 08:27 -0700, Ceraolo Spurio, Daniele wrote: > The new binaries that support the 2-step authentication have contain the > legacy-style binary, which we can use for loading the HuC via DMA. To > find out where this is located in the image, we need to parse the meu > manifest of

Re: [Intel-gfx] [PATCH] drm/i915/guc/slpc: Disable rps_boost debugfs

On Fri, 12 May 2023 16:56:03 -0700, Vinay Belgaumkar wrote: > Hi Vinay, > rps_boost debugfs shows host turbo related info. This is not valid > when SLPC is enabled. A couple of thoughts about this. It appears people are know only about rps_boost_info and don't know about guc_slpc_info? So: a. I

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/guc/slpc: Disable rps_boost debugfs

== Series Details == Series: drm/i915/guc/slpc: Disable rps_boost debugfs URL : https://patchwork.freedesktop.org/series/117711/ State : warning == Summary == Error: dim checkpatch failed 0cd47cc8985c drm/i915/guc/slpc: Disable rps_boost debugfs -:11: WARNING:COMMIT_LOG_USE_LINK: Unknown link

Re: [Intel-gfx] [PATCH v2 5/8] drm/i915/huc: differentiate the 2 steps of the MTL HuC auth flow

On Fri, 2023-04-28 at 11:58 -0700, Ceraolo Spurio, Daniele wrote: > Before we add the second step of the MTL HuC auth (via GSC), we need to > have the ability to differentiate between them. To do so, the huc > authentication check is duplicated for GuC and GSC auth, with meu > binaries being consid

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc/slpc: Disable rps_boost debugfs

== Series Details == Series: drm/i915/guc/slpc: Disable rps_boost debugfs URL : https://patchwork.freedesktop.org/series/117711/ State : success == Summary == CI Bug Log - changes from CI_DRM_13143 -> Patchwork_117711v1 Summary --- *

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/tc: Add a workaround for an IOM/TCSS firmware hang issue (rev13)

== Series Details == Series: drm/i915/tc: Add a workaround for an IOM/TCSS firmware hang issue (rev13) URL : https://patchwork.freedesktop.org/series/117004/ State : success == Summary == CI Bug Log - changes from CI_DRM_13143_full -> Patchwork_117004v13_full =

Re: [Intel-gfx] [PATCH 5/6] drm/i915/pmu: Prepare for multi-tile non-engine counters

On Fri, 12 May 2023 13:57:59 -0700, Umesh Nerlige Ramappa wrote: > > On Fri, May 12, 2023 at 11:56:18AM +0100, Tvrtko Ursulin wrote: > > > > On 12/05/2023 02:08, Dixit, Ashutosh wrote: > >> On Fri, 05 May 2023 17:58:15 -0700, Umesh Nerlige Ramappa wrote: > >>> > >>> From: Tvrtko Ursulin > >>> > >>

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftest/gsc: Ensure GSC Proxy init completes before selftests

== Series Details == Series: drm/i915/selftest/gsc: Ensure GSC Proxy init completes before selftests URL : https://patchwork.freedesktop.org/series/117713/ State : warning == Summary == Error: dim checkpatch failed b97349ae2b23 drm/i915/selftest/gsc: Ensure GSC Proxy init completes before sel

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftest/gsc: Ensure GSC Proxy init completes before selftests

== Series Details == Series: drm/i915/selftest/gsc: Ensure GSC Proxy init completes before selftests URL : https://patchwork.freedesktop.org/series/117713/ State : success == Summary == CI Bug Log - changes from CI_DRM_13143 -> Patchwork_117713v1 ===

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gvt: KVM: KVMGT fixes and page-track cleanups (rev8)

== Series Details == Series: drm/i915/gvt: KVM: KVMGT fixes and page-track cleanups (rev8) URL : https://patchwork.freedesktop.org/series/112196/ State : warning == Summary == Error: dim checkpatch failed 7ddfeb73c37a drm/i915/gvt: Verify pfn is "valid" before dereferencing "struct page" 6e46

[Intel-gfx] [PATCH 4/6] drm/i915/pmu: Add reference counting to the sampling timer

From: Tvrtko Ursulin We do not want to have timers per tile and waste CPU cycles and energy via multiple wake-up sources, for a relatively un-important task of PMU sampling, so keeping a single timer works well. But we also do not want the first GT which goes idle to turn off the timer. Add some

[Intel-gfx] [PATCH 2/6] drm/i915/pmu: Skip sampling engines with no enabled counters

From: Tvrtko Ursulin As we have more and more engines do not waste time sampling the ones no- one is monitoring. Signed-off-by: Tvrtko Ursulin Reviewed-by: Umesh Nerlige Ramappa Signed-off-by: Umesh Nerlige Ramappa --- drivers/gpu/drm/i915/i915_pmu.c | 3 +++ 1 file changed, 3 insertions(+)

[Intel-gfx] [PATCH 6/6] drm/i915/pmu: Export counters from all tiles

From: Tvrtko Ursulin Start exporting frequency and RC6 counters from all tiles. Existing counters keep their names and config values and new one use the namespace added in the previous patch, with the "-gtN" added to their names. Interrupts counter is an odd one off. Because it is the global de

[Intel-gfx] [PATCH 1/6] drm/i915/pmu: Support PMU for all engines

From: Tvrtko Ursulin Given how the metrics are already exported, we also need to run sampling over engines from all GTs. Problem of GT frequencies is left for later. Signed-off-by: Tvrtko Ursulin Reviewed-by: Umesh Nerlige Ramappa Signed-off-by: Umesh Nerlige Ramappa --- drivers/gpu/drm/i91

[Intel-gfx] [PATCH 3/6] drm/i915/pmu: Transform PMU parking code to be GT based

From: Tvrtko Ursulin Trivial prep work for full multi-tile enablement later. Signed-off-by: Tvrtko Ursulin Signed-off-by: Vinay Belgaumkar Reviewed-by: Umesh Nerlige Ramappa Signed-off-by: Umesh Nerlige Ramappa --- drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 ++-- drivers/gpu/drm/i915/i915_p

[Intel-gfx] [PATCH 0/6] Add MTL PMU support for multi-gt

With MTL, frequency and rc6 counters are specific to a gt. Export these counters via gt-specific events to the user space. v2: Review comments (Ashutosh, Tvrtko) Signed-off-by: Umesh Nerlige Ramappa Tvrtko Ursulin (6): drm/i915/pmu: Support PMU for all engines drm/i915/pmu: Skip sampling en

[Intel-gfx] [PATCH 5/6] drm/i915/pmu: Prepare for multi-tile non-engine counters

From: Tvrtko Ursulin Reserve some bits in the counter config namespace which will carry the tile id and prepare the code to handle this. No per tile counters have been added yet. v2: - Fix checkpatch issues - Use 4 bits for gt id in non-engine counters. Drop FIXME. - Set MAX GTs to 4. Drop FIXM

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gvt: KVM: KVMGT fixes and page-track cleanups (rev8)

== Series Details == Series: drm/i915/gvt: KVM: KVMGT fixes and page-track cleanups (rev8) URL : https://patchwork.freedesktop.org/series/112196/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13143 -> Patchwork_112196v8 Sum

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/hwmon: Silence UBSAN uninitialized bool variable warning (rev2)

== Series Details == Series: drm/i915/hwmon: Silence UBSAN uninitialized bool variable warning (rev2) URL : https://patchwork.freedesktop.org/series/117591/ State : success == Summary == CI Bug Log - changes from CI_DRM_13143_full -> Patchwork_117591v2_full

[Intel-gfx] [PATCH v2 2/2] drm/i915/mtl: Add MTL performance tuning changes

MTL reuses the tuning parameters for DG2. Extend the dg2 performance tuning parameters to MTL. v2: Add DRAW_WATERMARK tuning parameter. Bspec: 68331 Cc: Haridhar Kalvala Cc: Matt Roper Cc: Gustavo Sousa Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 +

[Intel-gfx] [PATCH v2 1/2] drm/i915/mtl: Extend Wa_16014892111 to MTL A-step

The dg2 workaround which is used for performance tuning is needed for Meteorlake A-step. v2: Limit the WA for A-step Bspec: 68331 Cc: Haridhar Kalvala Cc: Matt Roper Cc: Gustavo Sousa Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +++- 1 file changed, 3 inse

Re: [Intel-gfx] [PATCH 4/6] drm/i915/pmu: Add reference counting to the sampling timer

On Fri, 12 May 2023 18:55:43 -0700, Umesh Nerlige Ramappa wrote: > > From: Tvrtko Ursulin > > We do not want to have timers per tile and waste CPU cycles and energy via > multiple wake-up sources, for a relatively un-important task of PMU > sampling, so keeping a single timer works well. But we al

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add MTL PMU support for multi-gt (rev3)

== Series Details == Series: Add MTL PMU support for multi-gt (rev3) URL : https://patchwork.freedesktop.org/series/115836/ State : warning == Summary == Error: dim checkpatch failed 676522fb00c9 drm/i915/pmu: Support PMU for all engines 61ea4272bfb6 drm/i915/pmu: Skip sampling engines with no

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add MTL PMU support for multi-gt (rev3)

== Series Details == Series: Add MTL PMU support for multi-gt (rev3) URL : https://patchwork.freedesktop.org/series/115836/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.BAT: failure for Add MTL PMU support for multi-gt (rev3)

== Series Details == Series: Add MTL PMU support for multi-gt (rev3) URL : https://patchwork.freedesktop.org/series/115836/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13143 -> Patchwork_115836v3 Summary --- **FAIL

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v2,1/2] drm/i915/mtl: Extend Wa_16014892111 to MTL A-step

== Series Details == Series: series starting with [v2,1/2] drm/i915/mtl: Extend Wa_16014892111 to MTL A-step URL : https://patchwork.freedesktop.org/series/117717/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separa

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/guc/slpc: Disable rps_boost debugfs

== Series Details == Series: drm/i915/guc/slpc: Disable rps_boost debugfs URL : https://patchwork.freedesktop.org/series/117711/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13143_full -> Patchwork_117711v1_full Summary --

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2,1/2] drm/i915/mtl: Extend Wa_16014892111 to MTL A-step

== Series Details == Series: series starting with [v2,1/2] drm/i915/mtl: Extend Wa_16014892111 to MTL A-step URL : https://patchwork.freedesktop.org/series/117717/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13143 -> Patchwork_117717v1 ==

Re: [Intel-gfx] [PATCH 5/6] drm/i915/pmu: Prepare for multi-tile non-engine counters

On Fri, 12 May 2023 18:55:44 -0700, Umesh Nerlige Ramappa wrote: > > From: Tvrtko Ursulin > > Reserve some bits in the counter config namespace which will carry the > tile id and prepare the code to handle this. > > No per tile counters have been added yet. > > v2: > - Fix checkpatch issues > - Us

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/selftest/gsc: Ensure GSC Proxy init completes before selftests

== Series Details == Series: drm/i915/selftest/gsc: Ensure GSC Proxy init completes before selftests URL : https://patchwork.freedesktop.org/series/117713/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13143_full -> Patchwork_117713v1_full =

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