[Intel-gfx] ✗ Fi.CI.SPARSE: warning for mtl: add support for pmdemand (rev5)

== Series Details == Series: mtl: add support for pmdemand (rev5) URL : https://patchwork.freedesktop.org/series/116949/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

Re: [Intel-gfx] [PATCH v11 0/8] drm/i915/pxp: Add MTL PXP Support

Thank you for the patches and the reviews. Pushed. - Radhakrishna(RK) Sripada > -Original Message- > From: dri-devel On Behalf Of Alan > Previn > Sent: Thursday, May 11, 2023 4:18 PM > To: intel-gfx@lists.freedesktop.org > Cc: Teres Alexis, Alan Previn ; Ursulin, > Tvrtko ; Juston Li ; d

[Intel-gfx] ✓ Fi.CI.BAT: success for mtl: add support for pmdemand (rev5)

== Series Details == Series: mtl: add support for pmdemand (rev5) URL : https://patchwork.freedesktop.org/series/116949/ State : success == Summary == CI Bug Log - changes from CI_DRM_13139 -> Patchwork_116949v5 Summary --- **WARNING

Re: [Intel-gfx] [PATCH 5/6] drm/i915/pmu: Prepare for multi-tile non-engine counters

On Fri, 05 May 2023 17:58:15 -0700, Umesh Nerlige Ramappa wrote: > > From: Tvrtko Ursulin > > Reserve some bits in the counter config namespace which will carry the > tile id and prepare the code to handle this. > > No per tile counters have been added yet. > > v2: > - Fix checkpatch issues > - Us

[Intel-gfx] [PATCH] drm/i915/guc: Fix confused register capture list creation

From: John Harrison The GuC has a completely separate engine class enum when referring to register capture lists, which combines render and compute. The driver was using the 'normal' GuC specific engine class enum instead. That meant that it thought it was defining a capture list for compute engi

[Intel-gfx] [PATCH] drm/i915/pmu: Turn off the timer to sample frequencies when GT is parked

pmu_needs_timer() keeps the timer running even when GT is parked, ostensibly to sample requested/actual frequencies. However frequency_sample() has the following: /* Report 0/0 (actual/requested) frequency while parked. */ if (!intel_gt_pm_get_if_awake(gt)) return;

Re: [Intel-gfx] [PATCH] drm/i915/guc: Fix confused register capture list creation

On Thu, 2023-05-11 at 18:35 -0700, john.c.harri...@intel.com wrote: > From: John Harrison > > The GuC has a completely separate engine class enum when referring to > register capture lists, which combines render and compute. The driver > was using the 'normal' GuC specific engine class enum inste

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/guc: Fix confused register capture list creation

== Series Details == Series: drm/i915/guc: Fix confused register capture list creation URL : https://patchwork.freedesktop.org/series/117655/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Fix confused register capture list creation

== Series Details == Series: drm/i915/guc: Fix confused register capture list creation URL : https://patchwork.freedesktop.org/series/117655/ State : success == Summary == CI Bug Log - changes from CI_DRM_13140 -> Patchwork_117655v1 Summary

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/pmu: Turn off the timer to sample frequencies when GT is parked

== Series Details == Series: drm/i915/pmu: Turn off the timer to sample frequencies when GT is parked URL : https://patchwork.freedesktop.org/series/117658/ State : success == Summary == CI Bug Log - changes from CI_DRM_13140 -> Patchwork_117658v1 ==

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: drop dependency on VLV_DISPLAY_BASE (rev2)

== Series Details == Series: drm/i915/gt: drop dependency on VLV_DISPLAY_BASE (rev2) URL : https://patchwork.freedesktop.org/series/117620/ State : success == Summary == CI Bug Log - changes from CI_DRM_13138_full -> Patchwork_117620v2_full

Re: [Intel-gfx] [PATCH v2 25/27] KVM: x86/mmu: Drop @slot param from exported/external page-track APIs

> > Hi Sean, > > After more thoughts, do you think checking KVM internal memslot is > > necessary? > > I don't think it's necessary per se, but I also can't think of any reason to > allow > it. > > > slot = gfn_to_memslot(kvm, gfn); > > if (!slot || slot->id >= KVM_USER_MEM_SLOTS) { > >

[Intel-gfx] [PATCH] drm/i915/gt: Add workaround 14016712196

Wa_14016712196 implementation for mtl Bspec: 72197 Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 38 1 file changed, 38 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c index

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/pxp: Add MTL PXP Support (rev12)

== Series Details == Series: drm/i915/pxp: Add MTL PXP Support (rev12) URL : https://patchwork.freedesktop.org/series/112647/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13139_full -> Patchwork_112647v12_full Summary

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/gt: Add workaround 14016712196

== Series Details == Series: drm/i915/gt: Add workaround 14016712196 URL : https://patchwork.freedesktop.org/series/117661/ State : failure == Summary == Error: make failed CALLscripts/checksyscalls.sh DESCEND objtool INSTALL libsubcmd_headers CC [M] drivers/gpu/drm/i915/gt/gen8_e

[Intel-gfx] [PATCH 00/13] DSC misc fixes

This series is an attempt to address multiple issues with DSC, scattered in separate existing series. Patches 1-3 are DSC fixes from series to Handle BPC for HDMI2.1 PCON https://patchwork.freedesktop.org/series/107550/ Patches 4-5 are from series DSC fixes for Bigjoiner: https://patchwork.freede

[Intel-gfx] [PATCH 01/13] drm/i915/dp: Consider output_format while computing dsc bpp

While using DSC the compressed bpp is computed assuming RGB output format. Consider the output_format and compute the compressed bpp during mode valid and compute config steps. For DP-MST we currently use RGB output format only, so continue using RGB while computing compressed bpp for MST case. v

[Intel-gfx] [PATCH 02/13] drm/i915/dp_mst: Use output_format to get the final link bpp

The final link bpp used to calculate the m_n values depend on the output_format. Though the output_format is set to RGB for MST case and the link bpp will be same as the pipe bpp, for the sake of semantics, lets calculate the m_n values with the link bpp, instead of pipe_bpp. Signed-off-by: Ankit

[Intel-gfx] [PATCH 03/13] drm/i915/dp: Use consistent name for link bpp and compressed bpp

Currently there are many places where we use output_bpp for link bpp and compressed bpp. Lets use consistent naming: output_bpp : The intermediate value taking into account the output_format chroma subsampling. compressed_bpp : target bpp for the DSC encoder. link_bpp : final bpp used in the link.

[Intel-gfx] [PATCH 04/13] drm/i915/dp: Update Bigjoiner interface bits for computing compressed bpp

In Bigjoiner check for DSC, bigjoiner interface bits for DP for DISPLAY > 13 is 36 (Bspec: 49259). v2: Corrected Display ver to 13. v3: Follow convention for conditional statement. (Ville) Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 3 ++- 1 file changed, 2 inse

[Intel-gfx] [PATCH 06/13] drm/i915/dp: Remove extra logs for printing DSC info

DSC compressed bpp and slice counts are already getting printed at the end of dsc compute config. Remove extra logs. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/

[Intel-gfx] [PATCH 05/13] drm/i915/intel_cdclk: Add vdsc with bigjoiner constraints on min_cdlck

As per Bsepc:49259, Bigjoiner BW check puts restriction on the compressed bpp for a given CDCLK, pixelclock in cases where Bigjoiner + DSC are used. Currently compressed bpp is computed first, and it is ensured that the bpp will work at least with the max CDCLK freq. Since the CDCLK is computed l

[Intel-gfx] [PATCH 08/13] drm/i915/dp: Avoid forcing DSC BPC for MST case

For MST the bpc is hardcoded to 8, and pipe bpp to 24. So avoid forcing DSC bpc for MST case. v2: Warn and ignore the debug flag than to bail out. (Jani) Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 11 +-- drivers/gpu/drm/i915/display/intel_dp_mst.c |

[Intel-gfx] [PATCH 07/13] drm/display/dp: Fix the DP DSC Receiver cap size

DP DSC Receiver Capabilities are exposed via DPCD 60h-6Fh. Fix the DSC RECEIVER CAP SIZE accordingly. Fixes: ffddc4363c28 ("drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT") Cc: Anusha Srivatsa Cc: Manasi Navare Cc: # v5.0+ Signed-off-by: Ankit Nautiyal --- include

[Intel-gfx] [PATCH 09/13] drm/i915/dp: Check min bpc DSC limits for dsc_force_bpc also

For DSC the min BPC is 8 for ICL+ and so the min pipe_bpp is 24. Check this condition for cases where bpc is forced by debugfs flag dsc_force_bpc. If the check fails, then WARN and ignore the debugfs flag. For MST case the pipe_bpp is already computed (hardcoded to be 24), and this check is not re

[Intel-gfx] [PATCH 10/13] drm/i915/dp: Avoid left shift of DSC output bpp by 4

To make way for fractional bpp support, avoid left shifting the output_bpp by 4 in helper intel_dp_dsc_get_output_bpp. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 12 drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- 2 files changed, 5 insertio

[Intel-gfx] [PATCH 11/13] drm/i915/dp: Rename helpers to get DSC max pipe_bpp/output_bpp

Currently the required dsc output bpp is set to be the largest compressed bpp supported for max, lane, rate, and bpp. The helper intel_dp_dsc_get_output_bpp gets the maximum supported compressed bpp taking into account link configuration, input bpp, bigjoiner considerations etc. Similarly, the hel

[Intel-gfx] [PATCH 12/13] drm/i915/dp: Get optimal link config to have best compressed bpp

Currently, we take the max lane, rate and pipe bpp, to get the maximum compressed bpp possible. We then set the output bpp to this value. This patch provides support to have max bpp, min rate and min lanes, that can support the min compressed bpp. v2: -Avoid ending up with compressed bpp, same as

[Intel-gfx] [PATCH 13/13] drm/i915: Query compressed bpp properly using correct DPCD and DP Spec info

From: Stanislav Lisovskiy Currently we seem to be using wrong DPCD register for reading compressed bpps, reading min/max input bpc instead of compressed bpp. Fix that, so that we now apply min/max compressed bpp limitations we get from DP Spec Table 2-157 DP v2.0 and/or correspondent DPCD registe

[Intel-gfx] ✓ Fi.CI.IGT: success for mtl: add support for pmdemand (rev5)

== Series Details == Series: mtl: add support for pmdemand (rev5) URL : https://patchwork.freedesktop.org/series/116949/ State : success == Summary == CI Bug Log - changes from CI_DRM_13139_full -> Patchwork_116949v5_full Summary ---

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