Hi,
On 19.04.2023 00:04, Radhakrishna Sripada wrote:
This series adds 2 MTL WA's and 2 patches to fix re-use
"DC off" power wells.
v2:
Haridhar Kalvala (1):
drm/i915/mtl: WA to clear RDOP clock gating
Madhumitha Tolakanahalli Pradeep (1):
drm/i915/mtl: Extend Wa_22011802037 to MTL A-step
> -Original Message-
> From: Sripada, Radhakrishna
> Sent: Saturday, April 22, 2023 2:24 AM
> To: Kahola, Mika
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 01/13] drm/i915/mtl: C20 PLL programming
>
> Hi Mika,
>
> On Thu, Apr 20, 2023 at 03:40:38PM +0300, Mika
On 23/04/2023 07:12, Yang, Fei wrote:
On 20/04/2023 00:00, fei.y...@intel.com wrote:
From: Fei Yang
Currently the KMD is using enum i915_cache_level to set caching policy
for buffer objects. This is flaky because the PAT index which really
controls the caching behavior in PTE has far more le
[fixed mailing lists addresses]
On 24/04/2023 09:36, Jordan Justen wrote:
On 2023-04-23 00:05:06, Yang, Fei wrote:
On 2023-04-20 09:11:18, Yang, Fei wrote:
On 20/04/2023 12:39, Andi Shyti wrote:
Hi Fei,
because this is an API change, we need some more information here.
First of all you ne
On 23/04/2023 07:52, Yang, Fei wrote:
On 20/04/2023 00:00, fei.y...@intel.com wrote:
From: Fei Yang
Currently the KMD is using enum i915_cache_level to set caching policy for
buffer objects. This is flaky because the PAT index which really controls
the caching behavior in PTE has far more le
WA 18018781329 is applicable now across all MTL
steppings.
V2:
- Remove IS_MTL check, code already running for MTL - Matt
Cc: Matt Roper
Signed-off-by: Tejas Upadhyay
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 30 ++---
1 file changed, 14 insertions(+), 16 deletions(-)
On Sun, 23 Apr 2023, Andi Shyti wrote:
> Hi,
>
> On Fri, Apr 21, 2023 at 03:46:52PM +0200, Andi Shyti wrote:
>> Hi,
>>
>> just another "Friday patch". While reviewing some patches from
>> Tejas I found a bit confusing the use of dev_priv__ inside the
>> for_each_engine(), perhaps it should be mov
Hi Jani,
On Thu, Sep 01, 2022 at 03:47:09PM +0300, Jani Nikula wrote:
> Prefer the parsed results for is_hdmi in display info over calling
> drm_detect_hdmi_monitor(). Remove the now redundant hdmi_monitor member
> from struct sti_hdmi.
>
> Cc: Alain Volmat
> Signed-off-by: Jani Nikula
> ---
>
On Fri, Mar 31, 2023 at 03:46:03PM +0530, Ankit Nautiyal wrote:
> The decision to use DFP output format conversion capabilities should be
> during compute_config phase.
>
> This patch uses the members of intel_dp->dfp to only store the
> format conversion capabilities of the DP device and uses the
On Fri, Mar 31, 2023 at 03:46:04PM +0530, Ankit Nautiyal wrote:
> Handle the case with DP to HDMI PCON, where sink_format is set to YCbCr444.
> In that case PCON is required to be configured to convert from given
> output_format to YCbCR444.
>
> Signed-off-by: Ankit Nautiyal
> ---
> drivers/gpu/
Visible glitches have been observed when running graphics applications on
Linux under Xen hypervisor. Those observations have been confirmed with
failures from kms_pwrite_crc Intel GPU test that verifies data coherency
of DRM frame buffer objects using hardware CRC checksums calculated by
display
On Fri, Mar 31, 2023 at 03:46:05PM +0530, Ankit Nautiyal wrote:
> Start passing the sink_format, to all functions that take a bool
> ycbcr420_output as parameter. This will make the functions generic,
> and will serve as a slight step towards 4:2:2 support later.
>
> v2: Rebased.
>
> v3: Correct
On Fri, Mar 31, 2023 at 03:46:06PM +0530, Ankit Nautiyal wrote:
> Common function to get the sink format for a given mode for DP.
>
> Signed-off-by: Ankit Nautiyal
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 30 -
> 1 file changed, 15 i
On Fri, Mar 31, 2023 at 03:46:02PM +0530, Ankit Nautiyal wrote:
> New member to store the YCBCR20 Pass through capability of the DP sink.
>
> Signed-off-by: Ankit Nautiyal
> ---
> drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers
On Fri, Mar 31, 2023 at 03:46:08PM +0530, Ankit Nautiyal wrote:
> While using DSC the compressed bpp is computed assuming RGB output
> format. Consider the output_format and compute the compressed bpp
> during mode valid and compute config steps.
>
> For DP-MST we currently use RGB output format o
On Fri, Mar 31, 2023 at 03:46:09PM +0530, Ankit Nautiyal wrote:
> The final link bpp used to calculate the m_n values depend on the
> output_format. Though the output_format is set to RGB for MST case and
> the link bpp will be same as the pipe bpp, for the sake of semantics,
> lets calculate the m
On Fri, Mar 31, 2023 at 03:46:13PM +0530, Ankit Nautiyal wrote:
> Currently there are many places where we use output_bpp for link bpp and
> compressed bpp.
> Lets use consistent naming:
> output_bpp : The intermediate value taking into account the
> output_format chroma subsampling.
> compressed_b
On Fri, Mar 31, 2023 at 03:46:00PM +0530, Ankit Nautiyal wrote:
> This series fixes issues faced when an HDMI2.1 sink that does not
> support DSC is connected via HDMI2.1PCON. It also includes other minor
> HDMI2.1 PCON fixes/refactoring.
>
> Patch 1-2 Have minor fixes/cleanups.
> Patch 3-6 Pull t
On 24.04.23 14:35, Janusz Krzysztofik wrote:
Visible glitches have been observed when running graphics applications on
Linux under Xen hypervisor. Those observations have been confirmed with
failures from kms_pwrite_crc Intel GPU test that verifies data coherency
of DRM frame buffer objects usin
igt_live_test has pr_err dumped in case of some
GT failures. It will be more informative regarding
GT if we use gt_err instead.
Cc: Andi Shyti
Signed-off-by: Tejas Upadhyay
---
drivers/gpu/drm/i915/selftests/igt_live_test.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git
== Series Details ==
Series: drm/i915/mtl: workaround coherency issue for Media (rev4)
URL : https://patchwork.freedesktop.org/series/116751/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13053 -> Patchwork_116751v4
Summary
Hi Jani,
> >> just another "Friday patch". While reviewing some patches from
> >> Tejas I found a bit confusing the use of dev_priv__ inside the
> >> for_each_engine(), perhaps it should be moved inside the gt/?
> >>
> >> As I was at it I made the /dev_priv/i915/ change which is still
> >> harmle
On Mon, Apr 24, 2023 at 02:35:24PM +0200, Janusz Krzysztofik wrote:
> Visible glitches have been observed when running graphics applications on
> Linux under Xen hypervisor. Those observations have been confirmed with
> failures from kms_pwrite_crc Intel GPU test that verifies data coherency
> of
On Wed, Apr 19, 2023 at 10:07:46AM +, Murthy, Arun R wrote:
> > -Original Message-
> > From: Nikula, Jani
> > Sent: Wednesday, April 19, 2023 3:26 PM
> > To: Murthy, Arun R ; intel-
> > g...@lists.freedesktop.org
> > Cc: ville.syrj...@linux.intel.com
> > Subject: RE: [RESEND PATCHv2] d
This reverts commit faca6aaa4838c3c234caa619d3c7d1f09da0d303.
This patch, in series with the next "Define MOCS and PAT tables
for MTL" are causing boot failures for MTL.
Revert them both.
Signed-off-by: Andi Shyti
Cc: Fei Yang
Cc: Matt Roper
---
drivers/gpu/drm/i915/gt/selftest_mocs.c | 3 +-
Hi,
The two patches reverted in this series are, together, preventing
MTL from booting.
Revert them until the fix is deployed.
Andi
Andi Shyti (2):
Revert "drm/i915/mtl: fix mocs selftest"
Revert "drm/i915/mtl: Define MOCS and PAT tables for MTL"
drivers/gpu/drm/i915/gt/intel_gt_regs.h |
This reverts commit b76c0deef6273609c02ed5053209f6397cd1b0fb.
This patch is causing boot failures for MTL.
Revert it.
Signed-off-by: Andi Shyti
Cc: Matt Roper
Cc: Lucas De Marchi
Cc: Aravind Iddamsetty
Cc: Nirmoy Das
Cc: Fei Yang
Cc: Andrzej Hajda
---
drivers/gpu/drm/i915/gt/intel_gt_reg
On 4/24/2023 6:09 PM, Andi Shyti wrote:
Hi,
The two patches reverted in this series are, together, preventing
MTL from booting.
Revert them until the fix is deployed.
Andi
Andi Shyti (2):
Revert "drm/i915/mtl: fix mocs selftest"
Revert "drm/i915/mtl: Define MOCS and PAT tables for MTL
== Series Details ==
Series: drm/i915/mtl: workaround coherency issue for Media (rev4)
URL : https://patchwork.freedesktop.org/series/116751/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13053_full -> Patchwork_116751v4_full
===
drm/i915: Initialize dkl_phy spin lock from display code path
Start moving the initialization of display locks from
i915_driver_early_probe().
Display locks should be initialized from display-only code paths.
It was also agreed that if a variable is only used in one file, it
should be initialized
From: Fei Yang
Extract PTE patch from https://patchwork.freedesktop.org/series/116868/
to fix MTL boot issue caused by MOCS/PAT update.
Fei Yang (2):
drm/i915/mtl: Add PTE encode function
drm/i915/mtl: workaround coherency issue for Media
drivers/gpu/drm/i915/display/intel_dpt.c | 2 +-
From: Fei Yang
PTE encode functions are platform dependent. This patch implements
PTE functions for MTL, and ensures the correct PTE encode function
is used by calling pte_encode function pointer instead of the
hardcoded gen8 version of PTE encode.
Fixes: b76c0deef627 ("drm/i915/mtl: Define MOCS
From: Fei Yang
This patch implements Wa_22016122933.
In MTL, memory writes initiated by the Media tile update the whole
cache line, even for partial writes. This creates a coherency
problem for cacheable memory if both CPU and GPU are writing data
to different locations within a single cache lin
On Sun, 23 Apr 2023 13:16:44 -0700, Belgaumkar, Vinay wrote:
>
Hi Vinay,
> On 4/14/2023 1:25 PM, Dixit, Ashutosh wrote:
> > On Fri, 14 Apr 2023 12:16:37 -0700, Vinay Belgaumkar wrote:
> > Hi Vinay,
> >
> >> Use default of 0 where GT id is not being used.
> >>
> >> v2: Add a helper for GT 0 (Ashut
On Mon, 24 Apr 2023 09:55:14 -0700, Dixit, Ashutosh wrote:
>
> On Sun, 23 Apr 2023 13:16:44 -0700, Belgaumkar, Vinay wrote:
> >
>
> Hi Vinay,
>
> > On 4/14/2023 1:25 PM, Dixit, Ashutosh wrote:
> > > On Fri, 14 Apr 2023 12:16:37 -0700, Vinay Belgaumkar wrote:
> > > Hi Vinay,
> > >
> > >> Use default
On 2023-04-24 02:08:43, Tvrtko Ursulin wrote:
>
> Being able to "list" supported extensions sounds like a reasonable
> principle, albeit a departure from the design direction to date.
> Which means there are probably no quick solutions. Also, AFAIU, only
> PXP context create is the problematic one
On Mon, 24 Apr 2023 10:07:26 -0700, Dixit, Ashutosh wrote:
>
> On Mon, 24 Apr 2023 09:55:14 -0700, Dixit, Ashutosh wrote:
> >
> > On Sun, 23 Apr 2023 13:16:44 -0700, Belgaumkar, Vinay wrote:
> > >
> >
> > Hi Vinay,
> >
> > > On 4/14/2023 1:25 PM, Dixit, Ashutosh wrote:
> > > > On Fri, 14 Apr 2023 1
On Sun, Apr 23, 2023 at 12:37:27AM -0700, Yang, Fei wrote:
> > On Fri, Apr 21, 2023 at 10:27:22AM -0700, Yang, Fei wrote:
> >>> On Wed, Apr 19, 2023 at 04:00:53PM -0700, fei.y...@intel.com wrote:
> From: Fei Yang
>
> PTE encode functions are platform dependent. This patch implements
It looks like the number you have in the title and comments isn't a
valid workaround number. It looks like you actually meant to use
Wa_14018575942.
On Mon, Apr 24, 2023 at 03:47:49PM +0530, Tejas Upadhyay wrote:
> WA 18018781329 is applicable now across all MTL
> steppings.
Wa_18018781329 hasn'
On Sun, Apr 23, 2023 at 10:28:58AM +, Liu, Yi L wrote:
> This noiommu improvement shall allow user to attach ioas to noiommu devices.
> is it? This may be done by calling iommufd_access_attach(). So there is a
> quick question. In the cdev series, shall we allow the attachment
> for noiommu?
On Tue, 04 Apr 2023 17:14:32 -0700, Umesh Nerlige Ramappa wrote:
Hi Umesh,
> GPU accumulates the context runtime in a 32 bit counter - CTX_TIMESTAMP
> in the context image. This value is saved/restored on context switches.
> KMD accumulates these values into a 64 bit counter taking care of any
>
On Thu, Apr 20, 2023 at 03:40:43PM +0300, Mika Kahola wrote:
> Use MPLLA for DP2.0 rates 20G and 20G, when ssc is enabled.
>
Reviewed-by: Radhakrishna Sripada
- Radhakrishna(RK) Sripada
> Signed-off-by: Mika Kahola
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 7 +--
> 1 file cha
From: Fei Yang
PTE encode functions are platform dependent. This patch implements
PTE functions for MTL, and ensures the correct PTE encode function
is used by calling pte_encode function pointer instead of the
hardcoded gen8 version of PTE encode.
Fixes: b76c0deef627 ("drm/i915/mtl: Define MOCS
From: Fei Yang
Extract PTE patch from https://patchwork.freedesktop.org/series/116868/
to fix MTL boot issue caused by MOCS/PAT update.
v2: address comment from Matt.
Fei Yang (2):
drm/i915/mtl: Add PTE encode function
drm/i915/mtl: workaround coherency issue for Media
drivers/gpu/drm/i91
From: Fei Yang
This patch implements Wa_22016122933.
In MTL, memory writes initiated by the Media tile update the whole
cache line, even for partial writes. This creates a coherency
problem for cacheable memory if both CPU and GPU are writing data
to different locations within a single cache lin
On Sat, Apr 22, 2023 at 08:43:59PM +0200, Hans de Goede wrote:
> The intel_dsi_msleep() helper skips sleeping if the MIPI-sequences have
> a version of 3 or newer and the panel is in vid-mode.
>
> This is based on the big comment around line 730 which starts with
> "Panel enable/disable sequences
> On Sun, Apr 23, 2023 at 12:37:27AM -0700, Yang, Fei wrote:
>>> On Fri, Apr 21, 2023 at 10:27:22AM -0700, Yang, Fei wrote:
> On Wed, Apr 19, 2023 at 04:00:53PM -0700, fei.y...@intel.com wrote:
>> From: Fei Yang
>>
>> PTE encode functions are platform dependent. This patch implemen
Hi Ville,
On 4/24/23 20:34, Ville Syrjälä wrote:
> On Sat, Apr 22, 2023 at 08:43:59PM +0200, Hans de Goede wrote:
>> The intel_dsi_msleep() helper skips sleeping if the MIPI-sequences have
>> a version of 3 or newer and the panel is in vid-mode.
>>
>> This is based on the big comment around line 7
On Mon, Apr 24, 2023 at 08:54:27PM +0200, Hans de Goede wrote:
> Hi Ville,
>
> On 4/24/23 20:34, Ville Syrjälä wrote:
> > On Sat, Apr 22, 2023 at 08:43:59PM +0200, Hans de Goede wrote:
> >> The intel_dsi_msleep() helper skips sleeping if the MIPI-sequences have
> >> a version of 3 or newer and the
== Series Details ==
Series: drm/i915/mtl: Add workaround 14018778641 (rev2)
URL : https://patchwork.freedesktop.org/series/116750/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13054 -> Patchwork_116750v2
Summary
---
On 2023-04-16 23:43:20, Yang, Fei wrote:
> > fei.y...@intel.com kirjoitti 17.4.2023 klo 9.24:
> >> From: Fei Yang
> >>
> >> The series includes patches needed to enable MTL.
> >> Also add new extension for GEM_CREATE uAPI to let user space set cache
> >> policy for buffer objects.
> >
> > if I'm
On ADLP+ Bspec allows DC5/6 to be enabled while power well 2 is enabled.
Since the AUX and DDI power wells (except for port A/B) are also backed
by power well 2, this would suggest that DC5/6 can be enabled while any
of these AUX or DDI port functionalities are used. As opposed to this
AUX transfer
== Series Details ==
Series: x86/mm: Fix PAT bit missing from page protection modify mask
URL : https://patchwork.freedesktop.org/series/116883/
State : warning
== Summary ==
Error: dim checkpatch failed
43584c6560ff x86/mm: Fix PAT bit missing from page protection modify mask
-:50: WARNING:CO
== Series Details ==
Series: x86/mm: Fix PAT bit missing from page protection modify mask
URL : https://patchwork.freedesktop.org/series/116883/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: x86/mm: Fix PAT bit missing from page protection modify mask
URL : https://patchwork.freedesktop.org/series/116883/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13054 -> Patchwork_116883v1
Summ
On Thu, Apr 20, 2023 at 03:40:39PM +0300, Mika Kahola wrote:
> Create a table for C20 DP1.4, DP2.0 and HDMI2.1 rates.
> The PLL settings are based on table, not for algorithmic alternative.
> For DP 1.4 only MPLLB is in use.
>
> Once register settings are done, we read back C20 HW state.
>
> BSpe
On Thu, Apr 20, 2023 at 03:40:40PM +0300, Mika Kahola wrote:
> As we already do with C10 chip, let's dump the pll
> hw state for C20 as well.
>
Reviewed-by: Radhakrishna Sripada
> Signed-off-by: Mika Kahola
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 20
> driver
== Series Details ==
Series: drm/i915/mtl: add PTE encode function (rev2)
URL : https://patchwork.freedesktop.org/series/116868/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/mtl: add PTE encode function (rev2)
URL : https://patchwork.freedesktop.org/series/116868/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13055 -> Patchwork_116868v2
Summary
---
*
This is revived patchset improving ref_tracker library and converting
i915 internal tracker to ref_tracker.
The old thread ended without consensus about small kernel allocations,
which are performed under spinlock.
I have tried to solve the problem by splitting the calls, but it results
in complica
To have reliable detection of leaks, caller must be able to check under
the same lock both: tracked counter and the leaks. dir.lock is natural
candidate for such lock and unlocked print helper can be called with this
lock taken.
As a bonus we can reuse this helper in ref_tracker_dir_exit.
Signed-o
In case the library is tracking busy subsystem, simply
printing stack for every active reference will spam log
with long, hard to read, redundant stack traces. To improve
readabilty following changes have been made:
- reports are printed per stack_handle - log is more compact,
- added display name
Similar to stack_(depot|trace)_snprint the patch
adds helper to printing stats to memory buffer.
It will be helpful in case of debugfs.
Signed-off-by: Andrzej Hajda
Reviewed-by: Andi Shyti
---
include/linux/ref_tracker.h | 8 +++
lib/ref_tracker.c | 56 +++
Track every intel_gt_pm_get() until its corresponding release in
intel_gt_pm_put() by returning a cookie to the caller for acquire that
must be passed by on released. When there is an imbalance, we can see who
either tried to free a stale wakeref, or who forgot to free theirs.
Signed-off-by: Andrz
Wakeref has dedicated type. Assumption it will be int
compatible forever is incorrect.
Signed-off-by: Andrzej Hajda
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_
Library can handle allocation failures. To avoid allocation warnings
__GFP_NOWARN has been added everywhere. Moreover GFP_ATOMIC has been
replaced with GFP_NOWAIT in case of stack allocation on tracker free
call.
Signed-off-by: Andrzej Hajda
Reviewed-by: Andi Shyti
Reviewed-by: Eric Dumazet
---
Beside reusing existing code, the main advantage of ref_tracker is
tracking per instance of wakeref. It allows also to catch double
put.
On the other side we lose information about the first acquire and
the last release, but the advantages outweigh it.
Signed-off-by: Andrzej Hajda
---
drivers/gp
== Series Details ==
Series: drm/i915/selftest: Record GT error for gt failure
URL : https://patchwork.freedesktop.org/series/116890/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13056 -> Patchwork_116890v1
Summary
---
== Series Details ==
Series: drm/i915/mtl: Add PTE encode functions (rev2)
URL : https://patchwork.freedesktop.org/series/116900/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/mtl: Add PTE encode functions (rev2)
URL : https://patchwork.freedesktop.org/series/116900/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13056 -> Patchwork_116900v2
Summary
---
== Series Details ==
Series: drm/i915/mtl: Add workaround 14018778641 (rev2)
URL : https://patchwork.freedesktop.org/series/116750/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13054_full -> Patchwork_116750v2_full
Summary
== Series Details ==
Series: Restore MTL boot (rev2)
URL : https://patchwork.freedesktop.org/series/116894/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Restore MTL boot (rev2)
URL : https://patchwork.freedesktop.org/series/116894/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13056 -> Patchwork_116894v2
Summary
---
**SUCCESS**
No regr
== Series Details ==
Series: drm/i915/adlp+: Disable DC5/6 states for TC port DDI/AUX and for combo
port AUX
URL : https://patchwork.freedesktop.org/series/116909/
State : warning
== Summary ==
Error: dim checkpatch failed
308b7246ce58 drm/i915/adlp+: Disable DC5/6 states for TC port DDI/AUX
On Thu, 20 Apr 2023 17:08:42 -0700, Patchwork wrote:
>
> Patch Details
>
> Series: drm/i915/guc: Disable PL1 power limit when loading GuC firmware
> URL: https://patchwork.freedesktop.org/series/116768/
> State: failure
> Details:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11676
== Series Details ==
Series: drm/i915/adlp+: Disable DC5/6 states for TC port DDI/AUX and for combo
port AUX
URL : https://patchwork.freedesktop.org/series/116909/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13056 -> Patchwork_116909v1
==
== Series Details ==
Series: drm/i915: use ref_tracker library for tracking wakerefs (rev9)
URL : https://patchwork.freedesktop.org/series/100327/
State : warning
== Summary ==
Error: dim checkpatch failed
b36b281bc951 lib/ref_tracker: add unlocked leak print helper
258df8024aa3 lib/ref_tracke
== Series Details ==
Series: drm/i915: use ref_tracker library for tracking wakerefs (rev9)
URL : https://patchwork.freedesktop.org/series/100327/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: use ref_tracker library for tracking wakerefs (rev9)
URL : https://patchwork.freedesktop.org/series/100327/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13056 -> Patchwork_100327v9
Su
== Series Details ==
Series: x86/mm: Fix PAT bit missing from page protection modify mask
URL : https://patchwork.freedesktop.org/series/116883/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13054_full -> Patchwork_116883v1_full
== Series Details ==
Series: Improvements to uc firmare management (rev4)
URL : https://patchwork.freedesktop.org/series/116517/
State : warning
== Summary ==
Error: dim checkpatch failed
767fe16369d4 drm/i915/guc: Decode another GuC load failure case
95f43703948d drm/i915/guc: Print status re
== Series Details ==
Series: Improvements to uc firmare management (rev4)
URL : https://patchwork.freedesktop.org/series/116517/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Improvements to uc firmare management (rev4)
URL : https://patchwork.freedesktop.org/series/116517/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13056 -> Patchwork_116517v4
Summary
---
*
== Series Details ==
Series: drm/i915/mtl: add PTE encode function (rev2)
URL : https://patchwork.freedesktop.org/series/116868/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13055_full -> Patchwork_116868v2_full
Summary
--
For 128b/132b LT prior to LT DPTX should set power state, DP channel
coding and then link rate.
v2: added separate function to avoid code duplication(Jani N)
v3: DP2.1 section 3.5.2.16 is ordered, 3.5.1.2 is unordered and hence
discarding
Signed-off-by: Arun R Murthy
---
.../drm/i915/displ
== Series Details ==
Series: drm/i915/display/dp: 128/132b LT requirement (rev4)
URL : https://patchwork.freedesktop.org/series/116562/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13056 -> Patchwork_116562v4
Summary
-
== Series Details ==
Series: drm/i915/selftest: Record GT error for gt failure
URL : https://patchwork.freedesktop.org/series/116890/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13056_full -> Patchwork_116890v1_full
Summa
== Series Details ==
Series: drm/i915/mtl: Add PTE encode functions (rev2)
URL : https://patchwork.freedesktop.org/series/116900/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13056_full -> Patchwork_116900v2_full
Summary
-
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 3b85b9b39960c08f29fa91b8d984d055dde6017e Add linux-next specific
files for 20230424
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/202304102354.q4voxgte-...@intel.com
https
== Series Details ==
Series: Restore MTL boot (rev2)
URL : https://patchwork.freedesktop.org/series/116894/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13056_full -> Patchwork_116894v2_full
Summary
---
**SUCCESS**
On 24.04.2023 22:02, Imre Deak wrote:
On ADLP+ Bspec allows DC5/6 to be enabled while power well 2 is enabled.
Since the AUX and DDI power wells (except for port A/B) are also backed
by power well 2, this would suggest that DC5/6 can be enabled while any
of these AUX or DDI port functionalities a
On 24.04.2023 18:09, Andi Shyti wrote:
This reverts commit faca6aaa4838c3c234caa619d3c7d1f09da0d303.
This patch, in series with the next "Define MOCS and PAT tables
for MTL" are causing boot failures for MTL.
Revert them both.
Signed-off-by: Andi Shyti
Cc: Fei Yang
Cc: Matt Roper
Reviewed
On 24.04.2023 18:09, Andi Shyti wrote:
This reverts commit b76c0deef6273609c02ed5053209f6397cd1b0fb.
This patch is causing boot failures for MTL.
Revert it.
Signed-off-by: Andi Shyti
Cc: Matt Roper
Cc: Lucas De Marchi
Cc: Aravind Iddamsetty
Cc: Nirmoy Das
Cc: Fei Yang
Cc: Andrzej Hajda
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