Hi
Attached is the patch to provide gma500 with an interface to remove the
VGA devices. Hopefully this, otherwise, I'd respin the whole series.
Best regards
Thomas
Am 04.04.23 um 22:18 schrieb Daniel Vetter:
This one nukes all framebuffers, which is a bit much. In reality
gma500 is igpu and
== Series Details ==
Series: Add hwmon support for dgfx selftests (rev9)
URL : https://patchwork.freedesktop.org/series/109850/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12972_full -> Patchwork_109850v9_full
Summary
---
On Wed, 5 Apr 2023 at 19:46, Patrik Jakobsson
wrote:
>
> On Wed, Apr 5, 2023 at 7:15 PM Daniel Vetter wrote:
> >
> > On Wed, 5 Apr 2023 at 18:54, Javier Martinez Canillas
> > wrote:
> > >
> > > Daniel Vetter writes:
> > >
> > > > On Wed, Apr 05, 2023 at 04:32:19PM +0200, Thomas Zimmermann wrote
Hi Fei,
On Mon, Apr 03, 2023 at 03:50:26PM +0300, Jani Nikula wrote:
> On Fri, 31 Mar 2023, fei.y...@intel.com wrote:
> > From: Fei Yang
> >
> > On MTL, GT can no longer allocate on LLC - only the CPU can.
> > This, along with addition of support for ADM/L4 cache calls a
> > MOCS/PAT table update
Hi Dave & Daniel,
Here goes the final drm-intel-gt-next pull request for v6.4.
As top items we have a fix for context runtime accounting, Meteorlake
enabling, DMAR error noise elimination due to GPU error capture, BAR
resizing forcewake fix and memory contents clearing fix for discrete.
More robu
On Wed, 05 Apr 2023, Riana Tauro wrote:
> Rename librapl library to libpower. Add hwmon support in libpower for
> dgfx.
> Use libpower in selftests.
>
> Rev2 : Update commit message
> Rev3 : Remove redundant code
> Rev4 : Add hwmon per-gt support
> Rev5 : No functional changes.
>Change aut
Hi Fei,
On 4/1/2023 8:38 AM, fei.y...@intel.com wrote:
From: Fei Yang
On MTL, GT can no longer allocate on LLC - only the CPU can.
This, along with addition of support for ADM/L4 cache calls a
MOCS/PAT table update.
Also add PTE encode functions for MTL as it has different PAT
index definition
Thomas Zimmermann writes:
[...]
> Am 04.04.23 um 22:18 schrieb Daniel Vetter:
> Gma500 therefore calls both helpers to catch all cases. It's confusing
> as it implies that there's something about the PCI device that requires
> ownership management. The relationship between the PCI device and the
Hi
Am 06.04.23 um 10:38 schrieb Javier Martinez Canillas:
Thomas Zimmermann writes:
[...]
Am 04.04.23 um 22:18 schrieb Daniel Vetter:
Gma500 therefore calls both helpers to catch all cases. It's confusing
as it implies that there's something about the PCI device that requires
ownership manag
Currently we seem to be using wrong DPCD register for reading compressed bpps,
reading min/max input bpc instead of compressed bpp.
Fix that, so that we now apply min/max compressed bpp limitations we get
from DP Spec Table 2-157 DP v2.0 and/or correspondent DPCD register
DP_DSC_MAX_BITS_PER_PIXEL_
On 3/29/2023 7:19 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Introduce a structure that can hold our CSC matrices. In there
we shall have the preoffsets, postoffsets, and coefficients,
all in platform specific format (at least for now).
We shall start by converting the ilk+ code to make us
On 3/29/2023 7:19 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Split chv_cgm_csc_convert_ctm() out from chv_load_cgm_csc() so
that we have functions with clear jobs. This is also how the ilk+
code is already structured.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_c
== Series Details ==
Series: series starting with [1/8] drm/gma500: Use
drm_aperture_remove_conflicting_pci_framebuffers (rev2)
URL : https://patchwork.freedesktop.org/series/116115/
State : failure
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/116115/revisions/
Thomas Zimmermann writes:
[...]
>>> +EXPORT_SYMBOL(__aperture_remove_legacy_vga_devices);
>>
>> I would just call this symbol aperture_remove_legacy_vga_devices() as
>> mentioned, the fact that aperture_remove_conflicting_pci_devices() use it
>> internally is an implementation detail IMO. But i
On 3/29/2023 7:19 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Convert chv_cgm_csc_convert_ctm() over to using the nee
nitpick: typo: new.
Otherwise LGTM.
Reviewed-by: Ankit Nautiyal
intel_csc_matrix structure. No pre/post offsets on this
hardware so only the coefficients get filled ou
On Sat, 1 Apr 2023 at 07:37, wrote:
>
> From: Fei Yang
>
> To comply with the design that buffer objects shall have immutable
> cache setting through out its life cycle, {set, get}_caching ioctl's
> are no longer supported from MTL onward. With that change caching
> policy can only be set at obje
On 3/29/2023 7:19 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Embed a pair of intel_csc_matrix structs in the crtc state,
and fill them out appropriately during atomic_check().
Since pre-ivb platforms don't have programmable post offsets
we shall leave those zeroed, mainly in preparation fo
Hi Ashutosh,
kernel test robot noticed the following build warnings:
[auto build test WARNING on drm-tip/drm-tip]
url:
https://github.com/intel-lab-lkp/linux/commits/Ashutosh-Dixit/drm-i915-hwmon-Get-mutex-and-rpm-ref-just-once-in-hwm_power_max_write/20230406-124659
base: git
On 4/6/2023 2:33 PM, Nautiyal, Ankit K wrote:
On 3/29/2023 7:19 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Split chv_cgm_csc_convert_ctm() out from chv_load_cgm_csc() so
that we have functions with clear jobs. This is also how the ilk+
code is already structured.
Signed-off-by: Ville Syr
On 3/29/2023 7:19 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Store the chv cgm csc matrix in the crtc state as well. We
shall store it in the same place where we store the ilk+
pipe csc matrix (as opposed to the output csc matrix).
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/d
LGTM.
Reviewed-by: Ankit Nautiyal
On 3/29/2023 7:19 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Make sure the csc enable bit(s) match the way we're about to
fill the csc matrices.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 22 ++
1
== Series Details ==
Series: drm/i915: Query compressed bpp properly using correct DPCD and DP Spec
info
URL : https://patchwork.freedesktop.org/series/116179/
State : warning
== Summary ==
Error: dim checkpatch failed
3cce658f5bbb drm/i915: Query compressed bpp properly using correct DPCD an
Patch LGTM.
Perhaps TODO part, to check for case of PSR and if DC states are already
off can be taken as separate patch.
Reviewed-by: Ankit Nautiyal
On 3/29/2023 7:19 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Read out the pipe/output csc matrices on ilk+ and stash the results
(in the h
LGTM.
Reviewed-by: Ankit Nautiyal
On 3/29/2023 7:19 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Read out the csc matrix on chv, and stash the result into the
correct spot in the crtc state.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 36
== Series Details ==
Series: drm/i915: Query compressed bpp properly using correct DPCD and DP Spec
info
URL : https://patchwork.freedesktop.org/series/116179/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12979 -> Patchwork_116179v1
==
Hi Yi,
On 4/1/23 17:18, Yi Liu wrote:
> This defines KVM_DEV_VFIO_FILE* and make alias with KVM_DEV_VFIO_GROUP*.
> Old userspace uses KVM_DEV_VFIO_GROUP* works as well.
>
> Reviewed-by: Jason Gunthorpe
> Reviewed-by: Kevin Tian
> Tested-by: Terrence Xu
> Tested-by: Nicolin Chen
> Tested-by: Ma
On 3/29/2023 7:20 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Include the csc matrices in the state dump. The format being
hardware specific we just dump as hex for now. Might have
to think of some way to get a bit more human readable
output...
Yeah if we can read coeff and print in decima
LGTM.
Reviewed-by: Ankit Nautiyal
On 3/29/2023 7:20 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Have the state checker validate that the csc matrices
look correct when read back from the hardware.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 21 +++
== Series Details ==
Series: Add hwmon support for dgfx selftests
URL : https://patchwork.freedesktop.org/series/116136/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12973_full -> Patchwork_116136v1_full
Summary
---
On Thu, 06 Apr 2023, Stanislav Lisovskiy wrote:
> Currently we seem to be using wrong DPCD register for reading compressed bpps,
> reading min/max input bpc instead of compressed bpp.
> Fix that, so that we now apply min/max compressed bpp limitations we get
> from DP Spec Table 2-157 DP v2.0 and/
> From: Jason Gunthorpe
> Sent: Thursday, April 6, 2023 7:23 AM
>
> On Wed, Apr 05, 2023 at 01:49:45PM -0600, Alex Williamson wrote:
>
> > > > QEMU can make a policy decision today because the kernel provides a
> > > > sufficiently reliable interface, ie. based on the set of owned groups, a
> >
Not planning to upstream that actually, just for some bug on gitlab.
Want to see if that helps the reporter, then at least there is an idea whats
the problem.
From: Jani Nikula
Sent: Thursday, April 6, 2023 12:59 PM
To: Lisovskiy, Stanislav; intel-gfx@lis
On Thu, 06 Apr 2023, "Lisovskiy, Stanislav"
wrote:
> Not planning to upstream that actually, just for some bug on gitlab.
> Want to see if that helps the reporter, then at least there is an idea whats
> the problem.
The issue in drm_edp_dsc_sink_output_bpp() needs to be fixed regardless.
BR,
J
On Thu, Apr 06, 2023 at 02:33:05PM +0530, Nautiyal, Ankit K wrote:
>
> On 3/29/2023 7:19 PM, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Split chv_cgm_csc_convert_ctm() out from chv_load_cgm_csc() so
> > that we have functions with clear jobs. This is also how the ilk+
> > code is alread
== Series Details ==
Series: drm/i915/display: Increase AUX timeout for Type-C (rev2)
URL : https://patchwork.freedesktop.org/series/116010/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12973_full -> Patchwork_116010v2_full
Hi Eric,
> From: Eric Auger
> Sent: Thursday, April 6, 2023 5:47 PM
>
> Hi Yi,
>
> On 4/1/23 17:18, Yi Liu wrote:
> > This defines KVM_DEV_VFIO_FILE* and make alias with KVM_DEV_VFIO_GROUP*.
> > Old userspace uses KVM_DEV_VFIO_GROUP* works as well.
> >
> > Reviewed-by: Jason Gunthorpe
> > Revi
On Thu, Apr 06, 2023 at 12:59:40PM +0300, Jani Nikula wrote:
> On Thu, 06 Apr 2023, Stanislav Lisovskiy
> wrote:
> > Currently we seem to be using wrong DPCD register for reading compressed
> > bpps,
> > reading min/max input bpc instead of compressed bpp.
> > Fix that, so that we now apply min/
Hi Ville,
HDMI1.4b indeed says max value for 16bpc as 60160 (0xeb00)
And black level of 4096.
Got me thinking that we might need to consider bpc for getting the
Coeffs and the offsets.
IIUC for CSC Full range to Limited range:
out = in * gain + offset
Gain :
So for 8 bpc, as you have mention
On 05/04/2023 18:57, Rob Clark wrote:
On Tue, Jan 31, 2023 at 3:33 AM Tvrtko Ursulin
wrote:
From: Tvrtko Ursulin
Rudimentary vendor agnostic example of how lib_igt_drm_clients can be used
to display a sorted by card and usage list of processes using GPUs.
Borrows a bit of code from intel_
On Thu, Apr 06, 2023 at 04:26:48PM +0530, Nautiyal, Ankit K wrote:
> Hi Ville,
>
> HDMI1.4b indeed says max value for 16bpc as 60160 (0xeb00)
> And black level of 4096.
>
> Got me thinking that we might need to consider bpc for getting the
> Coeffs and the offsets.
> IIUC for CSC Full range to L
On Thu, Apr 6, 2023 at 9:32 AM Daniel Vetter wrote:
>
> On Wed, 5 Apr 2023 at 19:46, Patrik Jakobsson
> wrote:
> >
> > On Wed, Apr 5, 2023 at 7:15 PM Daniel Vetter wrote:
> > >
> > > On Wed, 5 Apr 2023 at 18:54, Javier Martinez Canillas
> > > wrote:
> > > >
> > > > Daniel Vetter writes:
> > >
Hi Dave, Daniel,
Pull request to avoid backmerges. ;)
Cheers,
~Maarten
drm-misc-next-2023-04-06:
drm-misc-next for v6.4-rc1:
UAPI Changes:
Cross-subsystem Changes:
- Document port and rotation dt bindings better.
- For panel timing DT bindings, document that vsync and hsync are
first, rather
On 4/6/2023 4:40 PM, Ville Syrjälä wrote:
On Thu, Apr 06, 2023 at 04:26:48PM +0530, Nautiyal, Ankit K wrote:
Hi Ville,
HDMI1.4b indeed says max value for 16bpc as 60160 (0xeb00)
And black level of 4096.
Got me thinking that we might need to consider bpc for getting the
Coeffs and the offsets
On Thu, Apr 06, 2023 at 01:56:00PM +0300, Ville Syrjälä wrote:
> On Thu, Apr 06, 2023 at 12:59:40PM +0300, Jani Nikula wrote:
> > On Thu, 06 Apr 2023, Stanislav Lisovskiy
> > wrote:
> > > Currently we seem to be using wrong DPCD register for reading compressed
> > > bpps,
> > > reading min/max i
On Fri, 31 Mar 2023, "Christian König" wrote:
> We only keept that around for API compatibility with drivers. Clean all
> this up and use the per device debugfs directory.
>
> Signed-off-by: Christian König
> ---
> drivers/accel/drm_accel.c | 2 --
> drivers/gpu/drm/amd/amd
On Thu, 06 Apr 2023, Maarten Lankhorst
wrote:
> Hi Dave, Daniel,
> Pull request to avoid backmerges. ;)
> Cheers,
> ~Maarten
Not using dim for this? Is the subject line copy-pasted from another
pull request? :)
BR,
Jani.
>
> drm-misc-next-2023-04-06:
> drm-misc-next for v6.4-rc1:
>
> UAPI Chan
== Series Details ==
Series: series starting with [1/2] drm/i915/tc: demote a kernel-doc comment to
a regular comment
URL : https://patchwork.freedesktop.org/series/116144/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12974_full -> Patchwork_116144v1_full
===
On Thu, Apr 06, 2023 at 01:56:00PM +0300, Ville Syrjälä wrote:
> On Thu, Apr 06, 2023 at 12:59:40PM +0300, Jani Nikula wrote:
> > On Thu, 06 Apr 2023, Stanislav Lisovskiy
> > wrote:
> > > Currently we seem to be using wrong DPCD register for reading compressed
> > > bpps,
> > > reading min/max i
On Thu, Apr 06, 2023 at 11:18:06AM +0300, Joonas Lahtinen wrote:
> Hi Dave & Daniel,
>
> Here goes the final drm-intel-gt-next pull request for v6.4.
>
> As top items we have a fix for context runtime accounting, Meteorlake
> enabling, DMAR error noise elimination due to GPU error capture, BAR
>
Hi Yi,
On 4/1/23 17:18, Yi Liu wrote:
> This avoids passing too much parameters in multiple functions.
> Reviewed-by: Kevin Tian
> Reviewed-by: Jason Gunthorpe
> Tested-by: Terrence Xu
> Tested-by: Nicolin Chen
> Tested-by: Matthew Rosato
> Tested-by: Yanting Jiang
> Signed-off-by: Yi Liu
>
On Wed, 05 Apr 2023, "Govindapillai, Vinod"
wrote:
> On Wed, 2023-04-05 at 13:41 +0300, Jani Nikula wrote:
>> There's not much point in a static work function having a kernel-doc
>> comment. Just clean it up and make it a regular comment.
>>
>> This fixes the kernel-doc warnings:
>>
>> drivers/gp
On Thu, Apr 06, 2023 at 03:34:04PM +0300, Jani Nikula wrote:
> On Thu, 06 Apr 2023, Maarten Lankhorst
> wrote:
> > Hi Dave, Daniel,
> > Pull request to avoid backmerges. ;)
> > Cheers,
> > ~Maarten
>
> Not using dim for this? Is the subject line copy-pasted from another
> pull request? :)
dim d
From: Clint Taylor
Initialization sequences and C10 phy are in place to be able to enable
the first 2 ports of MTL. The other ports use C20 phy that still need
to be properly added. Enable the first ports for now, keeping a TODO
comment about the others.
Cc: Radhakrishna Sripada
Reviewed-by: Lu
Phy programming support for C10 phy. This is the first part of
the series that adds support for PICA phy. Later stage the support
for C20 phy is added. This series gets the eDP going.
v2: Register refinitions in intel_cx0_phy_regs.h file (Jani)
v3: Add waits for between message bus writes (Imre)
C10 phys uses direct mapping internally for voltage and pre-emphasis levels.
Program the levels directly to the fields in the VDR Registers.
Bspec: 65449
v2: From table "C10: Tx EQ settings for DP 1.4x" it shows level 1
and preemphasis 1 instead of two times of level 1 preemphasis 0.
Fix
From: Radhakrishna Sripada
XELPDP has C10 and C20 phys from Synopsys to drive displays. Each phy
has a dedicated PIPE 5.2 Message bus for configuration. This message
bus is used to configure the phy internal registers.
XELPDP has C10 phys to drive output to the EDP and the native output
from the
Add DP rates for Meteorlake.
Reviewed-by: Vinod Govindapillai
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_dp.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
Create a separate file to store registers for PICA chips
C10 and C20.
v2: Rename file (Jani)
v3: Use _PICK_EVEN_2RANGES() macro (Lucas)
Coding style fixed (Lucas)
v4: Redefine macros (Imre)
Reviewed-by: Vinod Govindapillai (v3)
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
PICA is used for DP alt mode and TBT modes. Hotplug interruption is routed
from PICA chip to south display engine and from there to north display
engine. This patch adds functionality to enable hotplug detection for
all Type-C ports (4 ports available).
Differently from HPD in south display, PICA
From: Ankit Nautiyal
MTL requires the PORT_CTL_WIDTH, TRANS_DDI_FUNC_CTL and DDI_BUF_CTL
to be filled with 4 lanes for TMDS mode.
This patch enables D2D link and fills PORT_WIDTH in appropriate
registers.
v2:
- Added fixes from Clint's Add HDMI implementation changes.
- Modified commit messa
From: José Roberto de Souza
The differences between MTL and TGL DP sequences are big enough to
MTL have its own functions.
Also it is much easier to follow MTL sequences against spec with
its own functions.
One change worthy to mention is the move of
'intel_display_power_get(dev_priv, dig_port-
== Series Details ==
Series: drm/atomic-helper: Don't set deadline for modesets (rev2)
URL : https://patchwork.freedesktop.org/series/116140/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12974_full -> Patchwork_116140v2_full
===
The operator precedence between << and & is wrong, leading to the high
byte being completely ignored. For example, with the 6.4 format, 32
becomes 0 and 24 becomes 8. Fix it, and remove the slightly confusing
and unnecessary DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT macro while at it.
Fixes: 0575650077ea
The macro values just don't match the specs. Fix them.
Fixes: 1482ec00be4a ("drm: Add missing DP DSC extended capability definitions.")
Cc: Vinod Govindapillai
Cc: Stanislav Lisovskiy
Signed-off-by: Jani Nikula
---
include/drm/display/drm_dp.h | 4 ++--
1 file changed, 2 insertions(+), 2 delet
On Thu, 06 Apr 2023, Jani Nikula wrote:
> On Thu, 06 Apr 2023, "Lisovskiy, Stanislav"
> wrote:
>> Not planning to upstream that actually, just for some bug on gitlab.
>> Want to see if that helps the reporter, then at least there is an idea whats
>> the problem.
>
> The issue in drm_edp_dsc_sin
Hi Daniel,
Here goes drm-intel-next-2023-04-06:
- Fix DPT+shmem combo and add i915.enable_dpt modparam (Ville)
- i915.enable_sagv module parameter (Ville)
- Correction to QGV related register addresses (Vinod)
- IPS debugfs per-crtc and new file for false_color (Ville)
- More clean-up and reorgan
On 4/1/23 17:18, Yi Liu wrote:
> Allow the vfio_device file to be in a state where the device FD is
> opened but the device cannot be used by userspace (i.e. its .open_device()
> hasn't been called). This inbetween state is not used when the device
> FD is spawned from the group FD, however when
Hi Yi,
On 4/1/23 17:18, Yi Liu wrote:
> for counting the devices that are opened via the cdev path. This count
> is increased and decreased by the cdev path. The group path checks it
> to achieve exclusion with the cdev path. With this, only one path (group
> path or cdev path) will claim DMA owne
From: Tvrtko Ursulin
Extract some code into a new library to prepare for further work towards
making a vendor agnostic gputop tool.
Signed-off-by: Tvrtko Ursulin
---
lib/igt_drm_clients.c | 432 +++
lib/igt_drm_clients.h | 85 +++
lib/meson.build |
From: Tvrtko Ursulin
This is a pile of patches which implements a rudimentary vendor agnostic gputop
tool based of the new DRM spec as documented in
Documentation/gpu/drm-usage-stats.rst.
First part of the series is code refactoring which should be reasonably stable.
I've tested it all while wor
From: Tvrtko Ursulin
Prepare for supporting clients belonging to multiple DRM cards by storing
the DRM minor in the client record.
Signed-off-by: Tvrtko Ursulin
---
lib/igt_drm_clients.c | 22 ++
lib/igt_drm_clients.h | 1 +
2 files changed, 15 insertions(+), 8 deletions(-
From: Tvrtko Ursulin
Require DRM minor match during client lookup.
Signed-off-by: Tvrtko Ursulin
---
lib/igt_drm_clients.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/lib/igt_drm_clients.c b/lib/igt_drm_clients.c
index c23a3fae9793..e11c8b18188f 100644
--
From: Tvrtko Ursulin
Instead of hard coding the engine names, allow a map of names to indices
to either be passed in or it gets auto-detected (less efficient) while
parsing.
---
lib/igt_drm_clients.c | 18 +---
lib/igt_drm_clients.h | 3 ++-
lib/igt_drm_fdinfo.c| 48
From: Tvrtko Ursulin
Prep code for incoming work.
Signed-off-by: Tvrtko Ursulin
---
lib/igt_drm_fdinfo.c | 2 ++
lib/igt_drm_fdinfo.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/lib/igt_drm_fdinfo.c b/lib/igt_drm_fdinfo.c
index 68c89ad2c17e..b850d2210ae7 100644
--- a/lib/igt_drm_fdin
From: Tvrtko Ursulin
Some libdrmclient operations require that inactive clients are last in the
list. Rather than relying on callers of the library sort routine to
implement their comparison callbacks correctly, enforce this order
directly in the library and let callers comparison callbacks conce
From: Tvrtko Ursulin
Intel_gpu_top gets it's main engine configuration data via PMU probe and
uses that for per client view as well. Furthemore code so far assumed only
clients belonging from a single DRM card would be tracked in a single
clients list.
Break this inter-dependency by moving the e
From: Tvrtko Ursulin
Rudimentary vendor agnostic example of how lib_igt_drm_clients can be used
to display a sorted by card and usage list of processes using GPUs.
Borrows a bit of code from intel_gpu_top but for now omits the fancy
features like interactive functionality, card selection, client
On Thu, Apr 6, 2023 at 4:08 AM Tvrtko Ursulin
wrote:
>
>
> On 05/04/2023 18:57, Rob Clark wrote:
> > On Tue, Jan 31, 2023 at 3:33 AM Tvrtko Ursulin
> > wrote:
> >>
> >> From: Tvrtko Ursulin
> >>
> >> Rudimentary vendor agnostic example of how lib_igt_drm_clients can be used
> >> to display a sor
On 06/04/2023 15:21, Rob Clark wrote:
On Thu, Apr 6, 2023 at 4:08 AM Tvrtko Ursulin
wrote:
On 05/04/2023 18:57, Rob Clark wrote:
On Tue, Jan 31, 2023 at 3:33 AM Tvrtko Ursulin
wrote:
From: Tvrtko Ursulin
Rudimentary vendor agnostic example of how lib_igt_drm_clients can be used
to dis
Start to move the initialization of some lock from
i915_driver_early_probe().
This will also fix a warning in Xe kmd:
[ 201.894839] xe :00:02.0: [drm] [ENCODER:235:DDI A/PHY A] failed to
retrieve link info, disabling eDP
[ 202.136336] xe :00:02.0: [drm] *ERROR* Failed to write source OU
This spin lock will not be used in older display versions, so no need
to initialize it.
Cc: intel-gfx@lists.freedesktop.org
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_dkl_phy.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/
dsparb_lock it not used anymore, nuke it.
Cc: intel-gfx@lists.freedesktop.org
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display_core.h | 3 ---
drivers/gpu/drm/i915/i915_driver.c| 1 -
2 files changed, 4 deletions(-)
diff --git a/drivers/gpu/drm
> On 4/1/2023 8:38 AM, fei.y...@intel.com wrote:
>> From: Fei Yang
>>
>> On MTL, GT can no longer allocate on LLC - only the CPU can.
>> This, along with addition of support for ADM/L4 cache calls a
>> MOCS/PAT table update.
>> Also add PTE encode functions for MTL as it has different PAT
>> index
== Series Details ==
Series: drm/i915/mtl: Add Support for C10 phy
URL : https://patchwork.freedesktop.org/series/116191/
State : warning
== Summary ==
Error: dim checkpatch failed
09ec7a640ab5 drm/i915/mtl: Initial DDI port setup
581165ce249c drm/i915/mtl: Add DP rates
bee5f7f012de drm/i915/m
== Series Details ==
Series: drm/i915/mtl: Add Support for C10 phy
URL : https://patchwork.freedesktop.org/series/116191/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/mtl: Add Support for C10 phy
URL : https://patchwork.freedesktop.org/series/116191/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12981 -> Patchwork_116191v1
Summary
---
**SUCCES
This patchset makes dma-buf exporters responisble for taking care of
the reservation lock. I also included patch that moves drm-shmem to use
reservation lock, to let CI test the whole set. I'm going to take all
the patches via the drm-misc tree, please give an ack.
Previous policy stated that dma-
Don't assert held dma-buf reservation lock on memory mapping of exported
buffer.
We're going to change dma-buf mmap() locking policy such that exporters
will have to handle the lock. The previous locking policy caused deadlock
problem for DRM drivers in a case of self-imported dma-bufs once these
Don't assert held dma-buf reservation lock on memory mapping of exported
buffer.
We're going to change dma-buf mmap() locking policy such that exporters
will have to handle the lock. The previous locking policy caused deadlock
problem for DRM drivers in a case of self-imported dma-bufs once these
Don't assert held dma-buf reservation lock on memory mapping of exported
buffer.
We're going to change dma-buf mmap() locking policy such that exporters
will have to handle the lock. The previous locking policy caused deadlock
problem for DRM drivers in a case of self-imported dma-bufs once these
Don't assert held dma-buf reservation lock on memory mapping of exported
buffer.
We're going to change dma-buf mmap() locking policy such that exporters
will have to handle the lock. The previous locking policy caused deadlock
problem for DRM drivers in a case of self-imported dma-bufs once these
Replace all drm-shmem locks with a GEM reservation lock. This makes locks
consistent with dma-buf locking convention where importers are responsible
for holding reservation lock for all operations performed over dma-bufs,
preventing deadlock between dma-buf importers and exporters.
Suggested-by: D
Don't assert held dma-buf reservation lock on memory mapping of exported
buffer.
We're going to change dma-buf mmap() locking policy such that exporters
will have to handle the lock. The previous locking policy caused deadlock
problem for DRM drivers in a case of self-imported dma-bufs once these
Change locking policy of mmap() callback, making exporters responsible
for handling dma-buf reservation locking. Previous locking policy stated
that dma-buf is locked for both importers and exporters by the dma-buf
core, which caused a deadlock problem for DRM drivers in a case of
self-imported dma
On Thu, Apr 06, 2023 at 10:03:51AM -0400, Rodrigo Vivi wrote:
> Hi Daniel,
>
> Here goes drm-intel-next-2023-04-06:
>
> - Fix DPT+shmem combo and add i915.enable_dpt modparam (Ville)
> - i915.enable_sagv module parameter (Ville)
> - Correction to QGV related register addresses (Vinod)
> - IPS deb
On 3/31/23 01:02, Jani Nikula wrote:
On Thu, 30 Mar 2023, "Gustavo A. R. Silva" wrote:
Friendly ping: who can take this, please? 😄
It's in drm-intel-gt-next.
Awesome. :) Thank you!
--
Gustavo
commit 02abecdeebfcd3848b26b70778dd7f6eb0db65e1
Author: Gustavo A. R. Silva
AuthorDate:
== Series Details ==
Series: series starting with [1/2] drm/dsc: fix drm_edp_dsc_sink_output_bpp()
DPCD high byte usage
URL : https://patchwork.freedesktop.org/series/116192/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be che
Hi Yi,
On 4/1/23 17:18, Yi Liu wrote:
> VFIO group has historically allowed multi-open of the device FD. This
> was made secure because the "open" was executed via an ioctl to the
> group FD which is itself only single open.
>
> However, no known use of multiple device FDs today. It is kind of a
>
== Series Details ==
Series: series starting with [1/2] drm/dsc: fix drm_edp_dsc_sink_output_bpp()
DPCD high byte usage
URL : https://patchwork.freedesktop.org/series/116192/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12981 -> Patchwork_116192v1
===
On Thu, 6 Apr 2023 06:34:08 +
"Liu, Yi L" wrote:
> Hi Alex,
>
> > From: Alex Williamson
> > Sent: Thursday, April 6, 2023 3:50 AM
> >
> > On Wed, 5 Apr 2023 16:21:09 -0300
> > Jason Gunthorpe wrote:
> >
> > > On Wed, Apr 05, 2023 at 12:56:21PM -0600, Alex Williamson wrote:
> > > > Us
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