[Intel-gfx] [PATCH] drm/i915/guc: Disable PL1 power limit when loading GuC firmware

On dGfx, the PL1 power limit being enabled and set to a low value results in a low GPU operating freq. It also negates the freq raise operation which is done before GuC firmware load. As a result GuC firmware load can time out. Such timeouts were seen in the GL #8062 bug below (where the PL1 power

Re: [Intel-gfx] [PATCH 2/2] drm/i915/guc: Allow for very slow GuC loading

On 3/3/2023 11:20, Ceraolo Spurio, Daniele wrote: On 2/17/2023 3:47 PM, john.c.harri...@intel.com wrote: From: John Harrison A failure to load the GuC is occasionally observed where the GuC log actually showed that the GuC had loaded just fine. The implication being that the load just took eve

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: make kobj attributes const (rev2)

== Series Details == Series: drm/i915/gt: make kobj attributes const (rev2) URL : https://patchwork.freedesktop.org/series/114898/ State : success == Summary == CI Bug Log - changes from CI_DRM_12829_full -> Patchwork_114898v2_full Summary

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/ttm: let struct ttm_device_funcs be placed in rodata

== Series Details == Series: drm/ttm: let struct ttm_device_funcs be placed in rodata URL : https://patchwork.freedesktop.org/series/114907/ State : success == Summary == CI Bug Log - changes from CI_DRM_12829_full -> Patchwork_114907v1_full

Re: [Intel-gfx] [PATCH v4 9/9] drm/i915/perf: Add support for OA media units

On Fri, 10 Mar 2023 16:18:30 -0800, Umesh Nerlige Ramappa wrote: > > On Fri, Mar 10, 2023 at 09:36:52AM -0800, Dixit, Ashutosh wrote: > > On Fri, 10 Mar 2023 08:39:27 -0800, Umesh Nerlige Ramappa wrote: > >> > > > > Hi Umesh, > > > >> On Thu, Mar 09, 2023 at 03:57:48PM -0800, Dixit, Ashutosh wrote:

[Intel-gfx] [PATCH v3 2/3] drm/i915/guc: Clean up of register capture search

From: John Harrison The comparison in the search for a matching register capture node was not the most readable. It was also assuming that a zero GuC id means invalid, which it does not. So remove one invalid term, one redundant term and re-format to keep each term on a single line, and only one

[Intel-gfx] [PATCH v3 3/3] drm/i915: Include timeline seqno in error capture

From: John Harrison The seqno value actually written out to memory is no longer in the regular HWSP. Instead, it is now in its own private timeline buffer. Thus, it is no longer visible in an error capture. So, explicitly read the value and include that in the capture. v2: %d -> %u (Alan) Signe

[Intel-gfx] [PATCH v3 1/3] drm/i915/guc: Fix missing ecodes

From: John Harrison Error captures are tagged with an 'ecode'. This is a pseduo-unique magic number that is meant to distinguish similar seeming bugs with different underlying signatures. It is a combination of two ring state registers. Unfortunately, the register state being used is only valid i

[Intel-gfx] [PATCH v3 0/3] More error capture improvements

From: John Harrison Ecodes got lost with the switch to GuC based register lists. Put them back. Seqno values got lost with the switch to per context timelines. Put those back too. v2: Rework the timeline patch to just read the single seqno value rather than copying the entire object (Daniele) v

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for More error capture improvements (rev3)

== Series Details == Series: More error capture improvements (rev3) URL : https://patchwork.freedesktop.org/series/113628/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for More error capture improvements (rev3)

== Series Details == Series: More error capture improvements (rev3) URL : https://patchwork.freedesktop.org/series/113628/ State : success == Summary == CI Bug Log - changes from CI_DRM_12842 -> Patchwork_113628v3 Summary --- **SUCCE

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