> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Wednesday, February 22, 2023 8:45 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH] drm/i915/audio: Track audio state per-transcoder
>
> From: Ville Syrjälä
>
> The audio logic lives in
Hi Dave, Daniel,
Here's this week drm-misc-fixes PR
Maxime
drm-misc-fixes-2023-02-23:
A fix for nouveau preventing the system shutdown and one for a build
warning, and NULL pointer dereference fix for cirrus.
The following changes since commit a950b989ea29ab3b38ea7f6e3d2540700a3c54e8:
drm/vmw
== Series Details ==
Series: drm/i915/psr: Use calculated io and fast wake lines (rev3)
URL : https://patchwork.freedesktop.org/series/114217/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12770 -> Patchwork_114217v3
Summar
Hi,
This is what are on gvt tree now for next kernel, including fixes for
gvt debugfs, one kconfig symbol fix for menu presentation and misc
typo fixes. Please check details below. This is generated against current
drm-intel-next-fixes.
Thanks!
--
The following changes since commit 8038510b1fe44
On 17.02.2023 19:54, Matt Roper wrote:
MTL's primary GT can continue to use the same engine TLB invalidation
programming as past Xe_HP-based platforms. However the media GT needs
some special handling:
* Invalidation registers on the media GT are singleton registers
(unlike the primary GT
Thanks
Reviewed-by: Vinod Govindapillai
BR
Vinod
On Wed, 2023-01-25 at 20:52 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> At least on some platforms (tested on ctg) the way
> vgacon does screen blanking seems to flag constant
> FIFO underruns, which means we have to be prepared
> for
> -Original Message-
> From: Sousa, Gustavo
> Sent: Tuesday, February 7, 2023 6:54 PM
> To: Kahola, Mika ; intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani
> Subject: Re: [Intel-gfx] [PATCH v2 09/21] drm/i915/mtl: C20 HW readout
>
> On Thu, Jan 05, 2023 at 02:54:34PM +0200, Mika Kahola
Hi Ville,
Please add closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8222
On 23-Feb-23 1:48 PM, Shankar, Uma wrote:
-Original Message-
From: Intel-gfx On Behalf Of Ville
Syrjala
Sent: Wednesday, February 22, 2023 8:45 PM
To: intel-gfx@lists.freedesktop.org
Subject: [Intel
Few selftest fixes to gt_pm and rps tests.
Anshuman Gupta (2):
drm/i915/selftest: Fix engine timestamp and ktime disparity
drm/i915/selftest: Fix ktime_get() and h/w access order
drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_rps.c | 10 +-
2 fil
While reading the engine timestamps there can be uncontrollable
concurrent mmio access via other i915 child drivers and by GuC,
which is not truly atomic context as expected by this selftest,
which may cause mmio latency to read the engine timestamps,
Account such latency to calculate time to read
Use ktime_get() after accessing the mmio or any driver resource,
while using wall time for various calculation that depends on
the inserted delay in order to account any mmio and resource
access latency.
Cc: Chris Wilson
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/gt/selftest_rps.c |
> From: Tian, Kevin
> Sent: Wednesday, February 22, 2023 3:18 PM
>
> > From: Liu, Yi L
> > Sent: Tuesday, February 21, 2023 11:48 AM
> >
> > +
> > + KVM_DEV_VFIO_FILE_SET_SPAPR_TCE: attaches a guest visible TCE
> table
> > allocated by sPAPR KVM.
> > +
> > + alias: KVM_DEV_VFIO_GROUP_SET_
> -Original Message-
> From: Intel-gfx On Behalf Of Kahola,
> Mika
> Sent: Thursday, February 23, 2023 11:47 AM
> To: Sousa, Gustavo ; intel-
> g...@lists.freedesktop.org
> Cc: Nikula, Jani
> Subject: Re: [Intel-gfx] [PATCH v2 09/21] drm/i915/mtl: C20 HW readout
>
> > -Original Mes
== Series Details ==
Series: drm/i915/psr: Use calculated io and fast wake lines (rev3)
URL : https://patchwork.freedesktop.org/series/114217/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12770_full -> Patchwork_114217v3_full
==
== Series Details ==
Series: Selftest fixes
URL : https://patchwork.freedesktop.org/series/114284/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12771 -> Patchwork_114284v1
Summary
---
**SUCCESS**
No regressions f
While computing compressed bpp, maximum value of bits_per_pixel is
calculated that can be supported with the given link configuration
for a given mode. Avoid rounding up of this max bits_per_pixel.
Also improve documentation for computing max bits_per_pixel.
Signed-off-by: Ankit Nautiyal
---
dri
On Thu, 23 Feb 2023, Zhenyu Wang wrote:
> Hi,
>
> This is what are on gvt tree now for next kernel, including fixes for
> gvt debugfs, one kconfig symbol fix for menu presentation and misc
> typo fixes. Please check details below. This is generated against current
> drm-intel-next-fixes.
Thanks,
Am 23.02.23 um 07:27 schrieb Hogander, Jouni:
On Wed, 2023-02-22 at 15:13 -0500, Rodrigo Vivi wrote:
On Wed, Feb 22, 2023 at 03:17:55PM +0100, Werner Sembach wrote:
On these Barebones PSR 2 is recognized as supported but is very
buggy:
- Upper third of screen does sometimes not updated, resul
On Thu, 23 Feb 2023, "Shankar, Uma" wrote:
>> -Original Message-
>> From: Nautiyal, Ankit K
>> Sent: Thursday, February 23, 2023 10:06 AM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Roper, Matthew D ; Shankar, Uma
>> ; Sharma, Swati2
>> Subject: [PATCH] drm/i915/dg2: Add HDMI pixel clo
> -Original Message-
> From: Jani Nikula
> Sent: Thursday, February 23, 2023 5:43 PM
> To: Shankar, Uma ; Nautiyal, Ankit K
> ; intel-gfx@lists.freedesktop.org
> Cc: Roper, Matthew D
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/dg2: Add HDMI pixel clock
> frequencies
> 267.30 and 319.8
Hello
Reviewed-by: Vinod Govindapillai
BR
Vinod
On Wed, 2023-01-25 at 20:52 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The gen2/gen3 irq code is supposed to be identical apart
> from the 32bit vs. 16bit access width. The recent change
> to intel_de_rmw() ruined that symmetry. Resto
Hi
Reviewed-by: Vinod Govindapillai
BR
Vinod
On Wed, 2023-01-25 at 20:52 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> PGTBL_ER contains the individual reasons for the page table
> error interrupt. Dump it out.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_irq.
Hi,
On Wed, 2023-01-25 at 20:52 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Pull the EMR calculation into small helpers.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_irq.c | 46 ++---
> 1 file changed, 25 insertions(+), 21 deletions
Hi
Reviewed-by: Vinod Govindapillai
BR
vinod
PS: With this patch seems my comment for the prev patch in this series might
not be relevant.
On Wed, 2023-01-25 at 20:52 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> FBC on gen2/3 seems to trigger page table errors. No visual
> artifact
On Thu, Feb 23, 2023 at 07:55:21AM +, Tian, Kevin wrote:
> > From: Jason Gunthorpe
> > Sent: Thursday, February 23, 2023 1:18 AM
> >
> > > > static bool vfio_dev_in_groups(struct vfio_pci_core_device *vdev,
> > > >struct vfio_pci_group_info *groups)
> > > > {
>
== Series Details ==
Series: Selftest fixes
URL : https://patchwork.freedesktop.org/series/114284/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12771_full -> Patchwork_114284v1_full
Summary
---
**SUCCESS**
No reg
PHY programming support for PICA C10 and C20 Type-C chips.
v2: Move intel_cx0_reg_defs.h to intel_cx0_phy_regs.h (Jani)
Move pmdemand as part of intel_display structure
PLL table updates
v3: Renaming C20 read/write functions (Gustavo)
Code readibility fixes (Gustavo)
HDMI PLL table
From: Clint Taylor
Initialize c10 combo phy ports. TODO Type-C ports.
Cc: Radhakrishna Sripada
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b
Create a separate file to store registers for PICA chips
C10 and C20.
v2: Rename file (Jani)
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 136 ++
1 file changed, 136 insertions(+)
create mode 100644 drivers/
Add DP rates for Meteorlake.
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_dp.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/int
Calculate port clock with C20 phy.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 64 +++-
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
3 files changed, 65 insertions(+), 5 deletions(-)
From: Radhakrishna Sripada
XELPDP has C10 and C20 phys from Synopsys to drive displays. Each phy
has a dedicated PIPE 5.2 Message bus for configuration. This message
bus is used to configure the phy internal registers.
XELPDP has C10 phys to drive output to the EDP and the native output
from the
Add C20 HDMI state calculations and put HDMI table definitions
in use.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_
From: Radhakrishna Sripada
C10 phys uses direct mapping internally for voltage and pre-emphasis levels.
Program the levels directly to the fields in the VDR Registers.
Bspec: 65449
v2: From table "C10: Tx EQ settings for DP 1.4x" it shows level 1
and preemphasis 1 instead of two times of le
As we already do with C10 chip, let's dump the pll
hw state for C20 as well.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 20
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 ++
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
3 files c
Use MPLLA for DP2.0 rates 20G and 20G, when ssc is enabled.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_c
C20 phy PLL programming sequence for DP, DP2.0, HDMI2.x non-FRL and
HDMI2.x FRL. This enables C20 MPLLA and MPLLB programming sequence. add
4 lane support for c20.
v2: Rename intel_c20_write() to intel_c20_sram_write() (Gustavo)
Remove unnecessary bit masks (Gustavo)
Fix comments on C20 pl
Create a table for C20 DP1.4, DP2.0 and HDMI2.1 rates.
The PLL settings are based on table, not for algorithmic alternative.
For DP 1.4 only MPLLB is in use.
Once register settings are done, we read back C20 HW state.
BSpec: 64568
v2: Update rbr, hbr1, hbr2, and hbr3 pll configurations 4 and 5
Enabling and disabling sequence for Thunderbolt PLL.
v2: Use __intel_de_wait_for_register() instead of
__intel_wait_for_register() (Jani)
Use '0' instead of ~XELPDP_TBT_CLOCK_ACK (Gustavo)
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 136
Readout hw state for Thunderbolt.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 27
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 5 +++-
3 files changed, 32 insertions(+), 2 deletions(-)
From: Anusha Srivatsa
Unlike previous platforms that used PORT_TX_DFLEXDPSP
for max_lane calculation, MTL uses only PORT_TX_DFLEXPA1
from which the max_lanes has to be calculated.
Bspec: 50235, 65380
Cc: Mika Kahola
Cc: Imre Deak
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
Signed-off-by:
PICA is used for DP alt mode and TBT modes. Hotplug interruption is routed
from PICA chip to south display engine and from there to north display
engine. This patch adds functionality to enable hotplug detection for
all Type-C ports (4 ports available).
Differently from HPD in south display, PICA
From: Imre Deak
The HPD live status for MTL has to be read from different set of
registers. MTL deserves a new function for this purpose
and cannot reuse the existing HPD live status detection
Signed-off-by: Anusha Srivatsa
Signed-off-by: Imre Deak
Signed-off-by: Mika Kahola
---
drivers/gpu
DP1.4 and DP20 voltage swing sequence for C20 phy.
Bspec: 65449, 67636, 67610
v2: DP2.0 Tx Eq tables has been updated in BSpec.
Update also the driver code as per BSpec 65449
Signed-off-by: Mika Kahola
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Clint Taylor
---
.../gpu/drm/i915/d
Add register writes to enable powering up Type-C subsystem i.e. TCSS.
For MeteorLake we need to request TCSS to power up and check the TCSS
power state after 500 us.
In addition, for PICA we need to set/clear the Type-C PHY ownnership
bit when Type-C device is connected/disconnected.
v2: Call tcs
Display14 introduces a new way to instruct the PUnit with
power and bandwidth requirements of DE. Add the functionality
to program the registers and handle waits using interrupts.
The current wait time for timeouts is programmed for 10 msecs to
factor in the worst case scenarios. Changes made to us
Finally, we can enable TC ports for Meteorlake.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_display.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f
From: Gustavo Sousa
Xe_LPD+ defines interrupt bits for only DDI ports in the DE Port
Interrupt registers. The bits for Type-C ports are defined in the PICA
interrupt registers.
BSpec: 50064
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/i915_irq.c | 5 -
1 file changed, 4 insertions
From: Radhakrishna Sripada
Like DG2, we still don't have a proper algorithm that can be used
for calculating PHY settings, but we do have tables of register
values for a handful of the more common link rates. Some support is
better than none, so let's go ahead and add/use these tables when we
can
On Thu, Feb 23, 2023 at 12:46:21PM +, Govindapillai, Vinod wrote:
> Hi
>
> Reviewed-by: Vinod Govindapillai
>
> BR
> vinod
>
> PS: With this patch seems my comment for the prev patch in this series might
> not be relevant.
Aye.
On a related note, sometimes I do muse about unifying all
t
== Series Details ==
Series: drm/i915/dp: Don't roundup max bpp, while computing compressed bpp
URL : https://patchwork.freedesktop.org/series/114290/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12772 -> Patchwork_114290v1
== Series Details ==
Series: drm/i915/mtl: Add C10 and C20 phy support (rev5)
URL : https://patchwork.freedesktop.org/series/109714/
State : warning
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/109714/revisions/5/mbox/ not
found
== Series Details ==
Series: drm/i915/mtl: Add C10 and C20 phy support (rev5)
URL : https://patchwork.freedesktop.org/series/109714/
State : warning
== Summary ==
Error: dim checkpatch failed
d63b0ef4e1cd drm/i915/mtl: Initial DDI port setup
8c2d26b90675 drm/i915/mtl: Add DP rates
a6ef4c024d38
== Series Details ==
Series: drm/i915/mtl: Add C10 and C20 phy support (rev5)
URL : https://patchwork.freedesktop.org/series/109714/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12772 -> Patchwork_109714v5
Summary
---
On Thu, Feb 23, 2023 at 03:19:30PM +0530, Swati Sharma wrote:
> Hi Ville,
>
> Please add closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8222
Added, and pushed.
Thanks for the review Uma.
>
> On 23-Feb-23 1:48 PM, Shankar, Uma wrote:
> >
> >
> >> -Original Message-
> >> Fro
This series (or at least the suballocator helper) is a prerequisite
for the new Xe driver.
There was an unresolved issue when the series was last up for review,
and that was the per allocation aligment. Last message was from
Maarten Lankhorst arguing that the larger per-driver alignment used
would
From: Maarten Lankhorst
Suballocating a buffer object is something that is not driver-specific
and useful for many drivers.
Use a slightly modified version of amdgpu_sa.c
v2:
- Style cleanups.
- Added / Modified documentation.
- Use u64 for the sizes and offset. The code dates back to 2012 and
From: Maarten Lankhorst
Now that we have a generic suballocation helper, Use it in amdgpu.
For lines that get moved or changed, also fix up pre-existing style issues.
Signed-off-by: Maarten Lankhorst
Co-developed-by: Thomas Hellström
Signed-off-by: Thomas Hellström
Reviewed-by: Christian Köni
From: Maarten Lankhorst
Use the generic suballocation helper for radeon.
v3:
- Select the suballoc helper in Kconfig (Thomas).
Signed-off-by: Maarten Lankhorst
Co-developed-by: Thomas Hellström
Signed-off-by: Thomas Hellström
Reviewed-by: Christian König
---
drivers/gpu/drm/radeon/Kconfig
Hi, Daniel,
On 2/16/23 21:18, Daniel Vetter wrote:
On Thu, Feb 16, 2023 at 05:27:28PM +0100, Thomas Hellström wrote:
A slightly unusual cover letter for a single patch.
The page table walker is currently used by the xe driver only,
but the code is generic so we can be good citizens and add it
On Wed, Feb 22, 2023 at 05:59:45PM +, Shankar, Uma wrote:
>
>
> > -Original Message-
> > From: Intel-gfx On Behalf Of
> > Ville Syrjala
> > Sent: Monday, February 20, 2023 8:48 PM
> > To: intel-gfx@lists.freedesktop.org
> > Subject: [Intel-gfx] [PATCH 1/2] drm/i915: Fix audio ELD ha
From: Ville Syrjälä
intel_crtc_prepare_cleared_state() is unintentionally losing
the "inherited" flag. This will happen if intel_initial_commit()
is forced to go through the full modeset calculations for
whatever reason.
Afterwards the first real commit from userspace will not get
forced to the
== Series Details ==
Series: drm/helpers: Make the suballocation manager drm generic
URL : https://patchwork.freedesktop.org/series/114299/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
> -Original Message-
> From: Ville Syrjälä
> Sent: Thursday, February 23, 2023 8:37 PM
> To: Shankar, Uma
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915: Fix audio ELD handling for DP
> MST
>
> On Wed, Feb 22, 2023 at 05:59:45PM +, Shankar,
== Series Details ==
Series: drm/helpers: Make the suballocation manager drm generic
URL : https://patchwork.freedesktop.org/series/114299/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12773 -> Patchwork_114299v1
Summary
-
A couple of fixes for issue related to synchronization of the GSC worker
start/end with kernel init/fini and suspend/resume. See the individual
commit messages for details.
Note: not fixes tag since MTL is still under force probe
Cc: Alan Previn
Daniele Ceraolo Spurio (2):
drm/i915/gsc: flush
If we unload the driver and wedge before the GSC worker is complete,
the worker will hit an error on its submission to the GSC engine and
then exit. This is hard to hit for a user, but it is reproducible
with skipping selftests. The error is handled gracefully by the
worker, so there are no functio
The GSC FW load is a slow process (up to 250 ms), so we defer it to a
dedicated worker to avoid stalling the init flow for that long. However,
we currently start this worker before the HW init is complete, so there
is a chance that the GSC loading code submits to the HW before the
engine initializa
On Tue, Feb 21, 2023 at 02:06:06PM +0530, Nautiyal, Ankit K wrote:
>
> On 2/21/2023 1:07 AM, Ville Syrjälä wrote:
> > On Mon, Feb 20, 2023 at 05:53:48PM +0530, Ankit Nautiyal wrote:
> >> The decision to use DFP output format conversion capabilities should be
> >> during compute_config phase.
> >>
On Thu, Feb 23, 2023 at 05:01:11PM +, Shankar, Uma wrote:
>
>
> > -Original Message-
> > From: Ville Syrjälä
> > Sent: Thursday, February 23, 2023 8:37 PM
> > To: Shankar, Uma
> > Cc: intel-gfx@lists.freedesktop.org
> > Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915: Fix audio ELD ha
== Series Details ==
Series: drm/i915/dp: Don't roundup max bpp, while computing compressed bpp
URL : https://patchwork.freedesktop.org/series/114290/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12772_full -> Patchwork_114290v1_full
==
Hi Dave and Daniel,
Here's the first pull request for v6.4-rc1.
Enjoy!
~Maarten
drm-misc-next-2023-02-23:
drm-misc-next for v6.4-rc1:
First pull request to keep the delta from growing too big.
UAPI Changes:
- Convert rockchip bindings to YAML.
- Constify kobj_type structure in dma-buf.
- FBD
On Wed, 2023-02-22 at 15:17 +0100, Werner Sembach wrote:
> On these Barebones PSR 2 is recognized as supported but is very
> buggy:
> - Upper third of screen does sometimes not updated, resulting in
> disappearing cursors or ghosts of already closed Windows saying
> behind.
> - Approximately 40 px
Apply Wa_14017073508 for MTL SoC die A step instead of graphics step.
To get the SoC die stepping there is no direct interface so using
revid as revid 0 aligns with SoC die A step.
Bspec: 55420
Fixes: 8f70f1ec587d ("drm/i915/mtl: Add Wa_14017073508 for SAMedia")
Signed-off-by: Badal Nilawar
---
Refactor the supports_x_tiling and fast_blit_ok helper
functions in the live client selftest to better reflect
when XY_FAST_COPY_BLT supports X-tile and can be used.
Signed-off-by: Jonathan Cavitt
---
.../i915/gem/selftests/i915_gem_client_blt.c | 19 +--
1 file changed, 9 inser
Hi Maarten,
On Thu, Feb 23, 2023 at 07:25:23PM +0100, Maarten Lankhorst wrote:
> Hi Dave and Daniel,
>
> Here's the first pull request for v6.4-rc1.
>
> Enjoy!
>
> ~Maarten
>
> drm-misc-next-2023-02-23:
> drm-misc-next for v6.4-rc1:
>
> First pull request to keep the delta from growing too bi
On Thu, Feb 23, 2023 at 10:03 AM Thomas Hellström
wrote:
>
> Hi, Daniel,
>
> On 2/16/23 21:18, Daniel Vetter wrote:
> > On Thu, Feb 16, 2023 at 05:27:28PM +0100, Thomas Hellström wrote:
> >> A slightly unusual cover letter for a single patch.
> >>
> >> The page table walker is currently used by th
Am 23.02.23 um 19:26 schrieb Hogander, Jouni:
On Wed, 2023-02-22 at 15:17 +0100, Werner Sembach wrote:
On these Barebones PSR 2 is recognized as supported but is very
buggy:
- Upper third of screen does sometimes not updated, resulting in
disappearing cursors or ghosts of already closed Window
Am 23.02.23 um 19:56 schrieb Werner Sembach:
Am 23.02.23 um 19:26 schrieb Hogander, Jouni:
On Wed, 2023-02-22 at 15:17 +0100, Werner Sembach wrote:
On these Barebones PSR 2 is recognized as supported but is very
buggy:
- Upper third of screen does sometimes not updated, resulting in
disappea
== Series Details ==
Series: drm/i915: Preserve crtc_state->inherited during state clearing
URL : https://patchwork.freedesktop.org/series/114303/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12774 -> Patchwork_114303v1
Su
== Series Details ==
Series: Fix a couple of issues with the GSC worker timing
URL : https://patchwork.freedesktop.org/series/114306/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Fix a couple of issues with the GSC worker timing
URL : https://patchwork.freedesktop.org/series/114306/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12774 -> Patchwork_114306v1
Summary
---
On Thu, 16 Feb 2023 16:58:50 -0800, Umesh Nerlige Ramappa wrote:
>
Hi Umesh,
> MTL introduces additional OA units dedicated to media use cases. Add
> support for programming these OA units by passing the media engine class
> and instance parameters.
>
> UMD specific changes for GPUvis support:
>
On Fri, Feb 24, 2023 at 12:11:40AM +0530, Badal Nilawar wrote:
> Apply Wa_14017073508 for MTL SoC die A step instead of graphics step.
> To get the SoC die stepping there is no direct interface so using
> revid as revid 0 aligns with SoC die A step.
>
> Bspec: 55420
This doesn't prove anything. I
== Series Details ==
Series: drm/i915/mtl: Apply Wa_14017073508 for MTL SoC Step
URL : https://patchwork.freedesktop.org/series/114307/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12774 -> Patchwork_114307v1
Summary
-
Apologies for the super slow reply, I put this series on the backburner while I
caught up on other stuff and completely missed your questions.
On Thu, Jan 19, 2023, Yan Zhao wrote:
> On Thu, Jan 19, 2023 at 10:58:42AM +0800, Zhenyu Wang wrote:
> > Current KVMGT usage is mostly in controlled mode,
== Series Details ==
Series: drm/i915/mtl: X-Tile support changes to client blits
URL : https://patchwork.freedesktop.org/series/114309/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12774 -> Patchwork_114309v1
Summary
On 22.02.2023 18:04, Peter Zijlstra wrote:
On Wed, Jan 18, 2023 at 04:35:22PM +0100, Andrzej Hajda wrote:
Andrzej Hajda (7):
arch: rename all internal names __xchg to __arch_xchg
linux/include: add non-atomic version of xchg
arch/*/uprobes: simplify arch_uretprobe_hijack_return_addr
On Wed, 2023-02-22 at 13:01 -0800, Teres Alexis, Alan Previn wrote:
> The Driver-FLR flow may inadvertently exit early before the full
> completion of the re-init of the internal HW state if we only poll
> GU_DEBUG Bit31 (polling for it to toggle from 0 -> 1). Instead
> we need a two-step completio
The Driver-FLR flow may inadvertently exit early before the full
completion of the re-init of the internal HW state if we only poll
GU_DEBUG Bit31 (polling for it to toggle from 0 -> 1). Instead
we need a two-step completion wait-for-completion flow that also
involves GU_CNTL. See the patch and new
On Tue, 2023-02-14 at 13:38 -0800, Teres Alexis, Alan Previn wrote:
> Add MTL's function for ARB session creation using PXP firmware
> version 4.3 ABI structure format.
>
alan:snip
>
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index aecc65b5da70
== Series Details ==
Series: drm/i915/gsc: Fix the Driver-FLR completion (rev2)
URL : https://patchwork.freedesktop.org/series/114269/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12774 -> Patchwork_114269v2
Summary
--
On Fri, 2023-02-17 at 03:12 +, Teres Alexis, Alan Previn wrote:
> On Tue, 2023-02-14 at 13:38 -0800, Teres Alexis, Alan Previn wrote:
> > Add MTL's function for ARB session creation using PXP firmware
> > version 4.3 ABI structure format.
>
> alan:snip
>
> Not part of this patch today but a n
On 2/23/2023 2:04 PM, Alan Previn wrote:
The Driver-FLR flow may inadvertently exit early before the full
completion of the re-init of the internal HW state if we only poll
GU_DEBUG Bit31 (polling for it to toggle from 0 -> 1). Instead
we need a two-step completion wait-for-completion flow tha
On 2/22/2023 1:01 PM, Alan Previn wrote:
The Driver-FLR flow may inadvertently exit early before the full
completion of the re-init of the internal HW state if we only poll
GU_DEBUG Bit31 (polling for it to toggle from 0 -> 1). Instead
we need a two-step completion wait-for-completion flow tha
Thanks Daniele, you are right about the fixes tag - i totally forgot that MTL
is still force-probe.
Will respin with the bit definition fix, remove the fixes-tag and leave out the
get/put runtime-pm from rev3 (as per your comment on rev3).
Rev4 coming right up.
...alan
P.S. I had the same thoug
The Driver-FLR flow may inadvertently exit early before the full
completion of the re-init of the internal HW state if we only poll
GU_DEBUG Bit31 (polling for it to toggle from 0 -> 1). Instead
we need a two-step completion wait-for-completion flow that also
involves GU_CNTL. See the patch and new
Xe_HP architecture already makes the CS_CTX_TIMESTAMP readable by
userspace on all engines; there's no longer a need to add it to the
software-managed whitelist for the non-RCS engines.
Bspec: 45545
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 11 +--
1 fil
A recommended tuning setting for both gen12 and Xe_HP platforms requires
that we grant userspace r/w access to the COMMON_SLICE_CHICKEN3
register.
Bspec: 73993, 73994, 31870, 68331
Cc: Dongwon Kim
Signed-off-by: Matt Roper
---
The bspec update to add COMMON_SLICE_CHICKEN3 to the tuning guide pag
== Series Details ==
Series: drm/i915/gsc: Fix the Driver-FLR completion (rev3)
URL : https://patchwork.freedesktop.org/series/114269/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12774 -> Patchwork_114269v3
Summary
--
1 - 100 of 119 matches
Mail list logo
