== Series Details ==
Series: drm/i915: fix TLB invalidation for Gen12.50 video and compute engines
URL : https://patchwork.freedesktop.org/series/111920/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12502 -> Patchwork_111920v1
=
On 13.12.2022 16:22, Tvrtko Ursulin wrote:
On 13/12/2022 14:52, Andrzej Hajda wrote:
On 13.12.2022 13:39, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
As the logic for selecting the register and corresponsing values
grew, the
code become a bit unsightly. Consolidate by storing the required
v
These patches enable HDCP2.x on machines MTL and above.
>From MTL onwards CSME is spilt into GSC and CSC and now
we use GSC CS instead of MEI to talk to firmware to start
HDCP authentication
--v2
-Fixing some checkpatch changes which I forgot before sending
out the series
--v3
-Drop cp and fw to
From: Anshuman Gupta
Change the include/drm/i915_mei_hdcp_interface.h to
include/drm/i915_cp_fw_hdcp_interface.h
Cc: Tomas Winkler
Cc: Rodrigo Vivi
Cc: Uma Shankar
Cc: Ankit Nautiyal
Signed-off-by: Anshuman Gupta
Signed-off-by: Suraj Kandpal
Acked-by: Tomas Winkler
---
.../drm/i915/displ
From: Anshuman Gupta
As now we have more then one type of content protection
secrity firmware. Let change the i915_cp_fw_hdcp_interface.h
header naming convention to suit generic f/w type.
%s/MEI_/HDCP_
%s/mei_dev/hdcp_dev
As interface to CP FW can be either a non i915 component or
i915 intergra
HDCP and PXP will require a common function to allow it to
submit commands to the gsc cs. Also adding the gsc mtl header
that needs to be added on to the existing payloads of HDCP
and PXP.
Cc: Daniele Ceraolo Spurio
Cc: Alan Previn
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/gt/intel_
MTL uses GSC command streamer i.e gsc cs to send HDCP/PXP commands
to GSC f/w. It requires to keep hdcp display driver
agnostic to content protection f/w (ME/GSC fw) in the form of
i915_hdcp_fw_ops generic ops.
Adding HDCP GSC CS interface by leveraging the i915_hdcp_fw_ops generic
ops instead of
Add function that takes care of sending command to gsc cs. We start
of with allocation of memory for our command intel_hdcp_gsc_message that
contains gsc cs memory header as directed in specs followed by the
actual payload hdcp message that we want to send.
Spec states that we need to poll pending
It requires to move intel specific HDCP API structures to
i915_cp_fw_hdcp_interface.h from driver/misc/mei/hdcp/mei_hdcp.h
so that any content protection fw interfaces can use these
structures.
Cc: Tomas Winkler
Cc: Rodrigo Vivi
Cc: Uma Shankar
Cc: Ankit Nautiyal
Signed-off-by: Anshuman Gupta
Need to fill wired cmd in structures at a single place as they remain
same for both gsc and mei.
--v3
-remove inline function from header [Jani]
Cc: Ankit Nautiyal
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_hdcp_interface.c |
On Wed, 14 Dec 2022, "Murthy, Arun R" wrote:
>> -Original Message-
>> From: Intel-gfx On Behalf Of Jani
>> Nikula
>> Sent: Monday, December 12, 2022 7:59 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani
>> Subject: [Intel-gfx] [PATCH 2/7] drm/i915/display: move more scanline
On Wed, 14 Dec 2022, "Murthy, Arun R" wrote:
>> -Original Message-
>> From: Intel-gfx On Behalf Of Jani
>> Nikula
>> Sent: Monday, December 12, 2022 7:59 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani
>> Subject: [Intel-gfx] [PATCH 0/7] drm/i915: extract vblank/scanline co
== Series Details ==
Series: Enable HDCP2.x via GSC CS (rev3)
URL : https://patchwork.freedesktop.org/series/111876/
State : warning
== Summary ==
Error: dim checkpatch failed
96a311246cfb drm/i915/gsc: Create GSC request submission mechanism
Traceback (most recent call last):
File "scripts/
== Series Details ==
Series: Enable HDCP2.x via GSC CS (rev3)
URL : https://patchwork.freedesktop.org/series/111876/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Wed, 14 Dec 2022, Arun R Murthy wrote:
> The busy timeout logic checks for the AUX BUSY, then waits for the
> timeout period and then after timeout reads the register for BUSY or
> Success.
> Instead replace interrupt with polling so as to read the AUX CTL
> register often before the timeout pe
== Series Details ==
Series: Enable HDCP2.x via GSC CS (rev3)
URL : https://patchwork.freedesktop.org/series/111876/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12502 -> Patchwork_111876v3
Summary
---
**SUCCESS**
On Tue, Nov 29, 2022 at 09:19:40PM +0200, Srivatsa, Anusha wrote:
>
>
> > -Original Message-
> > From: Intel-gfx On Behalf Of
> > Stanislav Lisovskiy
> > Sent: Thursday, November 24, 2022 2:36 AM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Nikula, Jani
> > Subject: [Intel-gfx] [PATC
Hi Andrzej,
On Wed, Dec 14, 2022 at 08:54:39AM +0100, Andrzej Hajda wrote:
> In case of Gen12.50 video and compute engines, TLB_INV registers are
> masked - to modify one bit, corresponding bit in upper half of the register
> must be enabled, otherwise nothing happens.
>
> Fixes: 77fa9efc16a9 ("d
== Series Details ==
Series: series starting with [1/2] drm/i915: fix TLB invalidation for Gen12.50
video and compute engines (rev3)
URL : https://patchwork.freedesktop.org/series/111744/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12501_full -> Patchwork_111744v3_full
On 14/12/2022 03:32, Mani Milani wrote:
Thank you for the patch.
I briefly tested this patch and it does fix my original problem of
"user-space application crashing due to receiving an -ENOSPC". Once
the code is reviewed, I can test it further and report back.
However, there are a few changes i
On 07-12-2022 23:41, Matt Roper wrote:
> On Wed, Dec 07, 2022 at 12:56:44PM +0530, Iddamsetty, Aravind wrote:
>>
>>
>> On 07-12-2022 05:09, Matt Roper wrote:
>>> On Tue, Dec 06, 2022 at 01:07:28PM +0530, Aravind Iddamsetty wrote:
Add a separate PTE encode function for MTL. The number of PAT
On Mon, Dec 12, 2022 at 03:35:20PM +0100, Jason A. Donenfeld wrote:
> Please CC me on future revisions.
>
> As of 6.2, the prandom namespace is *only* for predictable randomness.
> There's no need to rename anything. So nack on this patch 1/5.
It is not obvious (for casual developers like me) tha
On Tue, Dec 13, 2022 at 11:59:24AM +0200, Jani Nikula wrote:
> Starting from ICL, the default for MIPI GPIO sequences seems to be using
> native GPIOs i.e. GPIOs available in the GPU. These native GPIOs reuse
> many pins that quite frankly seem scary to poke based on the VBT
> sequences. We pretty
== Series Details ==
Series: drm/i915/gt: Modify mismatched function name
URL : https://patchwork.freedesktop.org/series/111886/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12501_full -> Patchwork_111886v1_full
Summary
--
On Mon, Dec 12, 2022 at 04:29:25PM +0200, Jani Nikula wrote:
> Reduce clutter in i915_reg.h by splitting out the vblank/scanline
> registers.
>
> Cc: Ville Syrjälä
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_crt.c | 1 +
> drivers/gpu/drm/i915/display/intel_vbl
On Mon, Dec 12, 2022 at 04:29:22PM +0200, Jani Nikula wrote:
> Let's not have scanline waits inline in hdmi code.
>
> This kind of waits should really have timeouts; add a FIXME comment.
>
> Cc: Ville Syrjälä
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_hdmi.c | 9
== Series Details ==
Series: series starting with [1/2] drm/i915: use proper helper in
igt_vma_move_to_active_unlocked
URL : https://patchwork.freedesktop.org/series/111892/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12501_full -> Patchwork_111892v1_full
==
The busy timeout logic checks for the AUX BUSY, then waits for the
timeout period and then after timeout reads the register for BUSY or
Success.
Instead replace interrupt with polling so as to read the AUX CTL
register often before the timeout period. Looks like there might be some
issue with inter
On Wed, Dec 14, 2022 at 04:15:49PM +0100, Eric Dumazet wrote:
> On Wed, Dec 14, 2022 at 1:34 PM Stanislaw Gruszka
> wrote:
> >
> > On Mon, Dec 12, 2022 at 03:35:20PM +0100, Jason A. Donenfeld wrote:
> > > Please CC me on future revisions.
> > >
> > > As of 6.2, the prandom namespace is *only* for
On Tue, Dec 13, 2022 at 03:41:19PM -0800, Matt Roper wrote:
> Programming of the ENABLE_PREFETCH_INTO_IC bit originally showed up in
> both the general DG2 tuning guide (applicable to all DG2
> variants/steppings) and under Wa_22012654132 (applicable only to
> specific steppings). It has now been
== Series Details ==
Series: drm/i915/dp: wait on timeout before retry include sw delay (rev5)
URL : https://patchwork.freedesktop.org/series/111303/
State : warning
== Summary ==
Error: make htmldocs had i915 warnings
./drivers/gpu/drm/i915/display/intel_dsb.c:201: warning: Excess function
p
On Wed, Dec 14, 2022 at 05:21:17PM +0100, Stanislaw Gruszka wrote:
> On Wed, Dec 14, 2022 at 04:15:49PM +0100, Eric Dumazet wrote:
> > On Wed, Dec 14, 2022 at 1:34 PM Stanislaw Gruszka
> > wrote:
> > >
> > > On Mon, Dec 12, 2022 at 03:35:20PM +0100, Jason A. Donenfeld wrote:
> > > > Please CC me o
== Series Details ==
Series: series starting with [1/2] drm/i915: fix TLB invalidation for Gen12.50
video and compute engines
URL : https://patchwork.freedesktop.org/series/111895/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12501_full -> Patchwork_111895v1_full
===
== Series Details ==
Series: drm/i915/dp: wait on timeout before retry include sw delay (rev5)
URL : https://patchwork.freedesktop.org/series/111303/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12505 -> Patchwork_111303v5
If the sink gets disconnected during receiving a multi-packet DP MST AUX
down-reply/up-request sideband message, the state keeping track of which
packets have been received already is not reset. This results in a failed
sanity check for the subsequent message packet received after a sink is
reconne
If an MST stream is enabled on a disconnected sink, the payload for the
stream is not created and the MST manager's payload count/next start VC
slot is not updated. Since the payload's start VC slot may still contain
a valid value (!= -1) the subsequent disabling of such a stream could
cause an inc
After an error during receiving a packet for a multi-packet DP MST
sideband message, the state tracking which packets have been received
already is not reset. This prevents the reception of subsequent down
messages (due to the pending message not yet completed with an
end-of-message-transfer packet
> -Original Message-
> From: Lisovskiy, Stanislav
> Sent: Wednesday, December 14, 2022 2:31 AM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani
> Subject: Re: [Intel-gfx] [PATCH 1/1] drm/i915: Implement workaround for
> CDCLK PLL disable/enable
>
> On Tue, N
The attribute __maybe_unused should remain only until the respective
info is not in the pciidlist. The info can't be added together
with its definition because that would cause the driver to automatically
probe for the device, while it's still not ready for that. However once
pciidlist contains it,
> -Original Message-
> From: De Marchi, Lucas
> Sent: Wednesday, December 14, 2022 11:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Sripada, Radhakrishna ; De Marchi, Lucas
>
> Subject: [PATCH] drm/i915: Remove __maybe_unused from used
>
> The attribute __maybe_unused should remai
== Series Details ==
Series: series starting with [1/3] drm/display/dp_mst: Fix down/up message
handling after sink disconnect
URL : https://patchwork.freedesktop.org/series/111943/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12506 -> Patchwork_111943v1
== Series Details ==
Series: drm/i915: Remove __maybe_unused from used
URL : https://patchwork.freedesktop.org/series/111945/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12506 -> Patchwork_111945v1
Summary
---
**SU
For the whole series:
Reviewed-by: Lyude Paul
Thanks!
On Wed, 2022-12-14 at 20:42 +0200, Imre Deak wrote:
> If the sink gets disconnected during receiving a multi-packet DP MST AUX
> down-reply/up-request sideband message, the state keeping track of which
> packets have been received already is
Hi Rodrigo,
On Tue, Dec 13, 2022 at 01:18:48PM +, Vivi, Rodrigo wrote:
> On Tue, 2022-12-13 at 00:08 +0100, Andi Shyti wrote:
> > Hi Rodrigo,
> >
> > On Mon, Dec 12, 2022 at 11:55:10AM -0500, Rodrigo Vivi wrote:
> > > On Mon, Dec 12, 2022 at 05:13:38PM +0100, Andi Shyti wrote:
> > > > From: C
While debugging page table faults it's useful not to kill the machine
with thousands of error mesages. Ratelimit all errors in
gen8_de_irq_handler().
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_irq.c | 28 ++--
1 file changed, 14 insertions(+), 14 deletio
== Series Details ==
Series: drm/i915: ratelimit errors in display engine irq
URL : https://patchwork.freedesktop.org/series/111951/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12506 -> Patchwork_111951v1
Summary
---
> -Original Message-
> From: Nikula, Jani
> Sent: Wednesday, December 14, 2022 2:49 PM
> To: Murthy, Arun R ; intel-
> g...@lists.freedesktop.org
> Subject: RE: [Intel-gfx] [PATCH 0/7] drm/i915: extract vblank/scanline code to
> a separate file
>
> On Wed, 14 Dec 2022, "Murthy, Arun R" w
> -Original Message-
> From: Nikula, Jani
> Sent: Wednesday, December 14, 2022 2:45 PM
> To: Murthy, Arun R ; intel-
> g...@lists.freedesktop.org
> Subject: RE: [Intel-gfx] [PATCH 2/7] drm/i915/display: move more scanline
> functions to intel_vblank.[ch]
>
> On Wed, 14 Dec 2022, "Murthy,
> -Original Message-
> From: Nautiyal, Ankit K
> Sent: Wednesday, December 14, 2022 12:43 PM
> To: Murthy, Arun R ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/hdmi: Go for scrambling only if
> platform supports TMDS clock > 340MHz
>
>
> On 12/14/2022
== Series Details ==
Series: drm/i915/dg2: Return Wa_22012654132 to just specific steppings
URL : https://patchwork.freedesktop.org/series/111912/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12502_full -> Patchwork_111912v1_full
==
Thanks for the explanations Matthew. It all makes sense now. I will
now test this patch further and report back the results.
There is just one comment block that needs to be updated I think. See below:
On Wed, Dec 14, 2022 at 10:47 PM Matthew Auld wrote:
>
...
> >> diff --git a/drivers/gpu/drm/i
== Series Details ==
Series: drm/i915/display: Enable VDIP Enable VSC whenever GMP DIP enabled (rev2)
URL : https://patchwork.freedesktop.org/series/111835/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12491_full -> Patchwork_111835v2_full
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