On 11/25/2022 5:54 AM, Ville Syrjälä wrote:
On Thu, Nov 10, 2022 at 04:56:51PM -0800, Daniele Ceraolo Spurio wrote:
The fence is always initialized in huc_init_early, but the cleanup in
huc_fini is only being run if HuC is enabled. This causes a leaking of
the debug object when HuC is disable
On Sat, 26 Nov 2022, Mikko Kovanen wrote:
> intel_dsi->ports contains bitmask of enabled ports and correspondingly
> logic for selecting port for VBT packet sending must use port specific
> bitmask when deciding appropriate port.
>
> Fixes: 08c59dde71b7 ("drm/i915/dsi: fix VBT send packet port sel
From: Pallavi Mishra
Caching mode for an object shall be selected via upcoming VM_BIND
interface.
Cc: Lucas De Marchi
Cc: Matt Roper
Cc: Joonas Lahtinen
Signed-off-by: Pallavi Mishra
Signed-off-by: Aravind Iddamsetty
---
drivers/gpu/drm/i915/gem/i915_gem_domain.c | 3 +++
1 file changed,
Add a separate PTE encode function for MTL. The number of PAT registers
have increased to 16 on MTL. All 16 PAT registers are available for
PPGTT mapped pages, but only the lower 4 are available for GGTT mapped
pages.
BSPEC: 63884
Cc: Lucas De Marchi
Cc: Matt Roper
Co-developed-by: Fei Yang
Si
From: Madhumitha Tolakanahalli Pradeep
On MTL due to the introduction of L4 cache, coherency and cacheability
selections are different and also GT can no longer allocate on LLC. The
MOCS/PAT tables needs an update.
BSpec: 44509, 45101, 44235
Cc: Matt Roper
Cc: Lucas De Marchi
Signed-off-by:
On 25/11/2022 22:30, Andi Shyti wrote:
From: Chris Wilson
Introduce the concept of padding the i915_vma with guard pages before
and after. The major consequence is that all ordinary uses of i915_vma
must use i915_vma_offset/i915_vma_size and not i915_vma.node.start/size
directly, as the drm_m
On 25/11/2022 22:30, Andi Shyti wrote:
Chris commit "drm/i915: Introduce guard pages to i915_vma" was
"cunningly" changing display_alignment to u32 from u64. The
reason is that the display GGTT is and will be limited o 4GB.
Put it in a separate patch and use "max(...)" instead of
"max_t(64, ..
Add helper to get the DSC bits_per_pixel precision for the DP sink.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/display/drm_dp_helper.c | 27 +
include/drm/display/drm_dp_helper.h | 1 +
2 files changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/display/dr
Add a check to use force DSC bpc only if its less that the connector max
requested bpc.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 23 ++-
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
DSC parameter bits_per_pixel is stored in U6.4 format.
The 4 bits represent the fractional part of the bpp.
Currently we use compressed_bpp member of dsc structure to store
only the integral part of the bits_per_pixel.
To store the full bits_per_pixel along with the fractional part,
compressed_bpp
Currently we the required dsc output bpp is set to be the largest
compressed bpp supported for max, lane, rate, and bpp.
The helper intel_dp_dsc_get_output_bpp gets the maximum supported
compressed bpp taking into account link configuration, input bpp,
bigjoiner considerations etc.
Append 'max' su
This patch series adds support for having fractional compressed bpp
for MTL+. The initial patches that lay groundwork to iterate over valid
compressed bpps to select the 'best' compressed bpp with optimal link
configuration are taken from upstream pending series:
https://patchwork.freedesktop.org/s
Currently, we take the max lane, rate and pipe bpp, to get the maximum
compressed bpp possible. We then set the output bpp to this value.
This patch provides support to have max bpp, min rate and min lanes,
that can support the min compressed bpp.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/dr
MTL+ supports fractional compressed bits_per_pixel, with precision of
1/16. This compressed bpp is stored in U6.4 format.
Accommodate this precision while computing m_n values.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +-
drivers/gpu/drm/i915/display
MTL+ supports fractional compressed bits_per_pixel, with precision of
1/16. This compressed bpp is stored in U6.4 format.
Accommodate the precision during calculation of transfer unit data
for hblank_early calculation.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_audio.c
From: Swati Sharma
DSC_Sink_BPP_Precision entry is added to i915_dsc_fec_support_show
to depict sink's precision.
Also, new debugfs entry is created to enforce fractional bpp.
If Force_DSC_Fractional_BPP_en is set then while iterating over
output bpp with fractional step size we will continue if
This patch adds support to iterate over compressed output bpp as per the
fractional step, supported by DP sink.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 45 +++--
1 file changed, 27 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/dr
From: Vandita Kulkarni
Consider the fractional bpp while reading the qp values.
Signed-off-by: Vandita Kulkarni
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_qp_tables.c | 3 ---
drivers/gpu/drm/i915/display/intel_vdsc.c | 12 +---
2 files changed, 9 inser
From: Swati Sharma
If force_dsc_fractional_bpp_en is set through debugfs allow DSC iff
compressed bpp is fractional. Continue if we computed compressed bpp is
computed as integer.
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/display/intel_dp.c | 6 ++
1 file changed, 6 insertions(+
When (size != 0 || ptrs->lvds_ entries != 3), the program tries to
free() the ptrs. However, the ptrs is not created by calling kzmalloc(),
but is obtained by pointer offset operation.
This may lead to memory leaks or undefined behavior.
Fix this by replacing the arguments of kfree() with ptrs_blo
intel_dsi->ports contains bitmask of enabled ports and correspondingly
logic for selecting port for VBT packet sending must use port specific
bitmask when deciding appropriate port.
Fixes: 08c59dde71b7 ("drm/i915/dsi: fix VBT send packet port selection for
ICL+")
Cc: sta...@vger.kernel.org
Signed
On 11/22/2022 8:10 AM, Dixit, Ashutosh wrote:
On Sun, 20 Nov 2022 23:29:46 -0800, Riana Tauro wrote:
diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c
b/drivers/gpu/drm/i915/gt/selftest_rc6.c
index 15b84c428f66..845058ed83ed 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
+++ b/driver
== Series Details ==
Series: series starting with [1/3] drm/i915/mtl: Define MOCS and PAT tables for
MTL
URL : https://patchwork.freedesktop.org/series/111390/
State : warning
== Summary ==
Error: dim checkpatch failed
3a4cce54c504 drm/i915/mtl: Define MOCS and PAT tables for MTL
42fb2a23d315
On Sun, Nov 27, 2022 at 10:52:32AM +0530, Ankit Nautiyal wrote:
> After enabling DDI_BUF_CTL, wait for DDI_BUF_CTL to be active.
> Bspec:4232,53339,49191,54145
>
> Signed-off-by: Ankit Nautiyal
Looks ok to me. On the series:
Reviewed-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/intel_d
== Series Details ==
Series: series starting with [1/3] drm/i915/mtl: Define MOCS and PAT tables for
MTL
URL : https://patchwork.freedesktop.org/series/111390/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12438 -> Patchwork_111390v1
==
== Series Details ==
Series: Add DSC fractional bpp support
URL : https://patchwork.freedesktop.org/series/111391/
State : warning
== Summary ==
Error: dim checkpatch failed
d0e4e48ec58b drm/i915/dp: Check if force dsc bpc <= max requested bpc
22a420e3ce87 drm/display/dp: Add helper function t
== Series Details ==
Series: Add DSC fractional bpp support
URL : https://patchwork.freedesktop.org/series/111391/
State : warning
== Summary ==
Error: make htmldocs had i915 warnings
./drivers/gpu/drm/i915/gt/intel_gt_mcr.c:739: warning: expecting prototype for
intel_gt_mcr_wait_for_reg_fw()
== Series Details ==
Series: Add DSC fractional bpp support
URL : https://patchwork.freedesktop.org/series/111391/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12438 -> Patchwork_111391v1
Summary
---
**SUCCESS**
On Mon, Nov 28, 2022 at 01:10:58AM -0800, Ceraolo Spurio, Daniele wrote:
>
>
> On 11/25/2022 5:54 AM, Ville Syrjälä wrote:
> > On Thu, Nov 10, 2022 at 04:56:51PM -0800, Daniele Ceraolo Spurio wrote:
> >> The fence is always initialized in huc_init_early, but the cleanup in
> >> huc_fini is only b
== Series Details ==
Series: drm/i915/bios: fix a memory leak in generate_lfp_data_ptrs
URL : https://patchwork.freedesktop.org/series/111392/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12438 -> Patchwork_111392v1
Summar
== Series Details ==
Series: drm/i915/dsi: fix VBT send packet port selection for dual link DSI
(rev2)
URL : https://patchwork.freedesktop.org/series/111366/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12438 -> Patchwork_111366v2
== Series Details ==
Series: series starting with [1/3] drm/i915/mtl: Define MOCS and PAT tables for
MTL
URL : https://patchwork.freedesktop.org/series/111390/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12438_full -> Patchwork_111390v1_full
On 11/28/2022 5:08 AM, Ville Syrjälä wrote:
On Mon, Nov 28, 2022 at 01:10:58AM -0800, Ceraolo Spurio, Daniele wrote:
On 11/25/2022 5:54 AM, Ville Syrjälä wrote:
On Thu, Nov 10, 2022 at 04:56:51PM -0800, Daniele Ceraolo Spurio wrote:
The fence is always initialized in huc_init_early, but th
In case context is exiting preempt_timeout_ms is used for timeout,
but since introduction of DRM_I915_PREEMPT_TIMEOUT_COMPUTE it increases
to 7.5 seconds. Heartbeat occurs earlier but it is still 2.5s.
Fixes: d7a8680ec9fb21 ("drm/i915: Improve long running compute w/a for GuC
submission")
Closes:
== Series Details ==
Series: Add DSC fractional bpp support
URL : https://patchwork.freedesktop.org/series/111391/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12438_full -> Patchwork_111391v1_full
Summary
---
**SUC
I found issue with this patch:
There is a time window between psr_invalidate/flush and next vblank
where atomic commit with selective update will cause full frame update
being lost due to overwriting the configuration.
I will send a new version.
On Fri, 2022-11-25 at 15:43 +0200, Jouni Högander
== Series Details ==
Series: Align DDI_BUF_CTL Active timeouts with Bspec updates (rev2)
URL : https://patchwork.freedesktop.org/series/111373/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12439 -> Patchwork_111373v2
Summa
== Series Details ==
Series: drm/i915: fix exiting context timeout calculation
URL : https://patchwork.freedesktop.org/series/111402/
State : warning
== Summary ==
Error: dim checkpatch failed
a049dd461775 drm/i915: fix exiting context timeout calculation
-:10: WARNING:BAD_FIXES_TAG: Please us
== Series Details ==
Series: drm/i915/bios: fix a memory leak in generate_lfp_data_ptrs
URL : https://patchwork.freedesktop.org/series/111392/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12438_full -> Patchwork_111392v1_full
==
On Wed, Nov 23, 2022 at 04:45:25PM -0300, Gustavo Sousa wrote:
> On Wed, Nov 23, 2022 at 10:36:47AM -0800, Matt Atwood wrote:
> > Wa_18018764978 applies to specific steppings of DG2 (G10 C0+,
> > G11 and G12 A0+). Clean up style in function at the same time.
> >
> > Bspec: 66622
> >
> > Signed-of
Hi Eric,
On Mon, Nov 28, 2022 at 7:22 PM Eric W. Biederman wrote:
>
> Tvrtko Ursulin writes:
>
> > On 19/10/2022 21:19, Jason A. Donenfeld wrote:
> >> On Wed, Oct 19, 2022 at 09:09:28PM +0100, Tvrtko Ursulin wrote:
> >>> Hm why is kthread_stop() after kthread_run() abuse? I don't see it in
> >>>
== Series Details ==
Series: drm/i915: fix exiting context timeout calculation
URL : https://patchwork.freedesktop.org/series/111402/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12439 -> Patchwork_111402v1
Summary
---
On Wed, Nov 23, 2022 at 06:49:16PM +0200, Jani Nikula wrote:
> Remove rmw_set(), rmw_clear(), clear_register(), rmw_set_fw(), and
> rmw_clear_fw(). They're just one too many levels of abstraction for
> register access, for very specific purposes.
>
> clear_register() seems like a micro-optimizatio
On 11/23/2022 15:54, Daniele Ceraolo Spurio wrote:
The fence is only tracking if the HuC load is in progress or not and
doesn't distinguish between already loaded, not supported or disabled,
so we can always initialize it to completed, no matter the actual
support. We already do that for most pla
== Series Details ==
Series: drm/i915/dsi: fix VBT send packet port selection for dual link DSI
(rev2)
URL : https://patchwork.freedesktop.org/series/111366/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12438_full -> Patchwork_111366v2_full
==
Hello,
On Thu, Nov 24, 2022 at 02:32:25PM +, Tvrtko Ursulin wrote:
> > Soft limits is a bit of misnomer and can be confused with best-effort limits
> > such as memory.high. Prolly best to not use the term.
>
> Are you suggesting "best effort limits" or "best effort "? It
> would sounds good t
> From: Iddamsetty, Aravind
> Sent: Monday, November 28, 2022 2:14 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas ; Roper, Matthew D
> ; Yang, Fei
> Subject: [PATCH 2/3] drm/i915/mtl: Define new PTE encode for MTL
>
> Add a separate PTE encode function for MTL. The number of PAT
On Mon, Nov 28, 2022 at 03:43:52PM +0530, Aravind Iddamsetty wrote:
From: Pallavi Mishra
Caching mode for an object shall be selected via upcoming VM_BIND
interface.
last I've heard there was no plan to support this through VM_BIND. Did
anything change? Otherwise this needs a better explanat
On Mon, Nov 28, 2022 at 03:43:51PM +0530, Aravind Iddamsetty wrote:
Add a separate PTE encode function for MTL. The number of PAT registers
have increased to 16 on MTL. All 16 PAT registers are available for
PPGTT mapped pages, but only the lower 4 are available for GGTT mapped
pages.
this woul
On 23.11.2022 17:49, Jani Nikula wrote:
Remove rmw_set(), rmw_clear(), clear_register(), rmw_set_fw(), and
rmw_clear_fw(). They're just one too many levels of abstraction for
register access, for very specific purposes.
clear_register() seems like a micro-optimization bypassing the write
when th
== Series Details ==
Series: drm/i915/huc: always init the delayed load fence (rev2)
URL : https://patchwork.freedesktop.org/series/111288/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12440 -> Patchwork_111288v2
Summary
-
== Series Details ==
Series: Align DDI_BUF_CTL Active timeouts with Bspec updates (rev2)
URL : https://patchwork.freedesktop.org/series/111373/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12439_full -> Patchwork_111373v2_full
=
We've been overloading uncore->lock to protect access to the MCR
steering register. That's not really what uncore->lock is intended for,
and it would be better if we didn't need to hold such a high-traffic
spinlock for the whole sequence of (apply steering, access MCR register,
restore steering).
We've been overloading uncore->lock to protect access to the MCR
steering register. That's not really what uncore->lock is intended for,
and it would be better if we didn't need to hold such a high-traffic
spinlock for the whole sequence of (apply steering, access MCR register,
restore steering).
Passing the GT rather than uncore to the lowest level MCR read and write
functions will make it easier to introduce dedicated MCR locking in a
following patch.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 18 ++
1 file changed, 10 insertions(+), 8 deleti
Starting with MTL, the driver needs to not only protect the steering
control register from simultaneous software accesses, but also protect
against races with hardware/firmware agents. The hardware provides a
dedicated locking mechanism to support this via the MTL_STEER_SEMAPHORE
register. Readin
PPAT setup involves a series of multicast writes. This can be optimized
slightly be acquiring forcewake and the steering lock just once for the
entire sequence.
Suggested-by: Balasubramani Vivekanandan
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gtt.c | 27 +++--
The kerneldoc function name was not updated when this function was
converted to a non-fw form.
Fixes: 192bb40f030a ("drm/i915/gt: Manage uncore->lock while waiting on MCR
register")
Reported-by: kernel test robot
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 2 +-
1 fi
On 29-11-2022 01:22, Yang, Fei wrote:
>> From: Iddamsetty, Aravind
>> Sent: Monday, November 28, 2022 2:14 AM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: De Marchi, Lucas ; Roper, Matthew D
>> ; Yang, Fei
>> Subject: [PATCH 2/3] drm/i915/mtl: Define new PTE encode for MTL
>>
>> Add a separa
== Series Details ==
Series: i915: dedicated MCR locking and hardware semaphore (rev2)
URL : https://patchwork.freedesktop.org/series/111220/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: i915: dedicated MCR locking and hardware semaphore (rev2)
URL : https://patchwork.freedesktop.org/series/111220/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12440 -> Patchwork_111220v2
Summary
> -Original Message-
> From: Kahola, Mika
> Sent: Friday, October 14, 2022 5:47 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Kahola, Mika ; Taylor, Clinton A
> ; Sripada, Radhakrishna
>
> Subject: [PATCH 01/20] drm/i915/mtl: Initial DDI port setup
>
> From: Clint Taylor
>
> Initia
Starting with MTL, there will be two GT-tiles, a render and media
tile. PXP as a service for supporting workloads with protected
contexts and protected buffers can be subscribed by process
workloads on any tile. However, depending on the platform,
only one of the tiles is used for control events pe
MTL has two tiles that is represented by the intel_gt structure in the i915
code. The PXP feature has a control-structure that currently hangs off the
intel_gt structure. In MTL, the standalone media tile (i.e. not the root
tile) contains the VDBOX and KCR engine which are among several assets
that
== Series Details ==
Series: drm/i915: fix exiting context timeout calculation
URL : https://patchwork.freedesktop.org/series/111402/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12439_full -> Patchwork_111402v1_full
Summa
A driver bug was recently discovered where the security firmware was
receiving internal HW signals indicating that session key expirations
had occurred. Architecturally, the firmware was expecting a response
from the GuC to acknowledge the event with the firmware side.
However the OS was in a suspe
A gap was recently discovered where if an application did not
invalidate all of the stream keys (intentionally or not), and the
driver did a full PXP global teardown on the GT subsystem, we
find that future session creation would fail on the security
firmware's side of the equation. i915 is the ent
During suspend flow, i915 currently achors' on the pm_suspend_prepare
callback as the location where we quiesce the entire GPU and perform
all necessary cleanup in order to go into suspend. PXP is also called
during this time to perform the arbitration session teardown (with
the assurance no additi
A customer issue was recently discovered and in the process a
gap in i915's PXP interaction with HW+FW architecure was also
realized. This series adds those missing pieces.
The patches explain the details.
Changes from prior revs:
v1: - Dont need to teardown non arbitration sessions (Juston).
(++tagging Rodrigo)
This series is a replacement for
https://patchwork.freedesktop.org/series/109429/. Patchwork bestowed a new URL
as the
series is significantly different now with the new design approach direction
from Rodrigo.
...alan
On Mon, 2022-11-28 at 16:31 -0800, Alan Previn wrote:
>
== Series Details ==
Series: drm/i915/pxp: Prepare intel_pxp entry points for MTL
URL : https://patchwork.freedesktop.org/series/111408/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/pxp: Prepare intel_pxp entry points for MTL
URL : https://patchwork.freedesktop.org/series/111408/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12440 -> Patchwork_111408v1
Summary
As part of OA support for MTL,
- Enable 32 bit OAG formats for MTL.
- 0x200c is repurposed on MTL. Use a separate mux table to verify oa
configs passed by user.
- Similar to ACM, OA/CS timestamp is mismatched on MTL. Add MTL to the
WA.
- On MTL, gt->scratch was using stolen lmem. An MI_SRM to
== Series Details ==
Series: drm/i915/perf: Do not parse context image for HSW (rev4)
URL : https://patchwork.freedesktop.org/series/111231/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12440 -> Patchwork_111231v4
Summary
== Series Details ==
Series: drm/i915/pxp: Add missing cleanup steps for PXP global-teardown
URL : https://patchwork.freedesktop.org/series/111409/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/pxp: Add missing cleanup steps for PXP global-teardown
URL : https://patchwork.freedesktop.org/series/111409/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12440 -> Patchwork_111409v1
S
== Series Details ==
Series: drm/i915/mtl: Add support for 32 bit OAG formats in MTL
URL : https://patchwork.freedesktop.org/series/111411/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/mtl: Add support for 32 bit OAG formats in MTL
URL : https://patchwork.freedesktop.org/series/111411/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12440 -> Patchwork_111411v1
Summary
-
On 29-11-2022 01:57, Lucas De Marchi wrote:
> On Mon, Nov 28, 2022 at 03:43:51PM +0530, Aravind Iddamsetty wrote:
>> Add a separate PTE encode function for MTL. The number of PAT registers
>> have increased to 16 on MTL. All 16 PAT registers are available for
>> PPGTT mapped pages, but only the
== Series Details ==
Series: drm/i915/huc: always init the delayed load fence (rev2)
URL : https://patchwork.freedesktop.org/series/111288/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12440_full -> Patchwork_111288v2_full
On 29-11-2022 01:49, Lucas De Marchi wrote:
> On Mon, Nov 28, 2022 at 03:43:52PM +0530, Aravind Iddamsetty wrote:
>> From: Pallavi Mishra
>>
>> Caching mode for an object shall be selected via upcoming VM_BIND
>> interface.
>
> last I've heard there was no plan to support this through VM_BIND.
On Wed, Nov 23, 2022 at 09:47:03AM +0530, Iddamsetty, Aravind wrote:
On 23-11-2022 05:29, Matt Roper wrote:
On Tue, Nov 22, 2022 at 12:31:26PM +0530, Aravind Iddamsetty wrote:
On XE_LPM+ platforms the media engines are carved out into a separate
GT but have a common GGTMMADR address range whi
On 29-11-2022 11:24, Lucas De Marchi wrote:
> On Wed, Nov 23, 2022 at 09:47:03AM +0530, Iddamsetty, Aravind wrote:
>>
>>
>> On 23-11-2022 05:29, Matt Roper wrote:
>>> On Tue, Nov 22, 2022 at 12:31:26PM +0530, Aravind Iddamsetty wrote:
On XE_LPM+ platforms the media engines are carved out in
== Series Details ==
Series: i915: dedicated MCR locking and hardware semaphore (rev2)
URL : https://patchwork.freedesktop.org/series/111220/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12440_full -> Patchwork_111220v2_full
===
On Tue, Nov 29, 2022 at 11:33:15AM +0530, Iddamsetty, Aravind wrote:
On 29-11-2022 11:24, Lucas De Marchi wrote:
On Wed, Nov 23, 2022 at 09:47:03AM +0530, Iddamsetty, Aravind wrote:
On 23-11-2022 05:29, Matt Roper wrote:
On Tue, Nov 22, 2022 at 12:31:26PM +0530, Aravind Iddamsetty wrote:
On Tue, Nov 29, 2022 at 09:58:03AM +0530, Iddamsetty, Aravind wrote:
On 29-11-2022 01:57, Lucas De Marchi wrote:
On Mon, Nov 28, 2022 at 03:43:51PM +0530, Aravind Iddamsetty wrote:
Add a separate PTE encode function for MTL. The number of PAT registers
have increased to 16 on MTL. All 16 PAT
On Mon, Nov 28, 2022 at 05:21:46PM -0800, Umesh Nerlige Ramappa wrote:
As part of OA support for MTL,
- Enable 32 bit OAG formats for MTL.
- 0x200c is repurposed on MTL. Use a separate mux table to verify oa
configs passed by user.
- Similar to ACM, OA/CS timestamp is mismatched on MTL. Add MTL
== Series Details ==
Series: drm/i915/perf: Do not parse context image for HSW (rev4)
URL : https://patchwork.freedesktop.org/series/111231/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12440_full -> Patchwork_111231v4_full
DRM_I915_GEM_VM_BIND/UNBIND ioctls allows UMD to bind/unbind GEM
buffer objects (BOs) or sections of a BOs at specified GPU virtual
addresses on a specified address space (VM). Multiple mappings can map
to the same physical pages of an object (aliasing). These mappings (also
referred to as persiste
Rename __i915_request_await_bind() as i915_request_await_bind()
and make it non-static as it will be used in execbuf3 ioctl path.
v2: add documentation
Reviewed-by: Matthew Auld
Reviewed-by: Andi Shyti
Signed-off-by: Niranjana Vishwanathapura
---
drivers/gpu/drm/i915/i915_vma.c | 8 +---
Make i915_gem_vm_lookup() function non-static as it will be
used by the vm_bind feature.
Reviewed-by: Matthew Auld
Signed-off-by: Niranjana Vishwanathapura
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 11 ++-
drivers/gpu/drm/i915/gem/i915_gem_context.h |
Add getparam support for VM_BIND capability version.
Add VM creation time flag to enable vm_bind_mode for the VM.
v2: update kernel-doc
v3: create vm->root_obj only upon I915_VM_CREATE_FLAGS_USE_VM_BIND
v4: replace vm->vm_bind_mode check with i915_gem_vm_is_vm_bind_mode()
Reviewed-by: Matthew Aul
Expose i915_gem_object_max_page_size() function non-static
which will be used by the vm_bind feature.
Reviewed-by: Matthew Auld
Signed-off-by: Niranjana Vishwanathapura
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gem/i915_gem_create.c | 18 +-
drivers/gpu/drm/i915/gem/i9
Add support for handling out fence for vm_bind call.
v2: Reset vma->vm_bind_fence.syncobj to NULL at the end
of vm_bind call.
v3: Remove vm_unbind out fence uapi which is not supported yet.
v4: Return error if I915_TIMELINE_FENCE_WAIT fence flag is set.
Wait for bind to complete iff I915_T
Handle persistent (VM_BIND) mappings during the request submission
in the execbuf3 path.
v2: Ensure requests wait for bindings to complete.
v3: Remove short term pinning with PIN_VALIDATE flag.
Individualize fences before adding to dma_resv obj.
v4: Fix bind completion check, use PIN_NOEVICT,
Implement new execbuf3 ioctl (I915_GEM_EXECBUFFER3) which only
works in vm_bind mode. The vm_bind mode only works with
this new execbuf3 ioctl.
The new execbuf3 ioctl will not have any list of objects to validate
bind as all required objects binding would have been requested by the
userspace befor
Support dump capture of persistent mappings upon user request.
Signed-off-by: Brian Welty
Signed-off-by: Niranjana Vishwanathapura
---
.../drm/i915/gem/i915_gem_vm_bind_object.c| 11 +++
drivers/gpu/drm/i915/gt/intel_gtt.c | 3 +++
drivers/gpu/drm/i915/gt/intel_gtt.h
Update the execbuf path to use common execbuf functions to
reduce code duplication with the newer execbuf3 path.
Reviewed-by: Matthew Auld
Signed-off-by: Niranjana Vishwanathapura
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 513 ++
1 file changed, 39 insertions(+), 474 d
Update i915 documentation to include VM_BIND changes
and render all VM_BIND related documentation.
Reviewed-by: Matthew Auld
Signed-off-by: Niranjana Vishwanathapura
---
Documentation/gpu/i915.rst | 78 --
1 file changed, 59 insertions(+), 19 deletions(-)
di
Add uapi and implement support for bind and unbind of an
object at the specified GPU virtual addresses.
The vm_bind mode is not supported in legacy execbuf2 ioctl.
It will be supported only in the newer execbuf3 ioctl.
v2: On older platforms ctx->vm is not set, check for it.
In vm_bind call,
1 - 100 of 112 matches
Mail list logo
