Am 22.11.22 um 08:51 schrieb Somalapuram Amaranath:
Remove page shift operations as ttm_resource moved
from num_pages to size_t size in bytes.
v1 -> v2: fix missing page shift to fpfn and lpfn
Signed-off-by: Somalapuram Amaranath
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 4 +---
driv
On 22/11/2022 05:11, Zhenyu Wang wrote:
ping for this fix pull...
I missed it sorry, pulled now. Will go out this week.
Regards,
Tvrtko
On 2022.11.11 17:02:08 +0800, Zhenyu Wang wrote:
Hi,
Here's two fixes from Sean for 6.1 kernel, which is to fix kvm
reference in gvt. No regression fo
== Series Details ==
Series: drm/i915/mtl: Media GT and Render GT share common GGTT (rev5)
URL : https://patchwork.freedesktop.org/series/110321/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12413 -> Patchwork_110321v5
Sum
On 21/11/2022 18:21, John Harrison wrote:
On 11/18/2022 02:52, Jani Nikula wrote:
On Thu, 17 Nov 2022, john.c.harri...@intel.com wrote:
From: John Harrison
When trying to analyse bug reports from CI, customers, etc. it can be
difficult to work out exactly what is happening on which GT in a
Hi Andrzej,
On 2022-11-15 at 08:28:34 +0100, Andrzej Hajda wrote:
> test_plane_panning requires about 10 times bigger amount of memory than
> memory required by framebuffer in default display mode. In case of some
> configurations it can exceed available memory (4k modes on small-bar
> systems), c
On Mon, 21 Nov 2022, Daniele Ceraolo Spurio
wrote:
> On MTL the GSC FW needs to be loaded on the media GT by the graphics
> driver. We're going to treat it like a new uc_fw, so add the initial
> defs and init/fini functions for it.
>
> Similarly to the other FWs, the GSC FW path can be overriden
== Series Details ==
Series: drm/i915/mtl: Media GT and Render GT share common GGTT (rev5)
URL : https://patchwork.freedesktop.org/series/110321/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12413_full -> Patchwork_110321v5_full
===
On Mon, 2022-11-21 at 13:50 +0200, Luca Coelho wrote:
> From: Animesh Manna
>
> As part of die area reduction max input source modified to 4096
> for MTL so modified range check logic of scaler.
>
> Signed-off-by: José Roberto de Souza
> Signed-off-by: Animesh Manna
> Reviewed-by: Manasi Navar
In newer hardware versions (i.e. display version >= 14), the second
scaler doesn't support vertical scaling.
The current implementation of the scaling limits is simplified and
only occurs when the planes are created, so we don't know which scaler
is being used.
In order to handle separate scaling
From: Animesh Manna
As part of die area reduction max input source modified to 4096
for MTL so modified range check logic of scaler.
Signed-off-by: Jos� Roberto de Souza
Signed-off-by: Animesh Manna
Signed-off-by: Luca Coelho
---
In v2:
* No changes;
In v3:
* Removed stray reviewed-by
On Thu, Nov 10, 2022 at 02:23:53PM -0800, Navare, Manasi wrote:
> On Thu, Nov 03, 2022 at 03:23:00PM +0200, Stanislav Lisovskiy wrote:
> > Fix intel_dp_dsc_compute_config, previously timeslots parameter
> > was used in fact not as a timeslots, but more like a ratio
> > timeslots/64, which of course
On 21/11/2022 23:19, Janusz Krzysztofik wrote:
Hi Andrzej,
Thanks for providing your R-b.
On Monday, 21 November 2022 18:40:51 CET Andrzej Hajda wrote:
On 21.11.2022 15:56, Janusz Krzysztofik wrote:
Commit b97060a99b01 ("drm/i915/guc: Update intel_gt_wait_for_idle to work
with GuC") extende
>
>
> On 21/11/2022 09:35, Winkler, Tomas wrote:
> >>
> >> From: José Roberto de Souza
> >>
> >> For multi-tile setups the GSC operational only on the tile 0.
> >> Skip GSC auxiliary device creation for all other tiles in GSC device init
> >> code.
> >> Initialize basic GSC fields and use the s
On 21/11/2022 14:56, Janusz Krzysztofik wrote:
Users of intel_gt_retire_requests_timeout() expect 0 return value on
success. However, we have no protection from passing back 0 potentially
returned by a call to dma_fence_wait_timeout() when it succedes right
after its timeout has expired.
Is
On Mon, 21 Nov 2022, Vinod Govindapillai wrote:
> Enable the SDP split configuration for DP2.0.
>
> v2: Move the register handling out of compute config function (JaniN)
>
> v3: Patch styling and register access based on platform support (JaniN)
>
> v4: Rebased
>
> v5: Use unconditional clear bit
On Mon, Nov 21, 2022 at 02:48:55PM +0530, Arun R Murthy wrote:
> The WaFbcTurnOffFbcWhenHyperVisorIsUsed is applicable for all GEN9
> platforms as per BspecID: 0852
No. It says it was broken on kbl/cnl A-step.
>
> Signed-off-by: Arun R Murthy
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c |
On Thu, 17 Nov 2022, "Teres Alexis, Alan Previn"
wrote:
> Respectfully and humbly, i would like to request where is the coding
> guideline for function naming when u have 2nd level subsystem IPs
> owning control over global hw features so that we dont need to have
> this back and forth of conflic
From: Ville Syrjälä
Decided to do a bit more work on the DVO code. Started
with just some register definition cleanups/modernization
but ended up actually fixing suspend/resume for a two
of my ADD cards.
Ville Syrjälä (10):
drm/i915/dvo/ch7xxx: Fix suspend/resume
drm/i915/dvo/sil164: Nuke po
From: Ville Syrjälä
Poke a few more bits into the ch7xxx to make
it output a picture after being reset during S3.
In particular we need to set the input buffer select (IBS),
and enable VGA vsync output on the BCO pin. Selecting
VGA hsync on the c/h sync pin doesn't actually seem necessary
on my
From: Ville Syrjälä
Drop the pointless return statements at the end of void
functions.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/dvo_sil164.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/dvo_sil164.c
b/drivers/gpu/drm/i915/display/dvo_s
From: Ville Syrjälä
Poke a few more bits into the SiI164 to make it
recover after S3. HEN/VEN are the important bits,
the rest PLL filter/HPD detection I just did
for good measure to match the BIOS programming.
Note that the spec recommended SCNT bit in REGC
isn't set by the BIOS at least for me
From: Ville Syrjälä
Replace the hand rolled RMW with intel_de_rmw() in the DVO
port enable/disable functions. Also switch to intel_de_posting_read()
for the posting read (though maybe it should be just be nuked...).
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dvo.c | 11
From: Ville Syrjälä
We have two sets of bits for DVO "data order" stuff. Rename
one set to ACT_DATA_ORDER to make it clear they are separate
bitfields.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dvo.c | 4 ++--
drivers/gpu/drm/i915/i915_reg.h | 8
2 f
From: Ville Syrjälä
Pull the DVO port register definitons into their own header
to declutter i915_reg.h a bit.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dvo.c | 1 +
drivers/gpu/drm/i915/display/intel_dvo_regs.h | 54 +++
drivers/gpu/drm/i915/i91
From: Ville Syrjälä
Get rid of the dvo_reg/dvo_srcdim_reg stuff by parametrizing
the DVO port registers.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dvo.c | 73
drivers/gpu/drm/i915/display/intel_dvo_dev.h | 7 +-
drivers/gpu/drm/i915/i915_reg.
From: Ville Syrjälä
Define a few extra interrupt related bits on the DVO register.
One of these we included in the DVO_PRESERVE_MASK already.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dvo.c | 3 ++-
drivers/gpu/drm/i915/i915_reg.h | 4 +++-
2 files changed, 5
From: Ville Syrjälä
Polish the DVO port regisesters with REG_BIT()/etc.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dvo.c | 7 +--
drivers/gpu/drm/i915/i915_reg.h | 63 +---
2 files changed, 37 insertions(+), 33 deletions(-)
diff --git a/d
From: Ville Syrjälä
Currently it's not 100% obvious which DVO encoder chip was
found on which port. Leave a slightly better trace in log.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dvo.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/displ
If phy is PHY_NONE, the shift to register bits becomes negative. Check
and warn about this.
Reported-by: coverity-bot
References: https://lore.kernel.org/r/202211180848.D39006C@keescook
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_hti.c | 3 +++
1 file changed, 3 insertions
Release notes:
1. Fixes for Register noclaims and few restore.
Signed-off-by: Gustavo Sousa
---
v2:
- Use correct numbering for the minor version (8 instead of the
invalid octal 08).
drivers/gpu/drm/i915/display/intel_dmc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
On Tue, 22 Nov 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Poke a few more bits into the ch7xxx to make
> it output a picture after being reset during S3.
>
> In particular we need to set the input buffer select (IBS),
> and enable VGA vsync output on the BCO pin. Selecting
> VGA hsync o
On Tue, 22 Nov 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Drop the pointless return statements at the end of void
> functions.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/dvo_sil164.c | 2 --
> 1 file changed, 2 deletions(-)
>
> di
On Tue, 22 Nov 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Poke a few more bits into the SiI164 to make it
> recover after S3. HEN/VEN are the important bits,
> the rest PLL filter/HPD detection I just did
> for good measure to match the BIOS programming.
>
> Note that the spec recommend
On Tue, 22 Nov 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Get rid of the dvo_reg/dvo_srcdim_reg stuff by parametrizing
> the DVO port registers.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_dvo.c | 73
On Tue, 22 Nov 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Define a few extra interrupt related bits on the DVO register.
> One of these we included in the DVO_PRESERVE_MASK already.
>
> Signed-off-by: Ville Syrjälä
Acked-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_dv
On Tue, 22 Nov 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We have two sets of bits for DVO "data order" stuff. Rename
> one set to ACT_DATA_ORDER to make it clear they are separate
> bitfields.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/d
== Series Details ==
Series: Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes (rev6)
URL : https://patchwork.freedesktop.org/series/107550/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12415 -> Patchwork_107550v6
On Tue, 22 Nov 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Polish the DVO port regisesters with REG_BIT()/etc.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_dvo.c | 7 +--
> drivers/gpu/drm/i915/i915_reg.h | 63 +++
On Tue, 22 Nov 2022, Jani Nikula wrote:
> On Tue, 22 Nov 2022, Ville Syrjala wrote:
>> From: Ville Syrjälä
>>
>> Polish the DVO port regisesters with REG_BIT()/etc.
*registers
>>
>> Signed-off-by: Ville Syrjälä
>
> Reviewed-by: Jani Nikula
--
Jani Nikula, Intel Open Source Graphics Center
On Tue, 22 Nov 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Replace the hand rolled RMW with intel_de_rmw() in the DVO
> port enable/disable functions. Also switch to intel_de_posting_read()
> for the posting read (though maybe it should be just be nuked...).
>
> Signed-off-by: Ville Syrj
On Tue, 22 Nov 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Pull the DVO port register definitons into their own header
> to declutter i915_reg.h a bit.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_dvo.c | 1 +
> drivers/g
On Tue, 22 Nov 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Currently it's not 100% obvious which DVO encoder chip was
> found on which port. Leave a slightly better trace in log.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_dvo
On Fri, 18 Nov 2022, coverity-bot wrote:
> Hello!
>
> This is an experimental semi-automated report about issues detected by
> Coverity from a scan of next-20221118 as part of the linux-next scan project:
> https://scan.coverity.com/projects/linux-next-weekly-scan
>
> You're getting this email bec
== Series Details ==
Series: drm/ttm: Clean up page shift operation
URL : https://patchwork.freedesktop.org/series/81/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12415 -> Patchwork_81v1
Summary
---
**SUCCE
Introduce stricter rules for topic/core-for-CI management. Way too many
commits have been added over the years, with insufficient rationale
recorded in the commit message, and insufficient follow-up with removing
the commits from the topic branch.
New rules:
1. Require maintainer ack for rebase.
On Mon, 2022-11-21 at 14:31 +, Patchwork wrote:
Patch Details
Series: drm/i915/gsc: Only initialize GSC in tile 0 (rev2)
URL:https://patchwork.freedesktop.org/series/110304/
State: failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110304v2/index.html
CI Bug Log -
On Tue, 06 Sep 2022, Daniele Ceraolo Spurio
wrote:
> From: John Harrison
>
> There was a misunderstanding in how firmware file compatibility should
> be managed within i915. This has been clarified as:
> i915 must support all existing firmware releases forever
> new minor firmware releases s
The default_lists array should be in rodata.
Fixes: dce2bd542337 ("drm/i915/guc: Add Gen9 registers for GuC error state
capture.")
Cc: Alan Previn
Cc: Umesh Nerlige Ramappa
Cc: Lucas De Marchi
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c | 2 +-
1 file change
On Tue, Nov 22, 2022 at 03:17:14PM +0200, Jani Nikula wrote:
> Introduce stricter rules for topic/core-for-CI management. Way too many
> commits have been added over the years, with insufficient rationale
> recorded in the commit message, and insufficient follow-up with removing
> the commits from
On Mon, Nov 14, 2022 at 04:15:35PM -0300, Fabio Estevam wrote:
> On Mon, Nov 14, 2022 at 1:22 PM Andy Shevchenko
> wrote:
> >
> > The list API now provides the list_count() to help with counting
> > existing nodes in the list. Uilise it.
>
> s/Uilise/Utilise
Fixed for v3, thanks!
--
With Best
On Tue, Nov 15, 2022 at 05:46:28PM +0200, Jani Nikula wrote:
> On Mon, 14 Nov 2022, Andy Shevchenko
> wrote:
> > Some of the existing users, and definitely will be new ones, want to
> > count existing nodes in the list. Provide a generic API for that by
> > moving code from i915 to list.h.
>
> I
Some of the existing users, and definitely will be new ones, want to
count existing nodes in the list. Provide a generic API for that by
moving code from i915 to list.h.
Signed-off-by: Andy Shevchenko
Acked-by: Jani Nikula
---
v3: added tag (Jani), changed to be static inline (Mike)
v2: dropped
The list API now provides the list_count() to help with counting
existing nodes in the list. Utilise it.
Signed-off-by: Andy Shevchenko
---
v3: no change
v2: no change
drivers/usb/gadget/udc/bcm63xx_udc.c | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers/usb
The list API now provides the list_count() to help with counting
existing nodes in the list. Utilise it.
Signed-off-by: Andy Shevchenko
---
v3: no change
v2: no change
drivers/usb/host/xhci-ring.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/usb/host/xhci-ri
The list API now provides the list_count() to help with counting
existing nodes in the list. Utilise it.
Signed-off-by: Andy Shevchenko
---
v3: fixed typo in the commit message (Fabio)
v2: no change
drivers/usb/gadget/legacy/hid.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
dif
On Tue, Nov 22, 2022 at 05:35:13PM +0200, Andy Shevchenko wrote:
> Some of the existing users, and definitely will be new ones, want to
> count existing nodes in the list. Provide a generic API for that by
> moving code from i915 to list.h.
Sorry for the noise, forgot to squash one part, so it get
== Series Details ==
Series: drm/i915/dvo: Further DVO fixes/cleanups
URL : https://patchwork.freedesktop.org/series/91/
State : warning
== Summary ==
Error: dim checkpatch failed
dcb99cb1b0fc drm/i915/dvo/ch7xxx: Fix suspend/resume
-:31: CHECK:SPACING: spaces preferred around that '<<' (c
== Series Details ==
Series: drm/i915/dvo: Further DVO fixes/cleanups
URL : https://patchwork.freedesktop.org/series/91/
State : warning
== Summary ==
Error: make htmldocs had i915 warnings
./drivers/gpu/drm/i915/gt/intel_gt_mcr.c:739: warning: expecting prototype for
intel_gt_mcr_wait_fo
== Series Details ==
Series: drm/i915/dvo: Further DVO fixes/cleanups
URL : https://patchwork.freedesktop.org/series/91/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12417 -> Patchwork_91v1
Summary
---
**SUC
On 18.11.2022 11:52, Jani Nikula wrote:
> On Thu, 17 Nov 2022, john.c.harri...@intel.com wrote:
>> From: John Harrison
>>
>> When trying to analyse bug reports from CI, customers, etc. it can be
>> difficult to work out exactly what is happening on which GT in a
>> multi-GT system. So add GT or
On 18.11.2022 02:58, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> When trying to analyse bug reports from CI, customers, etc. it can be
> difficult to work out exactly what is happening on which GT in a
> multi-GT system. So add GT oriented debug/error message wrappers. If
> used
tldr; DMA buffers aren't normal memory, expecting that you can use
them like that (like calling get_user_pages works, or that they're
accounting like any other normal memory) cannot be guaranteed.
Since some userspace only runs on integrated devices, where all
buffers are actually all resident sys
On 18.11.2022 02:58, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> Create a set of HuC printers and start using them.
>
> Signed-off-by: John Harrison
> ---
> drivers/gpu/drm/i915/gt/uc/intel_huc.c | 31 ++
> drivers/gpu/drm/i915/gt/uc/intel_huc.h | 23 +
> -Original Message-
> From: Intel-gfx On Behalf Of
> Gustavo Sousa
> Sent: Tuesday, November 22, 2022 4:14 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2] drm/i915/dmc: Update DG2 DMC version to
> v2.08
>
> Release notes:
>
> 1. Fixes for Register noclaims
On Tue, Nov 22, 2022 at 04:16:16PM +0200, Jani Nikula wrote:
The default_lists array should be in rodata.
Fixes: dce2bd542337 ("drm/i915/guc: Add Gen9 registers for GuC error state
capture.")
Cc: Alan Previn
Cc: Umesh Nerlige Ramappa
Cc: Lucas De Marchi
Signed-off-by: Jani Nikula
Reviewe
On 18.11.2022 02:58, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> Create a set of GuC printers and start using them.
>
> Signed-off-by: John Harrison
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc.c| 32 --
> drivers/gpu/drm/i915/gt/uc/intel_guc.h| 35 +++
== Series Details ==
Series: Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes (rev6)
URL : https://patchwork.freedesktop.org/series/107550/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12415_full -> Patchwork_107550v6_full
==
We should still be able to GTT evict objects during execbuf (old
bindings can linger around), even if there is object lock contention. In
the worst case the execbuf should just wait on the contented locks.
Returning -ENOSPC smells like a regression from past behaviour, and
seems to break userspace.
On Tue, Nov 22, 2022 at 03:59:10PM +0100, Daniel Vetter wrote:
> On Tue, Nov 22, 2022 at 03:17:14PM +0200, Jani Nikula wrote:
> > Introduce stricter rules for topic/core-for-CI management. Way too many
> > commits have been added over the years, with insufficient rationale
> > recorded in the commi
== Series Details ==
Series: drm/i915/hti: avoid theoretically possible negative shift
URL : https://patchwork.freedesktop.org/series/92/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12418 -> Patchwork_92v1
Summary
On 18.11.2022 02:58, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> Re-work the existing GuC CT printers and extend as required to match
> the new wrapping scheme.
>
> Signed-off-by: John Harrison
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 222 +++---
>
On Mon, Nov 21, 2022 at 05:51:36PM +, Teres Alexis, Alan Previn wrote:
>
>
> On Mon, 2022-11-21 at 14:06 +, Vivi, Rodrigo wrote:
> > On Mon, 2022-11-21 at 11:39 +, Tvrtko Ursulin wrote:
> > >
> > > On 17/11/2022 22:34, Teres Alexis, Alan Previn wrote:
> > > > On Thu, 2022-11-17 at 11
Hi, Anusha.
On Tue, Nov 22, 2022 at 02:27:05PM -0300, Srivatsa, Anusha wrote:
>
>
> > -Original Message-
> > From: Intel-gfx On Behalf Of
> > Gustavo Sousa
> > Sent: Tuesday, November 22, 2022 4:14 AM
> > To: intel-gfx@lists.freedesktop.org
> > Subject: [Intel-gfx] [PATCH v2] drm/i915/d
On Tue, 22 Nov 2022 at 19:04, Jason Gunthorpe wrote:
>
> On Tue, Nov 22, 2022 at 06:08:00PM +0100, Daniel Vetter wrote:
> > tldr; DMA buffers aren't normal memory, expecting that you can use
> > them like that (like calling get_user_pages works, or that they're
> > accounting like any other normal
Hi Andy,
I love your patch! Yet something to improve:
[auto build test ERROR on usb/usb-testing]
[also build test ERROR on usb/usb-next usb/usb-linus drm-intel/for-linux-next
drm-intel/for-linux-next-fixes linus/master v6.1-rc6 next-20221122]
[If your patch is applied to the wrong git tree
Thanks, looked at the rest of the platforms in the file and the changes look
good.
Reviewed-by: Anusha Srivatsa
> -Original Message-
> From: Sousa, Gustavo
> Sent: Tuesday, November 22, 2022 10:06 AM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-g
On Tue, 22 Nov 2022, Michal Wajdeczko wrote:
> On 18.11.2022 11:52, Jani Nikula wrote:
>> On Thu, 17 Nov 2022, john.c.harri...@intel.com wrote:
>>> From: John Harrison
>>>
>>> When trying to analyse bug reports from CI, customers, etc. it can be
>>> difficult to work out exactly what is happening
From: Xu Panda
Replace the open-code with sysfs_streq().
Signed-off-by: Xu Panda
Signed-off-by: Yang Yang
---
drivers/gpu/drm/i915/gvt/cmd_parser.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c
b/drivers/gpu/drm/i915/
On 11/16/2022 2:50 PM, Arunpravin Paneer Selvam wrote:
Hi Amar,
On 11/16/2022 2:20 PM, Somalapuram Amaranath wrote:
ttm_resource allocate size in bytes i.e less than page size.
Signed-off-by: Somalapuram Amaranath
---
drivers/gpu/drm/drm_gem.c | 2 +-
1 file changed, 1 insertion(+), 1 de
Wa_18019271663 applies to all DG2 steppings and skus.
Bspec: 66622
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 7 ---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/
Wa_18018764978 applies to specific steppings of DG2 (G10 C0+,
G11 and G12 A0+). Clean up style in function at the same time.
Bspec: 66622
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +++--
2 files change
Hi Andy,
I love your patch! Yet something to improve:
[auto build test ERROR on usb/usb-testing]
[also build test ERROR on usb/usb-next usb/usb-linus drm-intel/for-linux-next
drm-intel/for-linux-next-fixes linus/master v6.1-rc6 next-20221122]
[If your patch is applied to the wrong git tree
On Tue, 2022-11-22 at 12:57 -0500, Vivi, Rodrigo wrote:
>
>
[Alan:snip]
> As I had told I don't have a strong preference, as long as it keep clean
> and without these many helpers of something "on_gt"...
>
> If this stays inside the gt, just make sure that you call for all the gts,
> but then
On Mon, Nov 21, 2022 at 03:16:13PM -0800, Daniele Ceraolo Spurio wrote:
> The current exectation from the FW side is that the driver will query
> the GSC FW version after the FW is loaded, similarly to what the mei
> driver does on DG2. However, we're discussing with the FW team if there
> is a way
== Series Details ==
Series: docs: updated rules for topic/core-for-CI commit management
URL : https://patchwork.freedesktop.org/series/98/
State : failure
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/98/revisions/1/mbox/ not
applied
Applying: docs: upd
== Series Details ==
Series: drm/i915/dmc: Update DG2 DMC version to v2.08 (rev2)
URL : https://patchwork.freedesktop.org/series/64/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12418 -> Patchwork_64v2
Summary
Hi,
This series adds guards around vma's but setting a pages at the
beginning and at the end that work as padding.
The first user of the vma guard are scanout objects which don't
need anymore to add scratch to all the unused ggtt's and speeding
up up considerably the boot and resume by several hu
From: Chris Wilson
We already wrap i915_vma.node.start for use with the GGTT, as there we
can perform additional sanity checks that the node belongs to the GGTT
and fits within the 32b registers. In the next couple of patches, we
will introduce guard pages around the objects _inside_ the drm_mm_n
From: Chris Wilson
Introduce the concept of padding the i915_vma with guard pages before
and after. The major consequence is that all ordinary uses of i915_vma
must use i915_vma_offset/i915_vma_size and not i915_vma.node.start/size
directly, as the drm_mm_node will include the guard pages that su
From: Chris Wilson
VT-d may cause overfetch of the scanout PTE, both before and after the
vma (depending on the scanout orientation). bspec recommends that we
provide a tile-row in either directions, and suggests using 168 PTE,
warning that the accesses will wrap around the ends of the GGTT.
Curr
This reverts commit 2ef6efa79fecd5e3457b324155d35524d95f2b6b.
Checking the presence if the IRST (Intel Rapid Start Technology)
through the ACPI to decide whether to rebuild or not the GGTT
puts us at the mercy of the boot firmware and we need to
unnecessarily rely on third parties.
Because now we
On Mon, Nov 21, 2022 at 03:16:14PM -0800, Daniele Ceraolo Spurio wrote:
> GSC FW is loaded by submitting a dedicated command via the GSC engine.
> The memory area used for loading the FW is then re-purposed as local
> memory for the GSC itself, so we use a separate allocation instead of
> using the
== Series Details ==
Series: drm/ttm: Clean up page shift operation
URL : https://patchwork.freedesktop.org/series/81/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12415_full -> Patchwork_81v1_full
Summary
---
== Series Details ==
Series: drm/i915/guc: make default_lists const data
URL : https://patchwork.freedesktop.org/series/111201/
State : warning
== Summary ==
Error: make htmldocs had i915 warnings
./drivers/gpu/drm/i915/gt/intel_gt_mcr.c:739: warning: expecting prototype for
intel_gt_mcr_wait
== Series Details ==
Series: series starting with [v3,1/4] i915: Move list_count() to list.h for
broader use
URL : https://patchwork.freedesktop.org/series/111206/
State : failure
== Summary ==
Error: make failed
CALLscripts/checksyscalls.sh
DESCEND objtool
VDSOarch/x86/entry/vd
On Tue, 22 Nov 2022 at 19:50, Jason Gunthorpe wrote:
>
> On Tue, Nov 22, 2022 at 07:08:25PM +0100, Daniel Vetter wrote:
> > On Tue, 22 Nov 2022 at 19:04, Jason Gunthorpe wrote:
> > >
> > > On Tue, Nov 22, 2022 at 06:08:00PM +0100, Daniel Vetter wrote:
> > > > tldr; DMA buffers aren't normal memor
== Series Details ==
Series: drm/i915/guc: make default_lists const data
URL : https://patchwork.freedesktop.org/series/111201/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12418 -> Patchwork_111201v1
Summary
---
**
On 11/22/2022 11:01 AM, Rodrigo Vivi wrote:
On Mon, Nov 21, 2022 at 03:16:14PM -0800, Daniele Ceraolo Spurio wrote:
GSC FW is loaded by submitting a dedicated command via the GSC engine.
The memory area used for loading the FW is then re-purposed as local
memory for the GSC itself, so we use
On 11/22/2022 1:03 AM, Jani Nikula wrote:
On Mon, 21 Nov 2022, Daniele Ceraolo Spurio
wrote:
On MTL the GSC FW needs to be loaded on the media GT by the graphics
driver. We're going to treat it like a new uc_fw, so add the initial
defs and init/fini functions for it.
Similarly to the other
== Series Details ==
Series: dma-buf: Require VM_PFNMAP vma for mmap
URL : https://patchwork.freedesktop.org/series/111210/
State : warning
== Summary ==
Error: dim checkpatch failed
354674e79934 dma-buf: Require VM_PFNMAP vma for mmap
-:15: WARNING:TYPO_SPELLING: 'useable' may be misspelled -
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