Do not use i915_vma activeness tracking for persistent vmas.
As persistent vmas are part of working set for each execbuf
submission on that address space (VM), a persistent vma is
active if the VM active. As vm->root_obj->base.resv will be
updated for each submission on that VM, it correctly
repre
Implement new execbuf3 ioctl (I915_GEM_EXECBUFFER3) which only
works in vm_bind mode. The vm_bind mode only works with
this new execbuf3 ioctl.
The new execbuf3 ioctl will not have any list of objects to validate
bind as all required objects binding would have been requested by the
userspace befor
Each VM creates a root_obj and shares it with all of its private objects
to use it as dma_resv object. This has a performance advantage as it
requires a single dma_resv object update for all private BOs vs list of
dma_resv objects update for shared BOs, in the execbuf path.
VM private BOs can be o
Add uapi and implement support for bind and unbind of an
object at the specified GPU virtual addresses.
The vm_bind mode is not supported in legacy execbuf2 ioctl.
It will be supported only in the newer execbuf3 ioctl.
v2: On older platforms ctx->vm is not set, check for it.
In vm_bind call,
Ensure i915_vma_verify_bind_complete() handles case where bind
is not initiated. Also make it non static, add documentation
and move it out of CONFIG_DRM_I915_DEBUG_GEM.
Signed-off-by: Niranjana Vishwanathapura
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/i915_vma.c | 16 +++-
The new execbuf3 ioctl path and the legacy execbuf ioctl
paths have many common functionalities.
Abstract out the common execbuf functionalities into a
separate file where possible, thus allowing code sharing.
Reviewed-by: Andi Shyti
Acked-by: Matthew Auld
Signed-off-by: Niranjana Vishwanathapur
Rename __i915_request_await_bind() as i915_request_await_bind()
and make it non-static as it will be used in execbuf3 ioctl path.
Reviewed-by: Andi Shyti
Signed-off-by: Niranjana Vishwanathapura
---
drivers/gpu/drm/i915/i915_vma.c | 8 +---
drivers/gpu/drm/i915/i915_vma.h | 6 ++
2 file
Update the execbuf path to use common execbuf functions to
reduce code duplication with the newer execbuf3 path.
Acked-by: Matthew Auld
Signed-off-by: Niranjana Vishwanathapura
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 507 ++
1 file changed, 38 insertions(+), 469 dele
Support eviction by maintaining a list of evicted persistent vmas
for rebinding during next submission. Ensure the list do not
include persistent vmas that are being purged.
v2: Remove unused I915_VMA_PURGED definition.
v3: Properly handle __i915_vma_unbind_async() case.
Acked-by: Matthew Auld
S
Handle persistent (VM_BIND) mappings during the request submission
in the execbuf3 path.
v2: Ensure requests wait for bindings to complete.
v3: Remove short term pinning with PIN_VALIDATE flag.
Individualize fences before adding to dma_resv obj.
Signed-off-by: Niranjana Vishwanathapura
Signe
Add getparam support for VM_BIND capability version.
Add VM creation time flag to enable vm_bind_mode for the VM.
v2: update kernel-doc
v3: create vm->root_obj only upon I915_VM_CREATE_FLAGS_USE_VM_BIND
Acked-by: Matthew Auld
Signed-off-by: Niranjana Vishwanathapura
Signed-off-by: Andi Shyti
-
Add i915_vma_instance_persistent() to create persistent vmas.
Persistent vmas will use i915_gtt_view to support partial binding.
vma_lookup is tied to segment of the object instead of section
of VA space. Hence, it do not support aliasing. ie., multiple
mappings (at different VA) point to the same
For persistent (vm_bind) vmas of userptr BOs, handle the user
page pinning by using the i915_gem_object_userptr_submit_init()
/done() functions
v2: Do not double add vma to vm->userptr_invalidated_list
Signed-off-by: Niranjana Vishwanathapura
Signed-off-by: Andi Shyti
---
.../gpu/drm/i915/gem/
Add support for handling out fence for vm_bind call.
v2: Reset vma->vm_bind_fence.syncobj to NULL at the end
of vm_bind call.
Signed-off-by: Niranjana Vishwanathapura
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h | 4 +
.../drm/i915/gem/i915_gem_vm_bind_objec
On 05.10.2022 14:11, Thomas Hellström wrote:
Commit 39a2bd34c933 ("drm/i915: Use the vma resource as argument for gtt
binding / unbinding") introduced a regression that due to the vma resource
tracking of the binding state, dpt ptes were not correctly repopulated.
Fix this by clearing the vma res
== Series Details ==
Series: drm/i915/vm_bind: Add VM_BIND functionality (rev6)
URL : https://patchwork.freedesktop.org/series/105879/
State : warning
== Summary ==
Error: dim checkpatch failed
95d7e27b6d51 drm/i915/vm_bind: Expose vm lookup function
630f95af9f30 drm/i915/vm_bind: Add __i915_s
== Series Details ==
Series: drm/i915/vm_bind: Add VM_BIND functionality (rev6)
URL : https://patchwork.freedesktop.org/series/105879/
State : warning
== Summary ==
Error: make htmldocs had i915 warnings
./include/uapi/drm/i915_drm.h:2666: warning: Function parameter or member
'flags' not des
== Series Details ==
Series: drm/i915/vm_bind: Add VM_BIND functionality (rev6)
URL : https://patchwork.freedesktop.org/series/105879/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
Ville,
Gentle reminder!
Thanks and Regards,
Arun R Murthy
> -Original Message-
> From: Murthy, Arun R
> Sent: Monday, September 19, 2022 10:38 AM
> To: 'intel-gfx@lists.freedesktop.org'
> Cc: Syrjala, Ville
> Subject: RE: [PATCHv3] drm/i915: Support Async Fl
== Series Details ==
Series: drm/i915: Fix simulated GPU reset wrt. encoder HW readout
URL : https://patchwork.freedesktop.org/series/109480/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12225_full -> Patchwork_109480v1_full
===
On 07/10/2022 20:47, Colin Ian King wrote:
The variable ret is being assigned with a value that is never read
both before and after a while-loop. The variable is being re-assigned
inside the while-loop and afterwards on the call to the function
i915_gem_object_lock_interruptible. Remove the red
== Series Details ==
Series: drm/i915/vm_bind: Add VM_BIND functionality (rev6)
URL : https://patchwork.freedesktop.org/series/105879/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12227 -> Patchwork_105879v6
Summary
--
On 08/10/2022 12:55, Christophe JAILLET wrote:
Le 07/10/2022 à 21:53, Colin Ian King a écrit :
The assignment to variable taken is redundant and so it can be
removed as well as the variable too.
Cleans up clang-scan build warnings:
warning: Although the value stored to 'taken' is used in the
As some faulty displays generate long HPDs even while connected to ports
can cause CI execution issues. Add a provision to ignore such long HPDs
in such systems with control through debugfs
Vinod Govindapillai (2):
drm/i915/display: ignore long HPDs based on a flag
drm/i915/display: debugfs en
Some panels generate long HPD events even while connected to
the port. This cause some unexpected CI execution issues. A
new flag is added to track if such spurious long HPDs can be
ignored and are not processed further if the flag is set.
v2: Address patch styling comments (Jani Nikula)
Signed-o
Knob to control ignoring the long hpds. Set this to true will
start ignoring the long HPDs generated by the displays. Useful
for use cases like CI systems where we dont expect to disconnect
the panels.
v2: Address patch styling comments (Jani Nikula)
Signed-off-by: Vinod Govindapillai
---
drive
== Series Details ==
Series: Provision to ignore long HPDs in CI systems (rev2)
URL : https://patchwork.freedesktop.org/series/109475/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
When tried locally, dim sparse were ok!
---
Sparse version: 0.6.4 (Ubuntu: 0.6.4-2)
Commit: drm/i915/display: ignore long HPDs based on a flag
Okay!
Commit: drm/i915/display: debugfs entry to control ignore long hpd flag
Okay!
---
BR
vinod
On Mon, 2022-10-10 at 08:52 +, Patchwork wrote:
== Series Details ==
Series: Provision to ignore long HPDs in CI systems (rev2)
URL : https://patchwork.freedesktop.org/series/109475/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12227 -> Patchwork_109475v2
Summary
--
== Series Details ==
Series: drm/i915/vm_bind: Add VM_BIND functionality (rev6)
URL : https://patchwork.freedesktop.org/series/105879/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12227_full -> Patchwork_105879v6_full
Summ
DG1, as expected only has a fixed sized bar, so attempting to force the
BAR size should fail. Update the test to account for such devices, and
perform a skip, instead of failing.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6458
Signed-off-by: Matthew Auld
Cc: Nirmoy Das
---
tests/
On 10/10/2022 12:48 PM, Matthew Auld wrote:
DG1, as expected only has a fixed sized bar, so attempting to force the
BAR size should fail. Update the test to account for such devices, and
perform a skip, instead of failing.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6458
Signed-o
On Sat, 08 Oct 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Currently we do the DRIVER_ATOMIC disable as almost the
> first thing during pci probe. That involves the use of
> DISPLAY_VER() which is perhaps a bit sketchy now that we
> may need to read that out from the hardware itself.
> L
On Sat, 08 Oct 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The watermark code for ctg/elk has been atomic ready for a long time
> so let's just flip the switch now that some of the last CxSR issues
> have been sorted out (which granted was a problem for vlv/chv as well
> despite them alr
On 10.10.2022 10:34, Vinod Govindapillai wrote:
Some panels generate long HPD events even while connected to
the port. This cause some unexpected CI execution issues. A
new flag is added to track if such spurious long HPDs can be
ignored and are not processed further if the flag is set.
v2: Addr
On Thu, 29 Sep 2022 18:30:56 +0200, Maxime Ripard wrote:
> Since we've recently added a ton of tests, the list starts to be a bit
> of a mess and creates unneeded conflicts.
>
> Let's order it alphabetically.
>
>
Applied to drm/drm-misc (drm-misc-next).
Thanks!
Maxime
On 10.10.2022 10:34, Vinod Govindapillai wrote:
Knob to control ignoring the long hpds. Set this to true will
start ignoring the long HPDs generated by the displays. Useful
for use cases like CI systems where we dont expect to disconnect
the panels.
v2: Address patch styling comments (Jani Nikul
On Thu, 29 Sep 2022 18:30:58 +0200, Maxime Ripard wrote:
> We currently have two sets of TV properties.
>
> The first one is there to deal with analog TV properties, creating
> properties such as the TV mode, subconnectors, saturation, hue and so on.
> It's created by calling the drm_mode_create_t
On Thu, 29 Sep 2022 18:30:59 +0200, Maxime Ripard wrote:
> There is two TV subconnector related properties registered by
> drm_mode_create_tv_properties(): subconnector and select subconnector.
>
> While the select subconnector property is stored in the kernel by the
> drm_tv_connector_state struc
On Thu, 29 Sep 2022 18:31:00 +0200, Maxime Ripard wrote:
> The subconnector property was created by drm_mode_create_tv_properties(),
> but wasn't exposed to the userspace through the generic
> atomic_get/set_property implementation, and wasn't stored in any generic
> state structure.
>
> Let's sol
On Thu, 29 Sep 2022 18:31:06 +0200, Maxime Ripard wrote:
> Some video= options might have a value that contains a dash. However, the
> command line parsing mode considers all dashes as the separator between the
> mode and the bpp count.
>
> Let's rework the parsing code a bit to only consider a da
On Thu, 29 Sep 2022 18:31:07 +0200, Maxime Ripard wrote:
> From: Geert Uytterhoeven
>
> It is fairly common for named video modes to contain dashes (e.g.
> "tt-mid" on Atari, "dblntsc-ff" on Amiga). Currently such mode names
> are not recognized, as the dash is considered to be a separator betwe
On Mon, 2022-10-10 at 14:08 +0200, Andrzej Hajda wrote:
> On 10.10.2022 10:34, Vinod Govindapillai wrote:
> > Some panels generate long HPD events even while connected to
> > the port. This cause some unexpected CI execution issues. A
> > new flag is added to track if such spurious long HPDs can be
On Thu, 29 Sep 2022 18:31:19 +0200, Maxime Ripard wrote:
> From: Mateusz Kwiatkowski
>
> PAL-M is a Brazilian analog TV standard that uses a PAL-style chroma
> subcarrier at 3.575611[888111] MHz on top of 525-line (480i60) timings.
> This commit makes the driver actually use the proper VEC preset
On Sat, Oct 01, 2022 at 03:12:06PM +0200, Noralf Trønnes wrote:
>
>
> Den 29.09.2022 18.30, skrev Maxime Ripard:
> > Hi,
> >
> > Here's a series aiming at improving the command line named modes support,
> > and more importantly how we deal with all the analog TV variants.
> >
> > The named mode
== Series Details ==
Series: Provision to ignore long HPDs in CI systems (rev2)
URL : https://patchwork.freedesktop.org/series/109475/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12227_full -> Patchwork_109475v2_full
Summ
On 10/10/2022 07:58, Niranjana Vishwanathapura wrote:
Support eviction by maintaining a list of evicted persistent vmas
for rebinding during next submission. Ensure the list do not
include persistent vmas that are being purged.
v2: Remove unused I915_VMA_PURGED definition.
v3: Properly handle __
The last user of macros from that include was removed in 2018 by the
commit below.
Fixes: 6cc42152b02b ("drm/i915: Remove support for legacy debugfs crc
interface")
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Tvrtko Ursulin
Cc: David Airlie
Cc: Daniel Vetter
Cc: intel-gfx@lists
When DRM_I915=y and BACKLIGHT_CLASS_DEVICE=m, the build fails:
ld: drivers/gpu/drm/i915/display/intel_backlight.o: in function
`intel_backlight_device_register':
intel_backlight.c:(.text+0x5587): undefined reference to
`backlight_device_get_by_name'
ld: drivers/gpu/drm/i915/display/intel_backlig
Remove the redundant semicolon
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2333
Reported-by: Abaci Robot
Signed-off-by: Yang Li
---
drivers/gpu/drm/i915/gvt/vgpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915
Thorsten Leemhuis writes:> On 03.10.22 19:48, Ville Syrjälä wrote:>> On Mon, Oct 03, 2022 at 08:45:18PM +0300, Ville Syrjälä wrote:>>> On Sat, Oct 01, 2022 at 12:07:39PM +0200, Thorsten Leemhuis wrote: On 30.09.22 14:26, Jerry Ling wrote:>> looks like someone has done it:> https://
If intel_gvt_dma_map_guest_page failed, it will call
ppgtt_invalidate_spt, which will finally free the spt.
But the caller does not notice that, it will free spt again in error path.
Fix this by spliting invalidate and free in ppgtt_invalidate_spt.
Only free spt when in good case.
Reported-by: Zh
On 04. 10. 22, 12:52, Jani Nikula wrote:
On Tue, 04 Oct 2022, "Jiri Slaby (SUSE)" wrote:
When DRM_I915=y and BACKLIGHT_CLASS_DEVICE=m, the build fails:
ld: drivers/gpu/drm/i915/display/intel_backlight.o: in function
`intel_backlight_device_register':
intel_backlight.c:(.text+0x5587): undefined
If intel_gvt_dma_map_guest_page failed, it will call
ppgtt_invalidate_spt, which will finally free the spt.
But the caller does not notice that, it will free spt again in error path.
Fix this by spliting invalidate and free in ppgtt_invalidate_spt.
Only free spt when in good case.
Reported-by: Zh
On Thu, Oct 06, 2022 at 10:48:44PM +0200, Andrzej Hajda wrote:
> drm_device pointers are unwelcome.
>
> Signed-off-by: Andrzej Hajda
Acked-by: Andi Shyti
To me both versions were good...
Jani, Ville, could you please check on this patch?
Andi
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c
== Series Details ==
Series: drm/i915/gvt: remove unneeded semicolon
URL : https://patchwork.freedesktop.org/series/109543/
State : failure
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/109543/revisions/1/mbox/ not
applied
Applying: drm/i915/gvt: remove unneeded
== Series Details ==
Series: series starting with [1/2] drm/i915/display: fix randconfig build (rev2)
URL : https://patchwork.freedesktop.org/series/109542/
State : failure
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/109542/revisions/2/mbox/ not
applied
Applyi
== Series Details ==
Series: drm/i915/gvt: fix double-free bug in split_2MB_gtt_entry (rev5)
URL : https://patchwork.freedesktop.org/series/108732/
State : warning
== Summary ==
Error: dim checkpatch failed
179c557abab8 drm/i915/gvt: fix double free bug in split_2MB_gtt_entry
-:58: CHECK:PAREN
On Mon, 10 Oct 2022, Andi Shyti wrote:
> On Thu, Oct 06, 2022 at 10:48:44PM +0200, Andrzej Hajda wrote:
>> drm_device pointers are unwelcome.
>>
>> Signed-off-by: Andrzej Hajda
>
> Acked-by: Andi Shyti
>
> To me both versions were good...
>
> Jani, Ville, could you please check on this patch?
== Series Details ==
Series: drm/i915/gvt: fix double-free bug in split_2MB_gtt_entry (rev5)
URL : https://patchwork.freedesktop.org/series/108732/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12230 -> Patchwork_108732v5
S
Simplified pps_get_register() which use get_pps_idx() hook to derive the
pps instance and get_pps_idx() will be initialized at pps_init().
v1: Initial version. Got r-b from Jani.
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Uma Shankar
Signed-off-by: Animesh Manna
---
.../gpu/drm/i915/display/intel
>From display gen12 onwards to support dual EDP two instances of pps added.
Currently backlight controller and pps instance can be mapped together
for a specific panel. Currently dual PPS support is broken. This patch fixes
it and enables for display 12+.
v1: Iniital revision.
v2: Called intel_bio
> -Original Message-
> From: Nikula, Jani
> Sent: Tuesday, October 4, 2022 1:19 PM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Cc: Manna, Animesh ; Ville Syrjälä
> ; Shankar, Uma
> Subject: Re: [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario
>
> On Tue,
On Mon, Oct 10, 2022 at 02:30:49PM +0100, Matthew Auld wrote:
On 10/10/2022 07:58, Niranjana Vishwanathapura wrote:
Support eviction by maintaining a list of evicted persistent vmas
for rebinding during next submission. Ensure the list do not
include persistent vmas that are being purged.
v2: R
== Series Details ==
Series: series starting with [1/2] drm/i915/pps: Add get_pps_idx() hook as part
of pps_get_register() cleanup
URL : https://patchwork.freedesktop.org/series/109547/
State : warning
== Summary ==
Error: dim checkpatch failed
25167c11f19e drm/i915/pps: Add get_pps_idx() hoo
== Series Details ==
Series: series starting with [1/2] drm/i915/pps: Add get_pps_idx() hook as part
of pps_get_register() cleanup
URL : https://patchwork.freedesktop.org/series/109547/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12230 -> Patchwork_109547v1
On Thu, Oct 06, 2022 at 05:24:34PM -0400, Rodrigo Vivi wrote:
> On Wed, Oct 05, 2022 at 08:59:43AM -0700, Vinay Belgaumkar wrote:
> > Read the values stored in the SLPC structures. Remove the
> > fields that are no longer valid (like RPS interrupts) as
> > well.
> >
> > v2: Move all functionality
On 10/10/2022 17:11, Niranjana Vishwanathapura wrote:
On Mon, Oct 10, 2022 at 02:30:49PM +0100, Matthew Auld wrote:
On 10/10/2022 07:58, Niranjana Vishwanathapura wrote:
Support eviction by maintaining a list of evicted persistent vmas
for rebinding during next submission. Ensure the list do no
Add OA format support for DG2 and various fixes for DG2.
This series has 2 uapi changes listed below:
1) drm/i915/perf: Add OAG and OAR formats for DG2
DG2 has new OA formats defined that can be selected by the
user. The UMD changes that are consumed by GPUvis are:
https://patchwork.freedesktop.
DG2 introduces OA reports with 64 bit report header fields. Perf OA
would need more information about the OA format in order to process such
reports. Store all OA format info in oa_buffer instead of just the size
and format-id.
v2: Drop format_size variable (Ashutosh)
Signed-off-by: Umesh Nerlige
User passes uabi engine class and instance to the perf OA interface. Use
gt corresponding to the engine to pin the buffers to the right ggtt.
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 21 +++--
1 file changed, 19 i
Predication for batch buffer commands changed in XEHPSDV.
MI_BATCH_BUFFER_START predicates based on MI_SET_PREDICATE_RESULT
register. The MI_SET_PREDICATE_RESULT register can only be modified
with MI_SET_PREDICATE command. When configured, the MI_SET_PREDICATE
command sets MI_SET_PREDICATE_RESULT b
With GuC mode of submission, GuC is in control of defining the context
id field that is part of the OA reports. To filter reports, UMD and KMD
must know what sw context id was chosen by GuC. There is not interface
between KMD and GuC to determine this, so read the upper-dword of
EXECLIST_STATUS to
Disable Clock gating in EU when gathering the events so that EU events
are not lost.
v2: Fix checkpatch issues
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/i915_perf.c| 23 +
OA reports in the OA buffer contain an OA timestamp field that helps
user calculate delta between 2 OA reports. The calculation relies on the
CS timestamp frequency to convert the timestamp value to nanoseconds.
The CS timestamp frequency is a function of the CTC_SHIFT value in
RPM_CONFIG0.
In DG2
OA was disabled for DG2 as support was missing. Enable it back now.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index c9ab7eaa15ea..cb3c67abb
From: Vinay Belgaumkar
On DG2, a w/a resets RCS/CCS before it goes into RC6. This breaks OA
since OA does not expect engine resets during its use. Fix it by
disabling RC6.
v2: (Ashutosh)
- Bring back slpc_unset_param helper
- Update commit msg
- Use with_intel_runtime_pm helper for set/unset
v3
Add new OA formats for DG2.
v2:
- Update commit title (Ashutosh)
- Coding style fixes (Lionel)
- 64 bit OA formats need UMD changes in GPUvis, drop for now and send in a
separate series with UMD changes
v3:
- Update commit message to drop 64 bit related description
Signed-off-by: Umesh Nerlige
Some SKUs of same gen12 platform may have different oactxctrl
offsets. For gen12, determine oactxctrl offsets at runtime.
v2: (Lionel)
- Move MI definitions to intel_gpu_commands.h
- Ensure __find_reg_in_lri does read past context image size
v3: (Ashutosh)
- Drop unnecessary use of double undersc
If a drm client is killed, then hw contexts used by the client are reset
immediately. This reset clears the EU flex counter configuration. If an
OA use case is running in parallel, it would start seeing zeroed eu
counter values following the reset even if the drm client is restarted.
Save/restore t
XEHPSDV and DG2 provide a way to configure bytes per clock vs commands
per clock reporting. Enable bytes per clock setting on enabling OA.
Bspec: 51762
Bspec: 52201
v2:
- Fix commit msg (Ashutosh)
- Fix checkpatch issues
v3:
- s/commands/bytes/ in code comment and commmit msg
Signed-off-by: Ume
Earlier code used exclusive_stream to check for user passed context.
Simplify this by accessing stream->ctx.
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/g
With multi-gt, user can access multiple OA buffers concurrently. Use
stream->lock instead of gt->perf.lock to serialize file operations.
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_perf.c | 31 --
drivers/gpu/drm/i
From: Lionel Landwerlin
We have an additional register to select which slices contribute to
OAG/OAG counter increments.
Signed-off-by: Lionel Landwerlin
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu
Make perf part of gt as the OAG buffer is specific to a gt. The refactor
eventually simplifies programming the right OA buffer and the right HW
registers when supporting multiple gts.
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Lionel Landwerlin
Reviewed-by: Ashutosh Dixit
---
drivers/gp
We're observing sporadic HuC delayed load timeouts in CI, due to mei_pxp
binding completing later than we expected. HuC is still loaded when the
bind occurs, but in the meantime i915 has started allowing submission to
the VCS engines even if HuC is not there.
In most of the cases I've observed, the
I dont believe either of these failures are related to my changes as ICL and
SKL doesn't support PXP and after re-
looking at the change to "intel_pxp_is_enabled", I am confident it remains
consistent with prior code in that it would
return FALSE for any HW without PXP support after it checks "px
On 9/30/2022 16:42, Ceraolo Spurio, Daniele wrote:
On 9/30/2022 4:24 PM, John Harrison wrote:
On 9/22/2022 15:11, Daniele Ceraolo Spurio wrote:
Our current FW loading process is the same for all FWs:
- Pin FW to GGTT at the start of the ggtt->uc_fw node
- Load the FW
- Unpin
This worked becau
On 10/6/2022 15:20, Patchwork wrote:
Project List - Patchwork *Patch Details*
*Series:* Improve anti-pre-emption w/a for compute workloads (rev8)
*URL:* https://patchwork.freedesktop.org/series/100428/
*State:*failure
*Details:*
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_1
MTL and dgfx use the same DC5 counter.
While at it, this patch also adds the corresponding
debugfs entries. Some cleanup wrt dc3co register
which makes the code more readable.
Driver loads all firmware that it finds in the firmware
binary but platform doesn't *need* all of them. Cleaning the
prev
== Series Details ==
Series: drm/i915/huc: bump timeout for delayed load and reduce print verbosity
(rev2)
URL : https://patchwork.freedesktop.org/series/109455/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12231 -> Patchwork_109455v2
== Series Details ==
Series: drm/i915/display: Add DC5 counter and DMC debugfs entries for MTL (rev2)
URL : https://patchwork.freedesktop.org/series/109488/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12231 -> Patchwork_109488v2
==
== Series Details ==
Series: series starting with [1/2] drm/i915/pps: Add get_pps_idx() hook as part
of pps_get_register() cleanup
URL : https://patchwork.freedesktop.org/series/109547/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12230_full -> Patchwork_109547v1_full
==
== Series Details ==
Series: Add DG2 OA support (rev5)
URL : https://patchwork.freedesktop.org/series/107584/
State : warning
== Summary ==
Error: dim checkpatch failed
e7d2ddc2181d drm/i915/perf: Fix OA filtering logic for GuC mode
1d70790b1303 drm/i915/perf: Add 32-bit OAG and OAR formats fo
== Series Details ==
Series: Add DG2 OA support (rev5)
URL : https://patchwork.freedesktop.org/series/107584/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On 10/10/2022 11:48, Daniele Ceraolo Spurio wrote:
We're observing sporadic HuC delayed load timeouts in CI, due to mei_pxp
binding completing later than we expected. HuC is still loaded when the
bind occurs, but in the meantime i915 has started allowing submission to
the VCS engines even if HuC
On 10/10/2022 3:50 PM, John Harrison wrote:
On 10/10/2022 11:48, Daniele Ceraolo Spurio wrote:
We're observing sporadic HuC delayed load timeouts in CI, due to mei_pxp
binding completing later than we expected. HuC is still loaded when the
bind occurs, but in the meantime i915 has started all
> From: Alex Williamson
> Sent: Friday, October 7, 2022 2:31 AM
>
> On Thu, 6 Oct 2022 08:37:09 -0300
> Jason Gunthorpe wrote:
>
> > On Wed, Oct 05, 2022 at 04:03:56PM -0600, Alex Williamson wrote:
> > > We can't have a .remove callback that does nothing, this breaks
> > > removing the device w
Platforms prior to MTL do not have a separate media and graphics version.
On platforms where GMD id is not supported, reuse the graphics ip version,
release info for media.
The rest of the IP graphics, display versions would be copied during driver
creation.
While at it warn if GMD is not used fo
On Thu, Sep 29, 2022 at 04:17:43PM +0300, Mika Kahola wrote:
From: Radhakrishna Sripada
XELPDP has C10 and C20 phys from Synopsys to drive displays. Each phy
has a dedicated PIPE 5.2 Message bus for configuration. This message
bus is used to configure the phy internal registers.
Bspec: 64599,
1 - 100 of 126 matches
Mail list logo
