On Thu, Aug 18, 2022 at 04:02:28PM -0700, Daniele Ceraolo Spurio wrote:
> Note that this series includes several mei patches that add support for
> sending the HuC loading command via mei-gsc. These patches depend on the
> GSC support for DG2 [1], which has been included squashed in a single
> patc
Hi,
On 8/18/22 22:07, Daniel Dadap wrote:
>
> On 8/18/22 1:42 PM, Hans de Goede wrote:
>> On x86/ACPI boards the acpi_video driver will usually initialize before
>> the kms driver (except i915). This causes /sys/class/backlight/acpi_video0
>> to show up and then the kms driver registers its own n
> -Original Message-
> From: Nikula, Jani
> Sent: Wednesday, August 3, 2022 1:44 PM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Cc: ville.syrj...@linux.intel.com; Shankar, Uma ;
> Manna, Animesh
> Subject: Re: [PATCH] drm/i915/pps: added get_pps_idx() hook as part of
>
On Wed, 17 Aug 2022, "Shankar, Uma" wrote:
>> -Original Message-
>> From: Nikula, Jani
>> Sent: Wednesday, August 17, 2022 5:50 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani ; Shankar, Uma
>>
>> Subject: [PATCH] drm/i915/mtl: Meteorlake and later support DP 2.0
>>
>> Met
On Wed, 17 Aug 2022, "Kahola, Mika" wrote:
>> -Original Message-
>> From: Nikula, Jani
>> Sent: Wednesday, August 17, 2022 3:26 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani ; Ville Syrjälä
>> ; Kahola, Mika
>> Subject: [PATCH] drm/i915/mtl: Introduce FBC B
>>
>> From: Vi
On Wed, 17 Aug 2022, Jani Nikula wrote:
> On Wed, 17 Aug 2022, "Lisovskiy, Stanislav"
> wrote:
>> On Tue, Aug 16, 2022 at 06:37:20PM +0300, Jani Nikula wrote:
>>> Avoid using ports that aren't initialized in case the VBT backlight or
>>> CABC ports have invalid values. This fixes a NULL pointer
Hi,
On 8/18/22 21:38, Daniel Dadap wrote:
>
> On 8/18/22 1:42 PM, Hans de Goede wrote:
>> Move the WMI interface definitions to a header, so that the definitions
>> can be shared with drivers/acpi/video_detect.c .
>>
>> Suggested-by: Daniel Dadap
>> Signed-off-by: Hans de Goede
>> ---
>> MAIN
On Fri, 19 Aug 2022, Badal Nilawar wrote:
> From: Dale B Stimson
>
> The i915 HWMON module will be used to expose voltage, power and energy
> values for dGfx. Here we set up i915 hwmon infrastructure including i915
> hwmon registration, basic data structures and functions.
>
> v2:
> - Create HW
== Series Details ==
Series: drm/i915/pxp: don't start pxp without mei_pxp bind (rev3)
URL : https://patchwork.freedesktop.org/series/107099/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11998_full -> Patchwork_107099v3_full
===
On Fri, Aug 19, 2022 at 01:35:52PM +0300, Jani Nikula wrote:
> On Fri, 19 Aug 2022, Badal Nilawar wrote:
> > From: Dale B Stimson
> >
> > The i915 HWMON module will be used to expose voltage, power and energy
> > values for dGfx. Here we set up i915 hwmon infrastructure including i915
> > hwmon r
On 18.08.2022 19:42, Juston Li wrote:
pxp will not start correctly until after mei_pxp bind completes and
intel_pxp_init_hw() is called.
Wait for the bind to complete before proceeding with startup.
This fixes a race condition during bootup where we observed a small
window for pxp commands to be
Commit 368d179adbac ("drm/i915/guc: Add GuC <-> kernel time stamp
translation information") added intel_device_info_print_runtime() in the
time info dump for no obvious reason or explanation in the commit
message. It only logs the rawclk freq. Remove it.
Cc: John Harrison
Cc: Alan Previn
Signed-
v3 of https://patchwork.freedesktop.org/series/105358/
Add a patch resolving guc time stamp logging related conflicts in the
front, and remove the last two patches, for now, to avoid any
potentially regressing functional changes. Leave them for later.
Jani Nikula (14):
drm/i915/guc: remove run
We'll be moving info between static and runtime info. Combine the
printing functions into one to keep the output sensible and (mostly)
unchanged in the process.
Signed-off-by: Jani Nikula
Reviewed-by: Maarten Lankhort
---
drivers/gpu/drm/i915/i915_debugfs.c | 3 +--
drivers/gpu/drm/i915/i
Add initial runtime info that we can copy to runtime info at i915
creation time. This lets us define the initial values for runtime info
statically while making it possible to change them runtime. This will be
the new home for the current "const" device info members that are
modified runtime anyway
If it's modified runtime, it's runtime info.
v2: Rebase on mtl fbc_mask
Signed-off-by: Jani Nikula
Reviewed-by: Maarten Lankhort
---
drivers/gpu/drm/i915/display/intel_fbc.c | 6 ++---
.../drm/i915/display/skl_universal_plane.c| 2 +-
drivers/gpu/drm/i915/i915_drv.h |
If it's modified runtime, it's runtime info.
Signed-off-by: Jani Nikula
Reviewed-by: Maarten Lankhort
---
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 2 +-
.../gpu/drm/i915/gem/selftests/huge_pages.c| 14 +++---
drivers/gpu/drm/i915/i915_drv.h| 2 +-
drivers/g
If it's modified runtime, it's runtime info.
mock_gem_device() is the only one that modifies them. If that could be
fixed, we wouldn't have to do this.
Signed-off-by: Jani Nikula
Reviewed-by: Maarten Lankhort
---
drivers/gpu/drm/i915/i915_drv.h| 6 +++---
drivers/gpu/drm/i915/
If it's modified runtime, it's runtime info.
Signed-off-by: Jani Nikula
Reviewed-by: Maarten Lankhort
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 4 +--
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i9
If it's modified runtime, it's runtime info.
Signed-off-by: Jani Nikula
Reviewed-by: Maarten Lankhort
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_pci.c | 6 +++---
drivers/gpu/drm/i915/intel_device_info.c | 3 ++-
drivers/gpu/drm/i915/intel_device_inf
If it's modified runtime, it's runtime info.
Signed-off-by: Jani Nikula
Reviewed-by: Maarten Lankhort
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 4 ++--
drivers/gpu/drm/i915/i915_pci.c | 6 +++---
drivers/gpu/drm/i915/intel_device_info.c | 4 +++-
drivers/gpu/drm/i915/intel_devi
If it's modified runtime, it's runtime info.
Curiously, the flag was never initialized statically.
Signed-off-by: Jani Nikula
Reviewed-by: Maarten Lankhort
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 5 ++---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_device
If it's modified runtime, it's runtime info.
mock_gem_device() is the only one that modifies it. If that could be
fixed, we wouldn't have to do this.
Signed-off-by: Jani Nikula
Reviewed-by: Maarten Lankhort
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_
If it's modified runtime, it's runtime info.
mock_gem_device() is the only one that modifies it. If that could be
fixed, we wouldn't have to do this.
Signed-off-by: Jani Nikula
Reviewed-by: Maarten Lankhort
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/i915_pc
If it's modified runtime, it's runtime info.
Signed-off-by: Jani Nikula
Reviewed-by: Maarten Lankhort
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 2 +-
drivers/gpu/drm/i915/i915_pci.c | 4 ++--
drivers/gpu/drm/i915/intel_device_info.c | 3 ++-
drivers/gpu/drm/i915/intel_device_in
Hi Jouni,
On 7/15/22 10:49, Jouni Högander wrote:
> drm_plane_state->src might be modified by the driver. This is done
> e.g. in i915 driver when there is bigger framebuffer than the plane
> and there is some offset within framebuffer. I915 driver calculates
> separate offset and adjusts src rect
On 17/08/2022 21:07, Vivi, Rodrigo wrote:
On Tue, 2022-08-16 at 12:43 +0800, Zhenyu Wang wrote:
On 2022.08.16 12:05:08 +0800, Zhenyu Wang wrote:
On 2022.08.15 19:32:45 -0400, Rodrigo Vivi wrote:
On Mon, Aug 15, 2022 at 10:38:55AM +0800, Zhenyu Wang wrote:
Hi,
Here's one gvt-fixes pull for 6
Follow the advice of the below link and prefer 'strscpy' in this
subsystem. Conversion is 1:1 because the return value is not used.
Generated by a coccinelle script.
Link:
https://lore.kernel.org/r/CAHk-=wgfRnXz0W3D37d01q3JFkr_i_uTL=v6a6g1ouzcprm...@mail.gmail.com/
Signed-off-by: Wolfram Sang
--
On 2022-08-17 13:56, Lyude Paul wrote:
> Adding Mark Pearson from Lenovo to this, Mark for reference the original patch
> is here:
>
> https://patchwork.freedesktop.org/patch/497807/?series=107312&rev=1>>
> Comments from me down below
>
> On Wed, 2022-08-17 at 09:02 +0800, Kai-Heng Feng wrot
This reverts commit 6a079903847cce1dd06345127d2a32f26d2cd9c6.
Everything in CI using GuC is now timing out[1], and killing the machine
with this change (perhaps a deadlock?). CI was recently on fire due to
some changes coming in from -rc1, so likely the pre-merge CI results for
this series were in
== Series Details ==
Series: gpu: move from strlcpy with unused retval to strscpy
URL : https://patchwork.freedesktop.org/series/107501/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12003 -> Patchwork_107501v1
Summary
On Fri, 2022-08-19 at 09:09 -0300, Maíra Canal wrote:
> Hi Jouni,
>
> On 7/15/22 10:49, Jouni Högander wrote:
> > drm_plane_state->src might be modified by the driver. This is done
> > e.g. in i915 driver when there is bigger framebuffer than the plane
> > and there is some offset within framebuff
== Series Details ==
Series: Revert "drm/i915/guc: Add delay to disable scheduling after pin count
goes to zero"
URL : https://patchwork.freedesktop.org/series/107502/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked se
== Series Details ==
Series: Revert "drm/i915/guc: Add delay to disable scheduling after pin count
goes to zero"
URL : https://patchwork.freedesktop.org/series/107502/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12003 -> Patchwork_107502v1
==
.org/0day-ci/archive/20220819/202208192254.jhkstqcs-...@intel.com/config)
compiler: clang version 16.0.0 (https://github.com/llvm/llvm-project
0ac597f3cacf60479ffd36b03766fa7462dabd78)
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin
On 8/19/2022 12:21 AM, Greg Kroah-Hartman wrote:
On Thu, Aug 18, 2022 at 04:02:28PM -0700, Daniele Ceraolo Spurio wrote:
Note that this series includes several mei patches that add support for
sending the HuC loading command via mei-gsc. These patches depend on the
GSC support for DG2 [1], wh
On 8/19/2022 05:39, Matthew Auld wrote:
This reverts commit 6a079903847cce1dd06345127d2a32f26d2cd9c6.
Everything in CI using GuC is now timing out[1], and killing the machine
with this change (perhaps a deadlock?). CI was recently on fire due to
some changes coming in from -rc1, so likely the pr
Will look into this - apologies for the trouble Matt.
...alan
-Original Message-
From: Harrison, John C
Sent: Friday, August 19, 2022 8:46 AM
To: Auld, Matthew ; intel-gfx@lists.freedesktop.org
Cc: Brost, Matthew ; Teres Alexis, Alan Previn
Subject: Re: [PATCH] Revert "drm/i915/guc: A
On Thu, Aug 18, 2022 at 2:09 PM Lukas Wunner wrote:
>
> On Tue, Aug 16, 2022 at 11:06:18AM +0300, Jani Nikula wrote:
> > On Tue, 16 Aug 2022, Kai-Heng Feng wrote:
> > > On mobile workstations like HP ZBook Fury G8, iGFX's DP-IN can switch to
> > > dGFX so external monitors are routed to dGFX, and
On Thu, Aug 18, 2022 at 04:41:42PM -0700, Radhakrishna Sripada wrote:
> From: Matt Roper
>
> Going forward, the hardware teams no longer consider new platforms to
> have a "generation" in the way we've defined it for past platforms.
> Instead, each IP block (graphics, media, display) will have th
On Thu, Aug 18, 2022 at 04:41:48PM -0700, Radhakrishna Sripada wrote:
> Add tables to map the GMBUS pin pairs to GPIO registers and port to DDC.
> From spec we have registers GPIO_CTL[1-5] mapped to native display phys and
> GPIO_CTL[9-14] are mapped to TC ports.
>
> BSpec: 49306
>
> Original Aut
On Thu, Aug 18, 2022 at 04:41:54PM -0700, Radhakrishna Sripada wrote:
> Watermark latency is adjusted in cases when latency is 0us for level
> greater than 1, the subsequent levels are disabled. Extract this logic
> into its own function.
>
> Suggested-by: Matt Roper
> Signed-off-by: Radhakrishna
On Thu, Aug 18, 2022 at 04:41:55PM -0700, Radhakrishna Sripada wrote:
> Since Xe LPD+, Memory latency data are in LATENCY_LPX_LPY registers
> instead of GT driver mailbox.
>
> v2: Use the extracted wm latency adjustment function(Matt)
>
> Bspec: 64608
>
> Cc: Matt Roper
> Original Author: Caz Y
On Thu, Aug 18, 2022 at 04:42:02PM -0700, Radhakrishna Sripada wrote:
> No need to update mask value/restrict because
> "Pcode only wants to use GV bandwidth value, not the mask value."
> for Display version greater than 14.
While the code changes might be correct, I can't decipher what the
commit
On 8/19/2022 03:45, Jani Nikula wrote:
On Wed, 27 Jul 2022, john.c.harri...@intel.com wrote:
From: John Harrison
It is useful to be able to match GuC events to kernel events when
looking at the GuC log. That requires being able to convert GuC
timestamps to kernel time. So, when dumping error c
On DG2, HuC loading is performed by the GSC, via a PXP command. The load
operation itself is relatively simple (just send a message to the GSC
with the physical address of the HuC in LMEM), but there are timing
changes that requires special attention. In particular, to send a PXP
command we need to
From: Tomas Winkler
GSC extend header is of variable size and data
is provided in a sgl list inside the header
and not in the data buffers, need to enable the path.
Signed-off-by: Tomas Winkler
Signed-off-by: Daniele Ceraolo Spurio
Cc: Vitaly Lubart
Cc: Greg Kroah-Hartman
---
drivers/misc/m
From: Tomas Winkler
GSC command is and extended header containing a scatter gather
list and without a data buffer. Using MEI_CL_IO_SGL flag,
the caller send the GSC command as a data and the function internally
moves it to the extended header.
Signed-off-by: Tomas Winkler
Signed-off-by: Daniele
The mei_pxp module is required to send the command to load authenticate
the HuC to the GSC even if pxp is not in use for protected content
management.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Reviewed-by: Alan Previn
---
drivers/gpu/drm/i915/Makefile| 10 +++---
dr
From: Tomas Winkler
With on-boards graphics card, both i915 and MEI
are in the same device hierarchy with the same parent,
while for discrete gfx card the MEI is its child device.
Adjust the match function for that scenario
by matching MEI parent device with i915.
V2:
1. More detailed commit me
From: Vitaly Lubart
The discrete graphics card with GSC firmware
using command streamer API hence it requires to enhance
pxp module with the new gsc_command() handler.
The handler is implemented via mei_pxp_gsc_command() which is
just just a thin wrapper around mei_cldev_send_gsc_command()
V2:
From: Tomas Winkler
Add support for loading HuC via a pxp stream command.
Signed-off-by: Tomas Winkler
Signed-off-by: Vitaly Lubart
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Reviewed-by: Alan Previn
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915
Wait on the fence to be signalled to avoid the submissions finding HuC
not yet loaded.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Tony Ye
Reviewed-by: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/intel_huc.h | 6 ++
drivers/gpu/drm/i915/i915_request.c| 24
2 file
From: Vitaly Lubart
Command to be sent via the stream interface are written to a local
memory page, whose address is then provided to the GSC.
The interface supports providing a full sg with multiple pages for both
input and output messages, but since for now we only aim to support short
and sync
The current HuC status getparam return values are a bit confusing in
regards to what happens in some scenarios. In particular, most of the
error cases cause the ioctl to return an error, but a couple of them,
INIT_FAIL and LOAD_FAIL, are not explicitly handled and neither is
their expected return v
This is a squash of the GSC support for XeHP SDV and DG2 series, which
is being reviewed separately at:
https://patchwork.freedesktop.org/series/106638/
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/intel_gsc.c | 118 +---
drivers/gpu/drm/i915/gt/intel
Both are required for HuC loading.
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/Kconfig.debug | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/Kconfig.debug
b/drivers/gpu/drm/i915/Kconfig.debug
index e7fd3e76f8a2..a6576ffbc4dc 100644
--- a/drivers/gpu
The fw name is different and we need to record the fact that the blob is
gsc-loaded, so add a new macro to help.
Note: A-step DG2 G10 does not support HuC loading via GSC and would
require a separate firmware to be loaded the legacy way, but that's
not a production stepping so we're not going to b
The GSC will perform both the load and teh authentication, so we just
need to check the auth bit after the GSC has replied.
Since we require the PXP module to load the HuC, the earliest we can
trigger the load is during the pxp_bind operation.
Note that GSC-loaded HuC survives GT reset, so we need
Given that HuC load is delayed on DG2, this patch adds support for a fence
that can be used to wait for load completion. No waiters are added in this
patch (they're coming up in the next one), to keep the focus of the
patch on the tracking logic.
The full HuC loading flow on boot DG2 is as follows
The intention is to check for squashing, crawling and modeset conditions
at atomic check phase and prepare for commit phase. This basically
means the in-flight cdclk state is available. intel_cdclk_can_squash(),
intel_cdclk_can_crawl() and intel_cdclk_needs_modeset() have changes
to accommodate thi
This is a prep patch for what the rest of the series does.
Add existing actions that change cdclk - squash, crawl, modeset to
intel_cdclk_state so we have access to the cdclk values
that are in transition.
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cd
Checking cdclk conditions during atomic check and preparing
for commit phase so we can have atomic commit as simple
as possible. Add the specific steps to be taken during
cdclk changes, prepare for squashing, crawling and modeset
scenarios.
v2: Add intel_cdclk_modeset() similar to intel_cdclk_squa
Apart from checking if squashing can be performed,
accommodate accessing in-flight cdclk state for any changes
that are needed during commit phase.
v2: Move squashing bits to switch case.(Anusha)
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 62
Apart from checking if crawling can be performed,
accommodate accessing in-flight cdclk state for any changes
that are needed during commit phase.
v2: Move crawling steps to a switch case (anusha)
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 45
Host Turbo operates at efficient frequency when GT is not idle unless
the user or workload has forced it to a higher level. Replicate the same
behavior in SLPC by allowing the algorithm to use efficient frequency.
We had disabled it during boot due to concerns that it might break
kernel ABI for min
== Series Details ==
Series: CDCLK churn: move checks to atomic check
URL : https://patchwork.freedesktop.org/series/107522/
State : warning
== Summary ==
Error: dim checkpatch failed
c3061d754e21 drm/i915/display: Add CDCLK actions to intel_cdclk_state
d6438fdf45eb drm/i915/squash: s/intel_cd
== Series Details ==
Series: CDCLK churn: move checks to atomic check
URL : https://patchwork.freedesktop.org/series/107522/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: CDCLK churn: move checks to atomic check
URL : https://patchwork.freedesktop.org/series/107522/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12004 -> Patchwork_107522v1
Summary
---
**FAI
== Series Details ==
Series: drm/i915/guc/slpc: Allow SLPC to use efficient frequency (rev4)
URL : https://patchwork.freedesktop.org/series/107101/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12004 -> Patchwork_107101v4
S
== Series Details ==
Series: drm/i915: HuC loading for DG2
URL : https://patchwork.freedesktop.org/series/107477/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12002_full -> Patchwork_107477v1_full
Summary
---
**FAIL
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