On Thu, 14 Jul 2022 16:06:28 +0200
Michal Wajdeczko wrote:
> On 14.07.2022 14:06, Mauro Carvalho Chehab wrote:
> > From: Prathap Kumar Valsan
> >
> > Add routines to interface with GuC firmware for TLB invalidation.
> >
> > Signed-off-by: Prathap Kumar Valsan
> > Cc: Bruce Chang
> > Cc: Mich
On 01/08/2022 20:02, Umesh Nerlige Ramappa wrote:
On Wed, Jul 27, 2022 at 09:48:18AM +0100, Tvrtko Ursulin wrote:
On 27/07/2022 07:01, Umesh Nerlige Ramappa wrote:
On Fri, Jun 17, 2022 at 09:00:06AM +0100, Tvrtko Ursulin wrote:
On 16/06/2022 23:13, Nerlige Ramappa, Umesh wrote:
From: John
== Series Details ==
Series: drm/i915/dg2: Add support for DC5 state (rev3)
URL : https://patchwork.freedesktop.org/series/106816/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11962 -> Patchwork_106816v3
Summary
---
== Series Details ==
Series: drm/i915/dg2: Add Wa_1509727124 (rev2)
URL : https://patchwork.freedesktop.org/series/106822/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11961_full -> Patchwork_106822v2_full
Summary
---
== Series Details ==
Series: drm/i915/gem: Remove shared locking on freeing objects (rev2)
URL : https://patchwork.freedesktop.org/series/106720/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/gem: Remove shared locking on freeing objects (rev2)
URL : https://patchwork.freedesktop.org/series/106720/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11962 -> Patchwork_106720v2
Sum
A patch series was floated in the drm mailing list which aimed to change
the drm_connector and drm_encoder fields to pointer in the
drm_connector_writeback structure, this received a huge pushback from
the community but since i915 expects each connector present in the
drm_device list to be a intel_
Adding WD Types, WD transcoder to enum list and WD Transcoder offsets.
Adding i915 register definitions related to WD transcoder
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_display.h | 6 +
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/i91
Adding support for writeback transcoder to start capturing frames using
interrupt mechanism
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_acpi.c | 1 +
drivers/gpu/drm/i915/display/intel_crtc.c | 3 +
.../dr
== Series Details ==
Series: Enabling Pipewriteback
URL : https://patchwork.freedesktop.org/series/106902/
State : failure
== Summary ==
Error: make failed
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
CC
Hi Daniel,
On 7/21/22 23:30, Daniel Dadap wrote:
>
> On 7/21/22 16:24, Daniel Dadap wrote:
>>
>> On 7/12/22 14:38, Hans de Goede wrote:
>>> ATM on x86 laptops where we want userspace to use the acpi_video backlight
>>> device we often register both the GPU's native backlight device and
>>> acpi_v
== Series Details ==
Series: drm/i915/dg2: Add additional HDMI pixel clock frequencies (rev2)
URL : https://patchwork.freedesktop.org/series/106891/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11961_full -> Patchwork_106891v2_full
Hi Jani, Ville and Imre,
If there are no problems after reviewing this patch series, could you
please merge it?
Many thanks,
G.G.
On 7/22/22 3:51 PM, Andrzej Hajda wrote:
Hi Jani, Ville, Arun,
This patchset is replacement of patch
"drm/i915/display: disable HPD workers before display driver
On Thu, Jul 28, 2022 at 11:36:41AM -0700, Anusha Srivatsa wrote:
> With the latest DMC in place, enabling DC5 on DG2.
>
> Cc: Imre Deak
> Signed-off-by: Anusha Srivatsa
Reviewed-by: Imre Deak
Thanks for the patch, pushed to drm-intel-next.
The failures in the IGT CI result are unrelated, sin
On Fri, 22 Jul 2022, Ankit Nautiyal wrote:
> DSC capabilities are given in bytes 11-13 of VSDB (i.e. bytes 8-10 of
> SCDS). Since minimum length of Data block is 7, all bytes greater than 7
> must be read only after checking the length of the data block.
>
> This patch adds check for data block le
On Wed, 13 Jul 2022, Arun R Murthy wrote:
> The patch with commit 20f85ef89d94 ("drm/i915/backlight: use unique
> backlight device names") already adds support for dual panel backlight
> but with error prints. Since the patch tried to create the backlight
> device with the same name and upon failu
On 7/26/2022 9:15 PM, Patchwork wrote:
Project List - Patchwork *Patch Details*
*Series:* drm/i915/gem: Remove shared locking on freeing objects
*URL:* https://patchwork.freedesktop.org/series/106720/
*State:*failure
*Details:*
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_1
On Mon, Aug 01, 2022 at 02:38:39PM -0700, Harish Chegondi wrote:
> Bspec: 46052
> Reviewed-by: Matt Roper
> Signed-off-by: Harish Chegondi
Applied to drm-intel-gt-next. Thanks for the patch.
Matt
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
> drivers/gpu/drm/i915/gt/intel_work
Customer report abnormal display output while switch eDP off sometimes.
In current display disable flow, plane will be off at first. Then turn
eDP off and disable HW pipe line. Try to turn PLANE_SURF off before
disable PLANE_CTL. No more abnormal pixel appear on eDP with this changes.
Signed-off-b
On Fri, 22 Jul 2022, "Taylor, Clinton A" wrote:
> Use BSPEC values for the Audio Keep alive M and N values as included in
> the cdclk BSPEC pages for display > 13
>
> BSPEC: 54034, 55409
> Cc: Kai Vehmanen
> Cc: Uma Shankar
> Cc: Ville Syrjälä
> Signed-off-by: Taylor, Clinton A
> ---
> driver
On Mon, Aug 01, 2022 at 06:23:39PM -0700, Matt Roper wrote:
> On Wed, Jul 27, 2022 at 06:34:07PM -0700, Radhakrishna Sripada wrote:
> > From: Imre Deak
> >
> > Add support for display power wells on MTL. The differences from D13:
Also, this should be "...from Xe_LPD"
Matt
> > - The AUX HW blo
On Wed, Jul 27, 2022 at 06:34:08PM -0700, Radhakrishna Sripada wrote:
> From: Imre Deak
>
> On MTL TypeC ports the AUX_CH_CTL and AUX_CH_DATA addresses have
> changed wrt. previous platforms, adjust the code accordingly.
>
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/intel_d
On Wed, Jul 27, 2022 at 06:34:10PM -0700, Radhakrishna Sripada wrote:
> Since Xe LPD+, Memory latency data are in LATENCY_LPX_LPY registers
> instead of GT driver mailbox.
>
> Bspec: 64608
>
> Cc: Matt Roper
> Original Author: Caz Yokoyama
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/
On Wed, Jul 27, 2022 at 06:34:12PM -0700, Radhakrishna Sripada wrote:
> From Meteorlake, Latency Level, SAGV bloack time are read from
> LATENCY_SAGV register instead of the GT driver pcode mailbox. DDR type
> and QGV information are also tob read from Mem SS registers.
There seems to be a typo he
This patch series aims at enabling TTM support for system memory objects in
integrated graphics platforms. Whether one wishes to use TTM for sysmem
objects depends on a user-enabled kernel module parameter, so that the
former behaviour of using shmem objects for the system memory region is
kept by
From: Robert Beckett
Various places within the driver override the default chosen cache_level.
Before ttm, these overrides were permanent until explicitly changed again
or for the lifetime of the buffer.
TTM movement code came along and decided that it could make that
decision at that time, whic
When i915_gem_object_set_cache_level sets the GEM object's cache_dirty to
true, in the case of TTM that will sometimes be overwritten when getting
the object's pages, more specifically for shmem-placed objects for which
its ttm structure has just been populated.
This wasn't an issue so far, even t
From: Robert Beckett
i965G[M] cannot relocate objects above 4GiB.
Ensure ttm uses dma32 on these systems.
Signed-off-by: Robert Beckett
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/intel_region_ttm.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/g
Introduces a new module parameter, 'use_pool_alloc', which defaults to
'false'. Its goal is to make the driver fall back on TTM for setting up
the system memory region, so that object allocation will be done through
the TTM subsystem rather than shmem objects.
This commit only brings in the new ke
Allow system memory to be managed by TTM on integrated graphics platforms.
We replace using the shmem objects with similar use of TTM objects and can
then benefit from using alloc_page() pages instead of shmem pages.
This commit has no effect on DGFX hardware.
Because it manages objects allocated
From: Robert Beckett
By default i915_ttm_cache_level() decides I915_CACHE_LLC if HAS_SNOOP.
This is divergent from existing backends code which only considers
HAS_LLC.
Testing shows that trusting snooping on gen5- is unreliable and bsw via
ggtt mappings, so limit DGFX for now and maintain previou
On Wed, Jul 27, 2022 at 06:34:13PM -0700, Radhakrishna Sripada wrote:
> Like ADL_P, Meteorlake has different memory characteristics from
> past platforms. Update the values used by our memory bandwidth
> calculations accordingly.
>
> Bspec: 64631
>
> Cc: Matt Roper
> Cc: Caz Yokoyama
> Signed-o
i965gm devices cannot relocate objects above 4GiB. This situation was
already being handled in the older shmem GEM object backend, but not in TTM
for BO's that are allocated in system memory.
Borrow the code from shmem so that TTM handles them in the same way.
Signed-off-by: Adrian Larumbe
---
On Wed, Jul 27, 2022 at 06:34:14PM -0700, Radhakrishna Sripada wrote:
> Display version 14 platforms has different credits values compared to ADL-P.
s/has/have/
> Update the credits based on pipe usage.
>
> Bspec: 49213
>
> Cc: Jose Roberto de Souza
> Cc: Matt Roper
> Original Author: Caz Yok
== Series Details ==
Series: drm/i915/display: avoid abnormal pixel output when turn eDP display off
URL : https://patchwork.freedesktop.org/series/106910/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11963 -> Patchwork_106910v1
===
== Series Details ==
Series: Enable TTM for integrated GFX objects in sysmem
URL : https://patchwork.freedesktop.org/series/106913/
State : warning
== Summary ==
Error: dim checkpatch failed
30b2640e4185 drm/i915/ttm: dont trample cache_level overrides during ttm move
b283b8a7d71e drm/i915: li
== Series Details ==
Series: Enable TTM for integrated GFX objects in sysmem
URL : https://patchwork.freedesktop.org/series/106913/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
Looks good, just a minor nit.
Reviewed-by: Alan Previn
On Wed, 2022-07-06 at 14:43 +0300, Alexander Usyskin wrote:
> From: Tomas Winkler
>
> GSC requires more operational memory than available on chip.
> Reserve 4M of LMEM for GSC operation. The memory is provided to the
> GSC as struct resou
On Wed, Jul 27, 2022 at 06:34:15PM -0700, Radhakrishna Sripada wrote:
> Meteorlake uses a similar DBUF programming as ADL-P.
> Reuse the call flow for meteorlake.
Although the patch below is correct, the commit message and subject line
here are extremely misleading. MTL uses _very_ different
hand
Something minor in comments, so conditional R-B (please fix on the way in or
reply to correct me):
Reviewed-by: Alan Previn
On Wed, 2022-07-27 at 19:20 -0700, Harrison, John C wrote:
> From: Alan Previn
>
> Add a helper to get GuC log buffer size.
>
> Signed-off-by: Alan Previn
> Signed-off
On Wed, Jul 27, 2022 at 06:34:16PM -0700, Radhakrishna Sripada wrote:
> From: José Roberto de Souza
>
> Display version 14 also supports MBUS joining just like ADL-P
> and also it don't need MBUS initialization, so extending ADL-P
s/don't/doesn't/
Otherwise,
Reviewed-by: Matt Roper
> code pa
Straight forward change - LGTM.
Reviewed-by: Alan Previn
On Wed, 2022-07-27 at 19:20 -0700, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> There was a size check to warn if the GuC error state capture buffer
> allocation would be too small to fit a reasonable amount of capture
>
== Series Details ==
Series: Enable TTM for integrated GFX objects in sysmem
URL : https://patchwork.freedesktop.org/series/106913/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11963 -> Patchwork_106913v1
Summary
---
On Wed, Jul 27, 2022 at 06:34:17PM -0700, Radhakrishna Sripada wrote:
> From: Madhumitha Tolakanahalli Pradeep
>
>
> Adding support to load DMC v2.08 on MTL.
>
> Signed-off-by: Madhumitha Tolakanahalli Pradeep
>
> ---
> drivers/gpu/drm/i915/display/intel_dmc.c | 11 ++-
> 1 file chan
On Wed, Jul 27, 2022 at 06:34:18PM -0700, Radhakrishna Sripada wrote:
> From: Anusha Srivatsa
>
> MTL needs both Pipe A and Pipe B DMC to be loaded
> along with Main DMC. Patch also adds
That's true, but it's unrelated to this patch. intel_dmc_load_program()
always loads all of the pipe firmwar
One minor NIT (though i hope it could be fixed otw in as it adds a bit of
ease-of-log-readibility).
That said, everything else looks good.
Reviewed-by: Alan Previn
On Wed, 2022-07-27 at 19:20 -0700, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> When debugging GuC communication i
One concern below. Else, nice, simple yet good optimization here. :)
In the interest of quicker progression, I will provide a conditional R-B if you
can either fix the issue raised below on
the way in or provide a reason why that's not an issue:
Reviewed-by: Alan Previn
On Wed, 2022-07-27 at 1
>
> Looks good, just a minor nit.
>
> Reviewed-by: Alan Previn
>
>
> On Wed, 2022-07-06 at 14:43 +0300, Alexander Usyskin wrote:
> > From: Tomas Winkler
> >
> > GSC requires more operational memory than available on chip.
> > Reserve 4M of LMEM for GSC operation. The memory is provided to the
Reviewed-by: Alan Previn
On Wed, 2022-07-27 at 19:20 -0700, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> Some debug code got left in when the GuC based register save for error
> capture was added. Remove that.
>
> Signed-off-by: John Harrison
> ---
> .../gpu/drm/i915/gt/uc/int
== Series Details ==
Series: drm/i915/dg2: Add support for DC5 state (rev3)
URL : https://patchwork.freedesktop.org/series/106816/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11962_full -> Patchwork_106816v3_full
Summary
On Wed, 2022-06-15 at 04:28 +, Lin, Wayne wrote:
> [Public]
>
> Thank you Lyude for addressing this!
>
> VCPI is also a confusing naming to me at first glance since it stands for
> Virtual Channel Payload Identification which is just an ID number ( we can
> look up these payload IDs In DPC
== Series Details ==
Series: drm/i915/gem: Remove shared locking on freeing objects (rev2)
URL : https://patchwork.freedesktop.org/series/106720/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11962_full -> Patchwork_106720v2_full
===
On Fri, Jul 29, 2022 at 09:03:54AM +0200, Mauro Carvalho Chehab wrote:
From: Chris Wilson
Prepare for supporting more TLB invalidation scenarios by moving
the current MMIO invalidation to its own file.
And looks like,
1. Rename intel_gt_invalidate_tlb() to intel_gt_invalidate_tlb_full()
2. Ad
On Fri, Jul 29, 2022 at 09:03:55AM +0200, Mauro Carvalho Chehab wrote:
Add a description for the TLB cache invalidation algorithm and for
the related kAPI functions.
Signed-off-by: Mauro Carvalho Chehab
---
To avoid mailbombing on a large number of people, only mailing lists were C/C
on the c
On Tue, Aug 02, 2022 at 09:41:38AM +0100, Tvrtko Ursulin wrote:
On 01/08/2022 20:02, Umesh Nerlige Ramappa wrote:
On Wed, Jul 27, 2022 at 09:48:18AM +0100, Tvrtko Ursulin wrote:
On 27/07/2022 07:01, Umesh Nerlige Ramappa wrote:
On Fri, Jun 17, 2022 at 09:00:06AM +0100, Tvrtko Ursulin wrote:
On 8/2/2022 11:48, Teres Alexis, Alan Previn wrote:
One concern below. Else, nice, simple yet good optimization here. :)
In the interest of quicker progression, I will provide a conditional R-B if you
can either fix the issue raised below on
the way in or provide a reason why that's not an issu
On 8/2/2022 11:27, Teres Alexis, Alan Previn wrote:
One minor NIT (though i hope it could be fixed otw in as it adds a bit of
ease-of-log-readibility).
That said, everything else looks good.
Reviewed-by: Alan Previn
On Wed, 2022-07-27 at 19:20 -0700, john.c.harri...@intel.com wrote:
From:
On 8/2/2022 10:37, Teres Alexis, Alan Previn wrote:
Something minor in comments, so conditional R-B (please fix on the way in or
reply to correct me):
Reviewed-by: Alan Previn
On Wed, 2022-07-27 at 19:20 -0700, Harrison, John C wrote:
From: Alan Previn
Add a helper to get GuC log buffer si
To support dual LFP two instances of pps added from display gen12 onwards.
Few older platform like VLV also has dual pps support but handling is
different. So added separate hook get_pps_idx() to formulate which pps
instance to used for a soecific LFP on a specific platform.
Simplified pps_get_reg
== Series Details ==
Series: drm/i915/pps: added get_pps_idx() hook as part of pps_get_register()
cleanup
URL : https://patchwork.freedesktop.org/series/106922/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11964 -> Patchwork_106922v1
=
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