Re: [Intel-gfx] [PATCH 2/2] drm/i915/fbdev: suspend HPD before fbdev unregistration

Thanks for comments, On 29.06.2022 07:38, Murthy, Arun R wrote: void intel_fbdev_unregister(struct drm_i915_private *dev_priv) { struct intel_fbdev *ifbdev = dev_priv->fbdev; @@ -573,6 +594,8 @@ void intel_fbdev_unregister(struct drm_i915_private *dev_priv) if (!ifbdev)

Re: [Intel-gfx] [PATCH v3 13/14] mei: debugfs: add pxp mode to devstate in debugfs

> > On Sun, Jun 19, 2022 at 04:37:20PM +0300, Alexander Usyskin wrote: > > From: Tomas Winkler > > > > CC: Vitaly Lubart > > Signed-off-by: Tomas Winkler > > We can not take patches without any changelog text, you know this :( Okay, will add some more info. > > > --- > > drivers/misc/mei/d

Re: [Intel-gfx] [PATCH v6 02/22] drm/gem: Move mapping of imported dma-bufs to drm_gem_mmap_obj()

On 6/29/22 10:22, Dmitry Osipenko wrote: On 6/29/22 09:40, Thomas Hellström (Intel) wrote: On 5/27/22 01:50, Dmitry Osipenko wrote: Drivers that use drm_gem_mmap() and drm_gem_mmap_obj() helpers don't handle imported dma-bufs properly, which results in mapping of something else than the impor

Re: [Intel-gfx] [PATCH i-g-t 3/3] tests/amdgpu/amdgpu_command_submission: fix uaf

Looks good to me. Reviewed-by: Gwan-gyeong Mun On 6/28/22 4:13 PM, Matthew Auld wrote: ../lib/amdgpu/amd_command_submission.c: In function ‘amdgpu_command_submission_write_linear_helper’: ../lib/amdgpu/amd_command_submission.c:201:13: warning: pointer ‘ring_context’ used after ‘free’ [-Wuse

[Intel-gfx] [CI RESEND 00/10] drm/edid: expand on struct drm_edid usage

Resend of [1] for CI, also sending without the i915 changes, to be merged on top. BR, Jani. [1] https://patchwork.freedesktop.org/series/104309/ Jani Nikula (10): drm/edid: move drm_connector_update_edid_property() to drm_edid.c drm/edid: convert drm_connector_update_edid_property() to stru

[Intel-gfx] [CI RESEND 01/10] drm/edid: move drm_connector_update_edid_property() to drm_edid.c

The function needs access to drm_edid.c internals more than drm_connector.c. We can make drm_reset_display_info(), drm_add_display_info() and drm_update_tile_info() static. There will be more benefits with follow-up struct drm_edid refactoring. Signed-off-by: Jani Nikula Reviewed-by: Ville Syrjäl

[Intel-gfx] [CI RESEND 02/10] drm/edid: convert drm_connector_update_edid_property() to struct drm_edid

Make drm_connector_update_edid_property() a thin wrapper around a struct drm_edid based version of the same. This lets us remove the legacy drm_update_tile_info() and drm_add_display_info() functions altogether. Signed-off-by: Jani Nikula Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/drm_edid

[Intel-gfx] [CI RESEND 03/10] drm/edid: clean up connector update error handling and debug logging

Bail out on all errors, debug log all errors, and convert to drm device based debug logging. Signed-off-by: Jani Nikula Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/drm_edid.c | 41 ++ 1 file changed, 28 insertions(+), 13 deletions(-) diff --git a/drivers/

[Intel-gfx] [CI RESEND 04/10] drm/edid: abstract debugfs override EDID set/reset

Add functions drm_edid_override_set() and drm_edid_override_reset() to support "edid_override" connector debugfs, and to hide the details about it in drm_edid.c. No functional changes at this time. Also note in the connector.override_edid flag kernel-doc that this is only supposed to be modified b

[Intel-gfx] [CI RESEND 05/10] drm/edid: add drm_edid_connector_update()

Add a new function drm_edid_connector_update() to replace the combination of calls drm_connector_update_edid_property() and drm_add_edid_modes(). Usually they are called in the drivers in this order, however the former needs information from the latter. Since the new drm_edid_read*() functions no

[Intel-gfx] [CI RESEND 06/10] drm/probe-helper: add drm_connector_helper_get_modes()

Add a helper function to be used as the "default" .get_modes() hook. This also works as an example of what the driver .get_modes() hooks are supposed to do regarding the new drm_edid_read*() and drm_edid_connector_update() calls. Signed-off-by: Jani Nikula Reviewed-by: Ville Syrjälä --- drivers

[Intel-gfx] [CI RESEND 07/10] drm/edid: add drm_edid_raw() to access the raw EDID data

Unfortunately, there are still plenty of interfaces around that require a struct edid pointer, and it's impossible to change them all at once. Add an accessor to the raw EDID data to help the transition. While there are no such cases now, be defensive against raw EDID extension count indicating bi

[Intel-gfx] [CI RESEND 09/10] drm/edid: add HF-EEODB support to EDID read and allocation

HDMI 2.1 section 10.3.6 defines an HDMI Forum EDID Extension Override Data Block, which may contain a different extension count than the base block claims. Add support for reading more EDID data if available. The extra blocks aren't parsed yet, though. Hard-coding the EEODB parsing instead of usin

[Intel-gfx] [CI RESEND 08/10] drm/edid: do invalid block filtering in-place

Rewrite edid_filter_invalid_blocks() to filter invalid blocks in-place. The main motivation is to not rely on passed in information on invalid block count or the allocation size, which will be helpful in follow-up work on HF-EEODB. Signed-off-by: Jani Nikula Reviewed-by: Ville Syrjälä --- drive

[Intel-gfx] [CI RESEND 10/10] drm/edid: take HF-EEODB extension count into account

Take the HF-EEODB extension count override into account. Signed-off-by: Jani Nikula Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/drm_edid.c | 13 + 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index fa3a3e294560..bbc25e3b72

Re: [Intel-gfx] [RFC PATCH 2/2] drm/i915: Enabling WD Transcoder

On Wed, 01 Jun 2022, Suraj Kandpal wrote: > Adding support for writeback transcoder to start capturing frames using > interrupt mechanism. Some notes inline based on our discussion off-list. > > Signed-off-by: Suraj Kandpal > --- > drivers/gpu/drm/i915/Makefile | 1 + > drive

[Intel-gfx] [PULL] drm-intel-gt-next

Hi Dave, Daniel, This is the first pull request for 5.20 merge window. A lot of fixes across the board, a few improvements and quite a lot of driver refactoring to prepare for Ponte Vecchio, and then a bunch of Ponte Vecchio early enablement on top. In terms of improvements, we now enable huge p

[Intel-gfx] [PULL] drm-intel-fixes

Hi Dave & Daniel - drm-intel-fixes-2022-06-29: drm/i915 fixes for v5.19-rc5: - Fix ioctl argument error return - Fix d3cold disable to allow PCI upstream bridge D3 transition - Fix setting cache_dirty for dma-buf objects on discrete Rodrigo will cover the remaining fixes until v5.19 final. B

[Intel-gfx] [PATCH] drm/fb-helper: Remove helpers to change frame buffer config

The DRM fbdev emulation layer does not support pushing back changes to fb_var_screeninfo to KMS. However, drm_fb_helper still implements the fb_ops.fb_check_var() and fb_ops.fb_set_par() callbacks, but the former fails to validate various parameters passed from userspace. Hence unsanitized and po

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/edid: expand on struct drm_edid usage (rev8)

== Series Details == Series: drm/edid: expand on struct drm_edid usage (rev8) URL : https://patchwork.freedesktop.org/series/104309/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] [PATCH v4 00/14] GSC support for XeHP SDV and DG2 platforms

Add GSC support for XeHP SDV and DG2 platforms. The series includes changes for the mei driver: - add ability to use polling instead of interrupts - add ability to use extended timeouts - setup extended operational memory for GSC The series includes changes for the i915 driver: - allocate extende

[Intel-gfx] [PATCH v4 01/14] HAX: drm/i915: force INTEL_MEI_GSC on for CI

From: Daniele Ceraolo Spurio After the new config option is merged we'll enable it by default in the CI config, but for now just force it on via the i915 Kconfig so we can get pre-merge CI results for it. Signed-off-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/Kconfig.debug | 1 + 1 fil

[Intel-gfx] [PATCH v4 02/14] drm/i915/gsc: skip irq initialization if using polling

From: Vitaly Lubart Some platforms require the host to poll on the GSC registers instead of relaying on the interrupts. For those platforms, irq initialization should be skipped Signed-off-by: Vitaly Lubart Signed-off-by: Tomas Winkler Signed-off-by: Alexander Usyskin Reviewed-by: Daniele Cer

[Intel-gfx] [PATCH v4 03/14] drm/i915/gsc: add slow_fw flag to the mei auxiliary device

Add slow_fw flag to the mei auxiliary device info to inform the mei driver about slow underlying firmware. Such firmware will require to use larger operation timeouts. Signed-off-by: Alexander Usyskin Signed-off-by: Tomas Winkler Reviewed-by: Daniele Ceraolo Spurio --- include/linux/mei_aux.h

[Intel-gfx] [PATCH v4 04/14] drm/i915/gsc: add slow_fw flag to the gsc device definition

Add slow_fw flag to the gsc device definition and pass it to mei auxiliary device. Signed-off-by: Alexander Usyskin Reviewed-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/gt/intel_gsc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gp

[Intel-gfx] [PATCH v4 05/14] drm/i915/gsc: add GSC XeHP SDV platform definition

Define GSC on XeHP SDV (Intel(R) dGPU without display) XeHP SDV uses the same hardware settings as DG1, but uses polling instead of interrupts and runs the firmware in slow pace due to hardware limitations. Signed-off-by: Vitaly Lubart Signed-off-by: Tomas Winkler Signed-off-by: Alexander Usysk

[Intel-gfx] [PATCH v4 06/14] mei: gsc: use polling instead of interrupts

From: Tomas Winkler A work-around for a HW issue in XEHPSDV that manifests itself when SW reads a gsc register when gsc is sending an interrupt. The work-around is to disable interrupts and to use polling instead. Cc: James Ausmus Signed-off-by: Vitaly Lubart Signed-off-by: Tomas Winkler ---

[Intel-gfx] [PATCH v4 07/14] mei: gsc: wait for reset thread on stop

Wait for reset work to complete before initiating stop reset flow sequence. Signed-off-by: Alexander Usyskin Signed-off-by: Tomas Winkler --- drivers/misc/mei/init.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/misc/mei/init.c b/drivers/misc/mei/init.c index eb052005ca86..5bb6b

[Intel-gfx] [PATCH v4 08/14] mei: extend timeouts on slow devices.

Parametrize operational timeouts in order to support slow firmware on some graphic devices. Signed-off-by: Alexander Usyskin Signed-off-by: Tomas Winkler --- drivers/misc/mei/bus-fixup.c | 3 +-- drivers/misc/mei/client.c| 14 +++--- drivers/misc/mei/gsc-me.c| 2 +- drivers/mi

[Intel-gfx] [PATCH v4 09/14] mei: bus: export common mkhi definitions into a separate header

From: Vitaly Lubart Exported common mkhi definitions from bus-fixup.c into a separate header file mkhi.h for other driver usage. Signed-off-by: Vitaly Lubart Signed-off-by: Tomas Winkler --- drivers/misc/mei/bus-fixup.c | 32 ++--- drivers/misc/mei/mkhi.h | 45 +++

[Intel-gfx] [PATCH v4 10/14] mei: mkhi: add memory ready command

From: Tomas Winkler Add GSC memory ready command. The command indicates to the firmware that extend operation memory was setup and the firmware may enter PXP mode. CC: Daniele Ceraolo Spurio Signed-off-by: Tomas Winkler --- drivers/misc/mei/mkhi.h | 14 +- 1 file changed, 13 inser

[Intel-gfx] [PATCH v4 11/14] mei: gsc: setup gsc extended operational memory

From: Tomas Winkler 1. Retrieve extended operational memory physical pointers from the auxiliary device info. 2. Setup memory registers. 3. Notify firmware that the memory is ready by sending the memory ready command. 4. Disable PXP device if GSC is not in PXP mode. CC: Daniele Ceraolo Spu

[Intel-gfx] [PATCH v4 12/14] mei: gsc: add transition to PXP mode in resume flow

From: Vitaly Lubart Added transition to PXP mode in resume flow. CC: Daniele Ceraolo Spurio Signed-off-by: Vitaly Lubart Signed-off-by: Tomas Winkler --- drivers/misc/mei/gsc-me.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gs

[Intel-gfx] [PATCH v4 13/14] mei: debugfs: add pxp mode to devstate in debugfs

From: Tomas Winkler Add pxp mode devstate to debugfs to monitor pxp state machine progress. During debug it is important to understand in what state the pxp handshake is. CC: Vitaly Lubart Signed-off-by: Tomas Winkler --- drivers/misc/mei/debugfs.c | 17 + 1 file changed, 17 i

[Intel-gfx] [PATCH v4 14/14] drm/i915/gsc: allocate extended operational memory in LMEM

From: Tomas Winkler GSC requires more operational memory than available on chip. Reserve 4M of LMEM for GSC operation. The memory is provided to the GSC as struct resource to the auxiliary data of the child device. Signed-off-by: Tomas Winkler Signed-off-by: Daniele Ceraolo Spurio Cc: Alan Pre

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/edid: expand on struct drm_edid usage (rev8)

== Series Details == Series: drm/edid: expand on struct drm_edid usage (rev8) URL : https://patchwork.freedesktop.org/series/104309/ State : success == Summary == CI Bug Log - changes from CI_DRM_11825 -> Patchwork_104309v8 Summary ---

[Intel-gfx] [PATCH v3 00/13] small BAR uapi bits

IGT: https://patchwork.freedesktop.org/series/104368/#rev2 Mesa: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16739 -- 2.36.1

[Intel-gfx] [PATCH v3 01/13] drm/doc: add rfc section for small BAR uapi

Add an entry for the new uapi needed for small BAR on DG2+. v2: - Some spelling fixes and other small tweaks. (Akeem & Thomas) - Rework error capture interactions, including no longer needing NEEDS_CPU_ACCESS for objects marked for capture. (Thomas) - Add probed_cpu_visible_size. (Lionel

[Intel-gfx] [PATCH v3 02/13] drm/i915/uapi: add probed_cpu_visible_size

Userspace wants to know the size of CPU visible portion of device local-memory, and on small BAR devices the probed_size is no longer enough. In Vulkan, for example, it would like to know the size in bytes for CPU visible VkMemoryHeap. We already track the io_size for each region, so plumb that thr

[Intel-gfx] [PATCH v3 03/13] drm/i915/uapi: expose the avail tracking

Vulkan would like to have a rough measure of how much device memory can in theory be allocated. Also add unallocated_cpu_visible_size to track the visible portion, in case the device is using small BAR. Also tweak the locking so we nice consistent values for both the mm->avail and the visible track

[Intel-gfx] [PATCH v3 08/13] drm/i915/uapi: tweak error capture on recoverable contexts

A non-recoverable context must be used if the user wants proper error capture on discrete platforms. In the future the kernel may want to blit the contents of some objects when later doing the capture stage. Also extend to newer integrated platforms. v2(Thomas): - Also extend to newer integrated

[Intel-gfx] [PATCH v3 06/13] drm/i915/uapi: add NEEDS_CPU_ACCESS hint

If set, force the allocation to be placed in the mappable portion of I915_MEMORY_CLASS_DEVICE. One big restriction here is that system memory (i.e I915_MEMORY_CLASS_SYSTEM) must be given as a potential placement for the object, that way we can always spill the object into system memory if we can't

[Intel-gfx] [PATCH v3 07/13] drm/i915/error: skip non-mappable pages

Skip capturing any lmem pages that can't be copied using the CPU. This in now only best effort on platforms that have small BAR. Testcase: igt@gem-exec-capture@capture-invisible Signed-off-by: Matthew Auld Cc: Thomas Hellström Cc: Lionel Landwerlin Cc: Tvrtko Ursulin Cc: Jon Bloomfield Cc: Da

[Intel-gfx] [PATCH v3 05/13] drm/i915/uapi: apply ALLOC_GPU_ONLY by default

On small BAR configurations, when dealing with I915_MEMORY_CLASS_DEVICE allocations, we assume that by default, all userspace allocations should be placed in the non-CPU visible portion. Note that dumb buffers are not included here, since these are not "GPU accelerated" and likely need CPU access.

[Intel-gfx] [PATCH v3 04/13] drm/i915: remove intel_memory_region avail

No longer used. Signed-off-by: Matthew Auld Cc: Thomas Hellström Cc: Lionel Landwerlin Cc: Tvrtko Ursulin Cc: Jon Bloomfield Cc: Daniel Vetter Cc: Jordan Justen Cc: Kenneth Graunke Cc: Akeem G Abodunrin Reviewed-by: Thomas Hellström --- drivers/gpu/drm/i915/intel_memory_region.c | 4 +--

[Intel-gfx] [PATCH v3 10/13] drm/i915/selftests: ensure we reserve a fence slot

We should always be explicit and allocate a fence slot before adding a new fence. Signed-off-by: Matthew Auld Cc: Thomas Hellström Cc: Lionel Landwerlin Cc: Tvrtko Ursulin Cc: Jon Bloomfield Cc: Daniel Vetter Cc: Jordan Justen Cc: Kenneth Graunke Cc: Akeem G Abodunrin Reviewed-by: Thomas

[Intel-gfx] [PATCH v3 09/13] drm/i915/selftests: skip the mman tests for stolen

It's not supported, and just skips later anyway. With small-BAR things get more complicated since all of stolen is likely not even CPU accessible, hence not passing I915_BO_ALLOC_GPU_ONLY just results in the object create failing. Signed-off-by: Matthew Auld Cc: Thomas Hellström Cc: Lionel Landw

[Intel-gfx] [PATCH v3 11/13] drm/i915/ttm: handle blitter failure on DG2

If the move or clear operation somehow fails, and the memory underneath is not cleared, like when moving to lmem, then we currently fallback to memcpy or memset. However with small-BAR systems this fallback might no longer be possible. For now we use the set_wedged sledgehammer if we ever encounter

[Intel-gfx] [PATCH v3 12/13] drm/i915/ttm: disallow CPU fallback mode for ccs pages

Falling back to memcpy/memset shouldn't be allowed if we know we have CCS state to manage using the blitter. Otherwise we are potentially leaving the aux CCS state in an unknown state, which smells like an info leak. Fixes: 48760ffe923a ("drm/i915/gt: Clear compress metadata for Flat-ccs objects"

[Intel-gfx] [PATCH v3 13/13] drm/i915: turn on small BAR support

With the uAPI in place we should now have enough in place to ensure a working system on small BAR configurations. v2: (Nirmoy & Thomas): - s/full BAR/Resizable BAR/ which is hopefully more easily understood by users. Signed-off-by: Matthew Auld Cc: Thomas Hellström Cc: Lionel Landwerlin

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/fb-helper: Remove helpers to change frame buffer config

== Series Details == Series: drm/fb-helper: Remove helpers to change frame buffer config URL : https://patchwork.freedesktop.org/series/105773/ State : success == Summary == CI Bug Log - changes from CI_DRM_11825 -> Patchwork_105773v1 Summa

Re: [Intel-gfx] [PATCH v3 12/13] drm/i915/ttm: disallow CPU fallback mode for ccs pages

On 2022-06-29 at 13:14:26 +0100, Matthew Auld wrote: > Falling back to memcpy/memset shouldn't be allowed if we know we have > CCS state to manage using the blitter. Otherwise we are potentially > leaving the aux CCS state in an unknown state, which smells like an info > leak. > > Fixes: 48760ffe9

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: ttm for stolen (rev5)

On 28/06/2022 17:22, Robert Beckett wrote: On 28/06/2022 09:46, Tvrtko Ursulin wrote: On 27/06/2022 18:08, Robert Beckett wrote: On 22/06/2022 10:05, Tvrtko Ursulin wrote: On 21/06/2022 20:11, Robert Beckett wrote: On 21/06/2022 18:37, Patchwork wrote: *Patch Details* *Series:*   

[Intel-gfx] ✗ Fi.CI.BAT: failure for GSC support for XeHP SDV and DG2 platforms (rev4)

== Series Details == Series: GSC support for XeHP SDV and DG2 platforms (rev4) URL : https://patchwork.freedesktop.org/series/102339/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11825 -> Patchwork_102339v4 Summary ---

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for small BAR uapi bits (rev4)

== Series Details == Series: small BAR uapi bits (rev4) URL : https://patchwork.freedesktop.org/series/104369/ State : warning == Summary == Error: dim checkpatch failed 0815fb1423e5 drm/doc: add rfc section for small BAR uapi -:46: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), d

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for small BAR uapi bits (rev4)

== Series Details == Series: small BAR uapi bits (rev4) URL : https://patchwork.freedesktop.org/series/104369/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.BAT: failure for small BAR uapi bits (rev4)

== Series Details == Series: small BAR uapi bits (rev4) URL : https://patchwork.freedesktop.org/series/104369/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11825 -> Patchwork_104369v4 Summary --- **FAILURE** Seri

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/edid: expand on struct drm_edid usage (rev7)

== Series Details == Series: drm/edid: expand on struct drm_edid usage (rev7) URL : https://patchwork.freedesktop.org/series/104309/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11820_full -> Patchwork_104309v7_full Summar

Re: [Intel-gfx] [RESEND RFC 08/18] drm/display/dp_mst: Add nonblocking helpers for DP MST

On Tue, 07 Jun 2022, Lyude Paul wrote: > As Daniel Vetter pointed out, if we only use the atomic modesetting locks > with MST it's technically possible for a driver with non-blocking modesets > to race when it comes to MST displays - as we make the mistake of not doing > our own CRTC commit tracki

[Intel-gfx] [PATCH] drm/i915: Drain freed object after suspend display

Display is turned off by i915_drm_suspend() during the suspend procedure, removing the last reference of some gem objects that were used by display. The issue is that those objects are only actually freed when mm.free_work executed and that can happen very late in the suspend process causing issue

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/guc/slpc: Add a new SLPC selftest (rev5)

== Series Details == Series: drm/i915/guc/slpc: Add a new SLPC selftest (rev5) URL : https://patchwork.freedesktop.org/series/105005/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11820_full -> Patchwork_105005v5_full Summa

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Drain freed object after suspend display

== Series Details == Series: drm/i915: Drain freed object after suspend display URL : https://patchwork.freedesktop.org/series/105779/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11825 -> Patchwork_105779v1 Summary --

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for small BAR uapi bits (rev5)

== Series Details == Series: small BAR uapi bits (rev5) URL : https://patchwork.freedesktop.org/series/104369/ State : warning == Summary == Error: dim checkpatch failed fca09013097d drm/doc: add rfc section for small BAR uapi -:46: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), d

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for small BAR uapi bits (rev5)

== Series Details == Series: small BAR uapi bits (rev5) URL : https://patchwork.freedesktop.org/series/104369/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.BAT: failure for small BAR uapi bits (rev5)

== Series Details == Series: small BAR uapi bits (rev5) URL : https://patchwork.freedesktop.org/series/104369/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11825 -> Patchwork_104369v5 Summary --- **FAILURE** Seri

[Intel-gfx] [PATCH v2 0/3] Fix TLB invalidate issues with Broadwell

i915 selftest hangcheck is causing the i915 driver timeouts, as reported by Intel CI bot: http://gfx-ci.fi.intel.com/cibuglog-ng/issuefilterassoc/24297?query_key=42a999f48fa6ecce068bc8126c069be7c31153b4 When such test runs, the only output is: [ 68.811639] i915: Performing live selftes

[Intel-gfx] [PATCH v2 1/3] drm/i915/gt: Ignore TLB invalidations on idle engines

From: Chris Wilson As an extension of the current skip TLB invalidations, check if the device is powered down prior to any engine activity, as, on such cases, all the TLBs were already invalidated, so an explicit TLB invalidation is not needed. This becomes more significant with GuC, as it can o

[Intel-gfx] [PATCH v2 2/3] drm/i915/gt: Serialize GRDOM access between multiple engine resets

From: Chris Wilson Don't allow two engines to be reset in parallel, as they would both try to select a reset bit (and send requests to common registers) and wait on that register, at the same time. Serialize control of the reset requests/acks using the uncore->lock, which will also ensure that no

[Intel-gfx] [PATCH v2 3/3] drm/i915/gt: Serialize TLB invalidates with GT resets

From: Chris Wilson Avoid trying to invalidate the TLB in the middle of performing an engine reset, as this may result in the reset timing out. Currently, the TLB invalidate is only serialised by its own mutex, forgoing the uncore lock, but we can take the uncore->lock as well to serialise the mmi

Re: [Intel-gfx] [PATCH 5/6] drm/i915/gt: Serialize GRDOM access between multiple engine resets

On Tue, 28 Jun 2022 16:49:23 +0100 Tvrtko Ursulin wrote: >.. which for me means a different patch 1, followed by patch 6 (moved > to be patch 2) would be ideal stable material. > > Then we have the current patch 2 which is open/unknown (to me at least). > > And the rest seem like optimisations

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/2] iosys-map: Add per-word read

Issue is related to https://gitlab.freedesktop.org/drm/intel/-/issues/6310 All tests - general protection fault, probably for non-canonical address 0x6b6b6b6b6b6b7c6b Since we have clean BAT results from Rev 2, I haven’t re-reported. Lakshmi. From: Lucas De Marchi Sent: Tuesday, June 28, 2022

Re: [Intel-gfx] [PATCH v4 13/14] mei: debugfs: add pxp mode to devstate in debugfs

On Wed, Jun 29, 2022 at 02:29:12PM +0300, Alexander Usyskin wrote: > From: Tomas Winkler > > Add pxp mode devstate to debugfs to monitor > pxp state machine progress. During debug > it is important to understand in what state > the pxp handshake is. You have 72 columns for changelog text, as you

Re: [Intel-gfx] [PATCH v4 13/14] mei: debugfs: add pxp mode to devstate in debugfs

On Wed, Jun 29, 2022 at 02:29:12PM +0300, Alexander Usyskin wrote: > From: Tomas Winkler > > Add pxp mode devstate to debugfs to monitor > pxp state machine progress. During debug > it is important to understand in what state > the pxp handshake is. > > CC: Vitaly Lubart > Signed-off-by: Tomas

Re: [Intel-gfx] [PATCH v4 00/14] GSC support for XeHP SDV and DG2 platforms

On Wed, Jun 29, 2022 at 02:28:59PM +0300, Alexander Usyskin wrote: > Add GSC support for XeHP SDV and DG2 platforms. > > The series includes changes for the mei driver: > - add ability to use polling instead of interrupts > - add ability to use extended timeouts > - setup extended operational memo

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Drain freed object after suspend display (rev2)

== Series Details == Series: drm/i915: Drain freed object after suspend display (rev2) URL : https://patchwork.freedesktop.org/series/105779/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11825 -> Patchwork_105779v2 Summary

Re: [Intel-gfx] [PATCH 5/6] drm/i915/gt: Serialize GRDOM access between multiple engine resets

On 29/06/2022 16:30, Mauro Carvalho Chehab wrote: On Tue, 28 Jun 2022 16:49:23 +0100 Tvrtko Ursulin wrote: .. which for me means a different patch 1, followed by patch 6 (moved to be patch 2) would be ideal stable material. Then we have the current patch 2 which is open/unknown (to me at le

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Fix TLB invalidate issues with Broadwell (rev2)

== Series Details == Series: Fix TLB invalidate issues with Broadwell (rev2) URL : https://patchwork.freedesktop.org/series/105167/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Fix TLB invalidate issues with Broadwell (rev2)

== Series Details == Series: Fix TLB invalidate issues with Broadwell (rev2) URL : https://patchwork.freedesktop.org/series/105167/ State : warning == Summary == Error: dim checkpatch failed b88ec824a39f drm/i915/gt: Ignore TLB invalidations on idle engines -:132: CHECK:MACRO_ARG_REUSE: Macro

Re: [Intel-gfx] [PATCH v3 11/13] drm/i915/ttm: handle blitter failure on DG2

Hi, Matthew, On 6/29/22 14:14, Matthew Auld wrote: If the move or clear operation somehow fails, and the memory underneath is not cleared, like when moving to lmem, then we currently fallback to memcpy or memset. However with small-BAR systems this fallback might no longer be possible. For now w

Re: [Intel-gfx] [PATCH v3 13/13] drm/i915: turn on small BAR support

On 6/29/22 14:14, Matthew Auld wrote: With the uAPI in place we should now have enough in place to ensure a working system on small BAR configurations. v2: (Nirmoy & Thomas): - s/full BAR/Resizable BAR/ which is hopefully more easily understood by users. Signed-off-by: Matthew Auld C

Re: [Intel-gfx] [PATCH v3 09/13] drm/i915/selftests: skip the mman tests for stolen

On 6/29/22 14:14, Matthew Auld wrote: It's not supported, and just skips later anyway. With small-BAR things get more complicated since all of stolen is likely not even CPU accessible, hence not passing I915_BO_ALLOC_GPU_ONLY just results in the object create failing. Signed-off-by: Matthew Au

Re: [Intel-gfx] [PATCH v3 11/13] drm/i915/ttm: handle blitter failure on DG2

On 29/06/2022 17:11, Thomas Hellström wrote: Hi, Matthew, On 6/29/22 14:14, Matthew Auld wrote: If the move or clear operation somehow fails, and the memory underneath is not cleared, like when moving to lmem, then we currently fallback to memcpy or memset. However with small-BAR systems this f

[Intel-gfx] ✓ Fi.CI.BAT: success for Fix TLB invalidate issues with Broadwell (rev2)

== Series Details == Series: Fix TLB invalidate issues with Broadwell (rev2) URL : https://patchwork.freedesktop.org/series/105167/ State : success == Summary == CI Bug Log - changes from CI_DRM_11825 -> Patchwork_105167v2 Summary ---

Re: [Intel-gfx] [PATCH v3 09/13] drm/i915/selftests: skip the mman tests for stolen

On 29/06/2022 17:22, Thomas Hellström wrote: On 6/29/22 14:14, Matthew Auld wrote: It's not supported, and just skips later anyway. With small-BAR things get more complicated since all of stolen is likely not even CPU accessible, hence not passing I915_BO_ALLOC_GPU_ONLY just results in the obje

Re: [Intel-gfx] [PATCH v3 11/13] drm/i915/ttm: handle blitter failure on DG2

On 6/29/22 18:28, Matthew Auld wrote: On 29/06/2022 17:11, Thomas Hellström wrote: Hi, Matthew, On 6/29/22 14:14, Matthew Auld wrote: If the move or clear operation somehow fails, and the memory underneath is not cleared, like when moving to lmem, then we currently fallback to memcpy or mems

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/guc: ADL-N should use the same GuC FW as ADL-S (rev3)

== Series Details == Series: drm/i915/guc: ADL-N should use the same GuC FW as ADL-S (rev3) URL : https://patchwork.freedesktop.org/series/105444/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11822_full -> Patchwork_105444v3_full ==

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Drain freed object after suspend display (rev3)

== Series Details == Series: drm/i915: Drain freed object after suspend display (rev3) URL : https://patchwork.freedesktop.org/series/105779/ State : success == Summary == CI Bug Log - changes from CI_DRM_11825 -> Patchwork_105779v3 Summary

[Intel-gfx] [CI v4 01/13] drm/doc: add rfc section for small BAR uapi

Add an entry for the new uapi needed for small BAR on DG2+. v2: - Some spelling fixes and other small tweaks. (Akeem & Thomas) - Rework error capture interactions, including no longer needing NEEDS_CPU_ACCESS for objects marked for capture. (Thomas) - Add probed_cpu_visible_size. (Lionel

[Intel-gfx] [CI v4 04/13] drm/i915: remove intel_memory_region avail

No longer used. Signed-off-by: Matthew Auld Cc: Thomas Hellström Cc: Lionel Landwerlin Cc: Tvrtko Ursulin Cc: Jon Bloomfield Cc: Daniel Vetter Cc: Jordan Justen Cc: Kenneth Graunke Cc: Akeem G Abodunrin Reviewed-by: Thomas Hellström --- drivers/gpu/drm/i915/intel_memory_region.c | 4 +--

[Intel-gfx] [CI v4 05/13] drm/i915/uapi: apply ALLOC_GPU_ONLY by default

On small BAR configurations, when dealing with I915_MEMORY_CLASS_DEVICE allocations, we assume that by default, all userspace allocations should be placed in the non-CPU visible portion. Note that dumb buffers are not included here, since these are not "GPU accelerated" and likely need CPU access.

[Intel-gfx] [CI v4 06/13] drm/i915/uapi: add NEEDS_CPU_ACCESS hint

If set, force the allocation to be placed in the mappable portion of I915_MEMORY_CLASS_DEVICE. One big restriction here is that system memory (i.e I915_MEMORY_CLASS_SYSTEM) must be given as a potential placement for the object, that way we can always spill the object into system memory if we can't

[Intel-gfx] [CI v4 02/13] drm/i915/uapi: add probed_cpu_visible_size

Userspace wants to know the size of CPU visible portion of device local-memory, and on small BAR devices the probed_size is no longer enough. In Vulkan, for example, it would like to know the size in bytes for CPU visible VkMemoryHeap. We already track the io_size for each region, so plumb that thr

[Intel-gfx] [CI v4 07/13] drm/i915/error: skip non-mappable pages

Skip capturing any lmem pages that can't be copied using the CPU. This in now only best effort on platforms that have small BAR. Testcase: igt@gem-exec-capture@capture-invisible Signed-off-by: Matthew Auld Cc: Thomas Hellström Cc: Lionel Landwerlin Cc: Tvrtko Ursulin Cc: Jon Bloomfield Cc: Da

[Intel-gfx] [CI v4 13/13] drm/i915: turn on small BAR support

With the uAPI in place we should now have enough in place to ensure a working system on small BAR configurations. v2: (Nirmoy & Thomas): - s/full BAR/Resizable BAR/ which is hopefully more easily understood by users. Signed-off-by: Matthew Auld Cc: Thomas Hellström Cc: Lionel Landwerlin

[Intel-gfx] [CI v4 10/13] drm/i915/selftests: ensure we reserve a fence slot

We should always be explicit and allocate a fence slot before adding a new fence. Signed-off-by: Matthew Auld Cc: Thomas Hellström Cc: Lionel Landwerlin Cc: Tvrtko Ursulin Cc: Jon Bloomfield Cc: Daniel Vetter Cc: Jordan Justen Cc: Kenneth Graunke Cc: Akeem G Abodunrin Reviewed-by: Thomas

[Intel-gfx] [CI v4 11/13] drm/i915/ttm: handle blitter failure on DG2

If the move or clear operation somehow fails, and the memory underneath is not cleared, like when moving to lmem, then we currently fallback to memcpy or memset. However with small-BAR systems this fallback might no longer be possible. For now we use the set_wedged sledgehammer if we ever encounter

[Intel-gfx] [CI v4 09/13] drm/i915/selftests: skip the mman tests for stolen

It's not supported, and just skips later anyway. With small-BAR things get more complicated since all of stolen is likely not even CPU accessible, hence not passing I915_BO_ALLOC_GPU_ONLY just results in the object create failing. Signed-off-by: Matthew Auld Cc: Thomas Hellström Cc: Lionel Landw

[Intel-gfx] [CI v4 03/13] drm/i915/uapi: expose the avail tracking

Vulkan would like to have a rough measure of how much device memory can in theory be allocated. Also add unallocated_cpu_visible_size to track the visible portion, in case the device is using small BAR. Also tweak the locking so we nice consistent values for both the mm->avail and the visible track

[Intel-gfx] [CI v4 08/13] drm/i915/uapi: tweak error capture on recoverable contexts

A non-recoverable context must be used if the user wants proper error capture on discrete platforms. In the future the kernel may want to blit the contents of some objects when later doing the capture stage. Also extend to newer integrated platforms. v2(Thomas): - Also extend to newer integrated

[Intel-gfx] [CI v4 12/13] drm/i915/ttm: disallow CPU fallback mode for ccs pages

Falling back to memcpy/memset shouldn't be allowed if we know we have CCS state to manage using the blitter. Otherwise we are potentially leaving the aux CCS state in an unknown state, which smells like an info leak. Fixes: 48760ffe923a ("drm/i915/gt: Clear compress metadata for Flat-ccs objects"

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