From: Matt Atwood
Newer platforms have DSS that aren't necessarily available for both
geometry and compute, two queries will need to exist. This introduces
the first, when passing a valid engine class and engine instance in the
flags returns a topology describing geometry.
Based on past discussi
Run CI for these two patches for:
https://gitlab.freedesktop.org/drm/intel/-/issues/5701
Nirmoy Das (1):
ALSA: hda: handle UAF at probe error
Takashi Iwai (1):
ALSA: core: Add snd_card_free_on_error() helper
include/sound/core.h | 1 +
sound/core/init.c | 28 +
From: Takashi Iwai
This is a small helper function to handle the error path more easily
when an error happens during the probe for the device with the
device-managed card. Since devres releases in the reverser order of
the creations, usually snd_card_free() gets called at the last in the
probe e
Call snd_card_free_on_error() on probe error instead of
calling snd_card_free() which should handle devres call orders.
Issues: https://gitlab.freedesktop.org/drm/intel/-/issues/5701
Fixes: e8ad415b7a55 ("ALSA: core: Add managed card creation")
Signed-off-by: Nirmoy Das
---
sound/pci/hda/hda_int
Call snd_card_free_on_error() on probe error instead of
calling snd_card_free() which should handle devres call orders.
Issues: https://gitlab.freedesktop.org/drm/intel/-/issues/5701
Fixes: e8ad415b7a55 ("ALSA: core: Add managed card creation")
Signed-off-by: Nirmoy Das
---
sound/pci/hda/hda_int
== Series Details ==
Series: series starting with [v2,1/1] i915/gem: drop wbinvd_on_all_cpus usage
URL : https://patchwork.freedesktop.org/series/102708/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11501 -> Patchwork_102708v1
=
== Series Details ==
Series: series starting with [v3,1/2] drm/i915/display/psr: Unset
enable_psr2_sel_fetch if other checks in intel_psr2_config_valid() fails
URL : https://patchwork.freedesktop.org/series/102704/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11500_full -> P
== Series Details ==
Series: series starting with [v3,1/2] drm/dp: Factor out a function to probe a
DPCD address (rev3)
URL : https://patchwork.freedesktop.org/series/102428/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11482_full -> Patchwork_102428v3_full
=
On Thu, Apr 14, 2022 at 07:36:26PM +0530, Tejas Upadhyay wrote:
> From: Matt Atwood
>
> Adding initial PCI ids for RPL-P.
> RPL-P behaves identically to ADL-P from i915's point of view.
>
> Bspec: 55376
> Signed-off-by: Matt Atwood
> Signed-off-by: Madhumitha Tolakanahalli Pradeep
>
> Signed-
Reviewed-by: Lyude Paul
On Wed, 2022-04-13 at 11:28 +0300, Jouni Högander wrote:
> We have now seen panel (XMG Core 15 e21 laptop) advertizing support
> for Intel proprietary eDP backlight control via DPCD registers, but
> actually working only with legacy pwm control.
>
> This patch adds panel
HI,
The result here says SUCCESS but closer look shows that it never ran on any
DG2. Wanted to know if something went wrong at the system side and if it needs
to be revived. The patch is simply loading DMC and shouldn’t cause the system
to not boot up at all.
Any info in this regard will be v
== Series Details ==
Series: drm/edid: CEA data block iterators, and more (rev2)
URL : https://patchwork.freedesktop.org/series/102703/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11500_full -> Patchwork_102703v2_full
Sum
Move the list of platform specific power domain -> power well
definitions to intel_display_power_map.c. While at it group the
platforms' power domain macros with the corresponding power well lists
and keep all the power domain lists in the same order (matching the enum
order).
No functional change
The for_each_power_well() macros are only used in intel_display_power.c
and intel_display_power_well.c, so unexport them.
Signed-off-by: Imre Deak
Reviewed-by: Jouni Högander
---
.../drm/i915/display/intel_display_power.c| 8
.../drm/i915/display/intel_display_power.h| 20
Save some space by grouping the HSW power well descriptor flags along
with other flags in one bitfield.
This change also lets simplifying the definition of power well
descriptors sharing the same flags in an upcoming patch.
Signed-off-by: Imre Deak
Reviewed-by: Jouni Högander
---
.../i915/disp
The DG2 fixed delay duration is always 600usec, so save some space in
the power well descriptors by converting the parameter to a flag. While
at it also use a bitfield for both the always_on and fixed_enable_delay
flag.
This change also lets simplifying the definiton of power wells sharing
the sam
Move the implementation of platform specific power well hooks to
intel_display_power_well.c, to reduce the clutter in
intel_display_power.c.
The locking of all the power domain/power well state is handled in the
power domain functions in intel_display_power.c using
i915_power_domains::lock. This p
Use the shortest descriptive name for all power wells for simplicity and
to use the same name for the same type of power wells on multiple
platforms.
Signed-off-by: Imre Deak
Reviewed-by: Jouni Högander
---
.../i915/display/intel_display_power_map.c| 254 +-
1 file changed,
Make all power domain names end with the pipe/port instance for
consistency.
No functional changes.
Signed-off-by: Imre Deak
Reviewed-by: Jouni Högander
---
drivers/gpu/drm/i915/display/icl_dsi.c| 8 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/disp
To remove the aliasing of the power domain enum values in a follow-up
patch in this patchset (requiring a bigger mask) and allow for defining
additional power domains in the future (at least some upcoming TypeC
changes requires this) convert the u64 i915_power_well_desc::domains
mask to a bitmap.
The next patch converts the i915_power_well_desc::domain mask from a u64
mask to a bitmap. I didn't find a reasonably simple way to initialize
bitmaps statically, so prepare for the next patch here by converting the
masks to an array of domain enums and initing the masks from these
arrays during mo
All the port specific AUX/DDI_IO power wells share the same power well
ops struct and flags, so we can save some space and simplify the
definition of these by listing for all such power wells only the params
specific to them (name, domains, power well register index, id). Move
these params to a new
Simplify the definition of DG1 power wells by reusing the identical
RKL DDI/AUX descriptors.
This reorders the DG1 DDI/AUX vs. PW4/5 power wells, but this shouldn't
make a difference (it is the order on RKL and the DDI/AUX power wells
don't have a dependency on PW4/5).
Signed-off-by: Imre Deak
R
Atm the port -> DDI and AUX power domain mapping is specified by relying
on the aliasing of the platform specific intel_display_power_domain enum
values. For instance D12+ platforms refer to the 'D' port and power
domain instances, which doesn't match the bspec terminology, on these
platforms the c
The spec calls the ICL TBT AUX power well instances TBT1-4 (similarly to
all later platforms), align the power domain names with the spec.
Signed-off-by: Imre Deak
Reviewed-by: Jouni Högander
---
.../gpu/drm/i915/display/intel_display_power.c | 10 +-
.../gpu/drm/i915/display/intel_di
Some power wells - like always-on and skl+/icl+ PW_1 - with the same
name, domain list, flags, ops are used by multiple platforms, so allow
platforms to reuse the descriptors of such power wells.
This change also lets the follow up patches to simplify the DG1/RKL
power well definitions, and remove
The DDI and AUX domain -> power well mappings are identical for a few
platforms/power well instances, reuse the mappings of earlier platforms
for these removing the duplicate mapping of new platforms.
Signed-off-by: Imre Deak
Reviewed-by: Jouni Högander
---
.../i915/display/intel_display_power_
The spec calls the XELPD_D/E ports just D/E, the platform prefix in the
domain names was only needed by the port->domain mapping relying on
matching enum values for the whole port/domain range (and the
corresponding aliasing between the platform specific domain enums).
Since a previous patch we can
Aliasing the intel_display_power_domain enum values was required because
of the u64 power domain mask size limit. This makes the dmesg/debugfs
printouts of the domain names somewhat unclear, for instance domain
names for port D are shown on D12+ platforms where the corresponding
port is called TC1.
Instead of the skip_mask special casing of the ADL-S power well
descriptors, add a power well descriptor list for ADL-S as well reusing
the TGL descriptors, w/o the TC-cold power well. ADL-S doesn't have
TypeC PHYs, so a better way would be having ADL-S specific AUX
descriptors, but I left changing
On Wed, Apr 13, 2022 at 05:39:27PM -0400, Rodrigo Vivi wrote:
> Bit 0: Currently bit used by i915. Ideally only i915 touches it
>in a Linux stack.
>
> Bits 1 and 2: A while ago we were using Bit 1 for i915 and bit 2
> for the user space, until commit 7130630323c5 ("drm/
Re-reported.
-Original Message-
From: Deak, Imre
Sent: Thursday, April 14, 2022 11:33 AM
To: intel-gfx@lists.freedesktop.org; Nikula, Jani ;
Almahallawy, Khaled
Cc: Vudum, Lakshminarayana
Subject: Re: ✗ Fi.CI.IGT: failure for series starting with [v3,1/2] drm/dp:
Factor out a functio
== Series Details ==
Series: Drop wbinvd_on_all_cpus usage
URL : https://patchwork.freedesktop.org/series/102710/
State : warning
== Summary ==
Error: dim checkpatch failed
e1e1903177c2 i915/gem: drop wbinvd_on_all_cpus usage
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit descri
At present i915 does not fetch busyness information from GuC, resulting in
incorrect busyness values in fdinfo. Because engine information is coupled
with busyness in fdinfo, skip showing client engine information in fdinfo
with GuC submission till fetching busyness is supported in the i915 GuC
sub
On Thu, 2022-04-14 at 14:14 -0700, Matt Roper wrote:
> On Wed, Apr 13, 2022 at 05:39:27PM -0400, Rodrigo Vivi wrote:
> > Bit 0: Currently bit used by i915. Ideally only i915 touches it
> > in a Linux stack.
> >
> > Bits 1 and 2: A while ago we were using Bit 1 for i915 and bit 2
> >
== Series Details ==
Series: Drop wbinvd_on_all_cpus usage
URL : https://patchwork.freedesktop.org/series/102710/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11502 -> Patchwork_102710v1
Summary
---
**SUCCESS**
N
== Series Details ==
Series: drm/i915/dmc: Load DMC on DG2 (rev4)
URL : https://patchwork.freedesktop.org/series/102630/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11500_full -> Patchwork_102630v4_full
Summary
---
On Thu, Apr 14, 2022 at 03:58:02PM +, Sean Paul wrote:
> On Tue, Apr 12, 2022 at 09:25:59AM -0400, Rodrigo Vivi wrote:
> > On Mon, Apr 11, 2022 at 08:47:32PM +, Sean Paul wrote:
> > > From: Sean Paul
> > >
> > > This patch updates the connector's property value in 2 cases which were
> > >
== Series Details ==
Series: series starting with [CI,1/4] drm/i915/doc: Convert
drm_i915_query_topology_info comment to kerneldoc
URL : https://patchwork.freedesktop.org/series/102713/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit w
On Thu, 14 Apr 2022 06:28:57 -0700, Jani Nikula wrote:
>
> On Wed, 13 Apr 2022, Ashutosh Dixit wrote:
> > Each gt contains an independent instance of pcode. Extend pcode functions
> > to interface with pcode on different gt's. Previous (GT0) pcode read/write
> > interfaces are preserved.
>
> The b
== Series Details ==
Series: drm/i915: Don't show client busyness in fdinfo with GuC submission
(rev2)
URL : https://patchwork.freedesktop.org/series/102676/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11500_full -> Patchwork_102676v2_full
==
== Series Details ==
Series: series starting with [CI,1/4] drm/i915/doc: Convert
drm_i915_query_topology_info comment to kerneldoc
URL : https://patchwork.freedesktop.org/series/102713/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11503 -> Patchwork_102713v1
== Series Details ==
Series: ALSA: hda: handle UAF at probe error
URL : https://patchwork.freedesktop.org/series/102714/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i2c/tda998x_drv.c:1
== Series Details ==
Series: ALSA: hda: handle UAF at probe error
URL : https://patchwork.freedesktop.org/series/102714/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11503 -> Patchwork_102714v1
Summary
---
**FAILURE
== Series Details ==
Series: series starting with [CI,01/18] drm/i915: Move per-platform power well
hooks to intel_display_power_well.c
URL : https://patchwork.freedesktop.org/series/102719/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each com
== Series Details ==
Series: series starting with [CI,01/18] drm/i915: Move per-platform power well
hooks to intel_display_power_well.c
URL : https://patchwork.freedesktop.org/series/102719/
State : warning
== Summary ==
Error: dim checkpatch failed
c5b4984a0598 drm/i915: Move per-platform po
== Series Details ==
Series: series starting with [CI,01/18] drm/i915: Move per-platform power well
hooks to intel_display_power_well.c
URL : https://patchwork.freedesktop.org/series/102719/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11503 -> Patchwork_102719v1
===
== Series Details ==
Series: drm/i915: Don't show client busyness in fdinfo with GuC submission
(rev3)
URL : https://patchwork.freedesktop.org/series/102676/
State : warning
== Summary ==
Error: dim checkpatch failed
0899841de83a drm/i915: Don't show engine information in fdinfo with GuC
sub
On 4/13/2022 12:27, Umesh Nerlige Ramappa wrote:
From: Tilak Tangudu
Prior to doing a reset, SW must ensure command streamer is stopped,
as a workaround, to eliminate a race condition in GPM flow.
Setting both the ring stop and prefetch disable bits, will cause the
command streamer to halt.
v2
On 4/14/2022 2:24 PM, Ashutosh Dixit wrote:
At present i915 does not fetch busyness information from GuC, resulting in
incorrect busyness values in fdinfo. Because engine information is coupled
with busyness in fdinfo, skip showing client engine information in fdinfo
with GuC submission till f
On Tue, Apr 12, 2022 at 03:59:55PM -0700, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> The latest GuC firmware drops the context descriptor pool in favour of
> passing all creation data in the create H2G. It also greatly simplifies
> the work queue and removes the process descriptor
== Series Details ==
Series: series starting with [v2,1/1] i915/gem: drop wbinvd_on_all_cpus usage
URL : https://patchwork.freedesktop.org/series/102708/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11501_full -> Patchwork_102708v1_full
===
On 4/13/2022 12:27, Umesh Nerlige Ramappa wrote:
From: Vinay Belgaumkar
Enable GuC Wa to reset RCS/CCS before it goes into RC6.
v2: Comments from Matt R.
Signed-off-by: Vinay Belgaumkar
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 5 +
drivers/gpu/d
== Series Details ==
Series: drm/i915: Don't show client busyness in fdinfo with GuC submission
(rev3)
URL : https://patchwork.freedesktop.org/series/102676/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11503 -> Patchwork_102676v3
On 4/13/2022 12:27, Umesh Nerlige Ramappa wrote:
From: Matthew Brost
There is bug in DG2 where if the CCS contexts switches out while the RCS
is running it can cause memory corruption. To workaround this add an
atomic to a memory address with a value 1 and semaphore wait to the same
address for
On 4/13/2022 12:27, Umesh Nerlige Ramappa wrote:
From: John Harrison
The above two workaronuds regarding context isolation are implemented
workaronuds -> workarounds
by GuC. The KMD just needs to enable them.
v2: Use dg2 stepping for ctx isolation WA (Umesh)
v3: Rebase (Umesh)
v4: Fix WA co
At present i915 does not fetch busyness information from GuC, resulting in
incorrect busyness values in fdinfo. Because engine information is coupled
with busyness in fdinfo, skip showing client engine information in fdinfo
with GuC submission till fetching busyness is supported in the i915 GuC
sub
On Thu, Apr 14, 2022 at 05:22:47PM -0700, John Harrison wrote:
On 4/13/2022 12:27, Umesh Nerlige Ramappa wrote:
From: John Harrison
The above two workaronuds regarding context isolation are implemented
workaronuds -> workarounds
by GuC. The KMD just needs to enable them.
v2: Use dg2 steppi
== Series Details ==
Series: drm/i915: Don't show client busyness in fdinfo with GuC submission
(rev4)
URL : https://patchwork.freedesktop.org/series/102676/
State : warning
== Summary ==
Error: dim checkpatch failed
f88e1e858cef drm/i915: Don't show engine information in fdinfo with GuC
sub
== Series Details ==
Series: drm/i915: Don't show client busyness in fdinfo with GuC submission
(rev4)
URL : https://patchwork.freedesktop.org/series/102676/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11504 -> Patchwork_102676v4
> From: Jason Gunthorpe
> Sent: Thursday, April 14, 2022 10:22 PM
>
> On Thu, Apr 14, 2022 at 09:51:49AM -0400, Matthew Rosato wrote:
> > On 4/12/22 11:53 AM, Jason Gunthorpe wrote:
> > > When the open_device() op is called the container_users is incremented
> and
> > > held incremented until clo
== Series Details ==
Series: Drop wbinvd_on_all_cpus usage
URL : https://patchwork.freedesktop.org/series/102710/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11502_full -> Patchwork_102710v1_full
Summary
---
**SUCC
On Wed, Apr 13, 2022 at 12:27:29PM -0700, Umesh Nerlige Ramappa wrote:
> From: Matthew Brost
>
> There is bug in DG2 where if the CCS contexts switches out while the RCS
> is running it can cause memory corruption. To workaround this add an
> atomic to a memory address with a value 1 and semaphor
On Tue, Apr 12, 2022 at 05:57:07PM -0700, Anusha Srivatsa wrote:
Add Support for DC states on Dg2.
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
Failure in CI seems unrelated. Although it's unfortunate the DG2
couldn't get tested with this patch.
were you able to test this l
On Thu, Apr 14, 2022 at 08:54:49PM +, Anusha Srivatsa wrote:
HI,
The result here says SUCCESS but closer look shows that it never ran on any
DG2. Wanted to know if something went wrong at the system side and if it needs
to be revived. The patch is simply loading DMC and shouldn’t cause th
== Series Details ==
Series: series starting with [CI,1/4] drm/i915/doc: Convert
drm_i915_query_topology_info comment to kerneldoc
URL : https://patchwork.freedesktop.org/series/102713/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11503_full -> Patchwork_102713v1_full
==
== Series Details ==
Series: series starting with [CI,01/18] drm/i915: Move per-platform power well
hooks to intel_display_power_well.c
URL : https://patchwork.freedesktop.org/series/102719/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11503_full -> Patchwork_102719v1_full
=
On Thu, Apr 14, 2022 at 09:37:14PM -0700, Lucas De Marchi wrote:
On Thu, Apr 14, 2022 at 08:54:49PM +, Anusha Srivatsa wrote:
HI,
The result here says SUCCESS but closer look shows that it never ran on any
DG2. Wanted to know if something went wrong at the system side and if it needs
to
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