[Intel-gfx] [PATCH] drm/i915/dp: make DSC usage logging actually useful

Debug log when DSC is going to be used, and why, instead of unconditionally logging the rarely used debug option setting, which might not have any bearing on whether DSC is going to be used or not. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dp.c | 19 --- 1

Re: [Intel-gfx] [PATCH] drm/i915/gt: fix i915_reg_t initialization

On Mon, 21 Mar 2022, Lucas De Marchi wrote: > On Mon, Mar 21, 2022 at 03:59:55PM +0200, Jani Nikula wrote: >>The initialization is there only to silence the compiler, but use the >>correct initializer for i915_reg_t. >> >>Cc: Lucas De Marchi >>Signed-off-by: Jani Nikula > > > Reviewed-by: Lucas

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm: round_up the size to the alignment value

== Series Details == Series: drm: round_up the size to the alignment value URL : https://patchwork.freedesktop.org/series/101950/ State : warning == Summary == $ dim checkpatch origin/drm-tip e363212181a6 drm: round_up the size to the alignment value -:47: CHECK:LINE_SPACING: Please don't use

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm: round_up the size to the alignment value

== Series Details == Series: drm: round_up the size to the alignment value URL : https://patchwork.freedesktop.org/series/101950/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not found ./

[Intel-gfx] [PATCH 1/2] drm/i915/audio: unify audio codec enable/disable debug logging

The audio codec enable/disable debug logging is spread around in callers and the platform specific hooks. Put them all together in one place on both the enable and disable paths. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/g4x_dp.c | 7 +--- drivers/gpu/drm/i915/display/g4x

[Intel-gfx] [PATCH 2/2] drm/i915/audio: move has_audio checks to within codec enable/disable

Reduce duplication. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/g4x_dp.c | 7 ++--- drivers/gpu/drm/i915/display/g4x_hdmi.c | 33 +++-- drivers/gpu/drm/i915/display/intel_audio.c | 6 drivers/gpu/drm/i915/display/intel_ddi.c| 14 +++-- dr

Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/gt: Split intel-gtt functions by arch

On Tue, Mar 29, 2022 at 04:35:17PM -0700, Casey Bowman wrote: > @@ -1208,11 +576,11 @@ static int ggtt_probe_hw(struct i915_ggtt *ggtt, > struct intel_gt *gt) > dma_resv_init(&ggtt->vm._resv); > > if (GRAPHICS_VER(i915) <= 5) > - ret = i915_gmch_probe(ggtt); > +

Re: [Intel-gfx] [PATCH] drm/i915/display/: Refactor hsw_crtc_enable for bigjoiner cleanup

On Tue, Mar 29, 2022 at 05:00:39PM -0700, Navare, Manasi wrote: > Hi Ville, > > I was looking at your suggestion of extracting the per pipe stuff out. > Currently in hsw_crtc_enable: the Only non per pipe stuff which gets enabled > for the encoders is : > encoder specific is pre_pll_enable(), ena

Re: [Intel-gfx] [PATCH v3 1/2] drm/i915/gt: Split intel-gtt functions by arch

On 30/03/2022 00:58, Casey Bowman wrote: Some functions defined in the intel-gtt module are used in several areas, but is only supported on x86 platforms. By separating these calls and their static underlying functions to another area, we are able to compile out these functions for non-x86 bui

[Intel-gfx] ✓ Fi.CI.BAT: success for drm: round_up the size to the alignment value

== Series Details == Series: drm: round_up the size to the alignment value URL : https://patchwork.freedesktop.org/series/101950/ State : success == Summary == CI Bug Log - changes from CI_DRM_11416 -> Patchwork_22730 Summary --- **S

Re: [Intel-gfx] [PATCH v3 1/2] drm/i915/gt: Split intel-gtt functions by arch

On Tue, 29 Mar 2022, Casey Bowman wrote: > +/* Stubs for non-x86 platforms */ > +#else > +static inline void intel_gt_gmch_gen5_chipset_flush(struct intel_gt *gt) > +{ > +} > +static inline int intel_gt_gmch_gen5_probe(struct i915_ggtt *ggtt) > +{ > + /* No HW should be probed for this case ye

Re: [Intel-gfx] [PATCH v3 1/2] drm/i915/gt: Split intel-gtt functions by arch

On Wed, 30 Mar 2022, Tvrtko Ursulin wrote: > On 30/03/2022 00:58, Casey Bowman wrote: >> Some functions defined in the intel-gtt module are used in several >> areas, but is only supported on x86 platforms. >> >> By separating these calls and their static underlying functions to >> another area, w

Re: [Intel-gfx] [PATCH v4 1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL

On Tue, Mar 29, 2022 at 03:30:59PM -0700, José Roberto de Souza wrote: > MBUS_DBOX_B2B_TRANSACTIONS_MAX, MBUS_DBOX_B2B_TRANSACTIONS_DELAY and > MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN were being programmed with > zeros while specification has different default values for this > registers in display

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/dp: make DSC usage logging actually useful

== Series Details == Series: drm/i915/dp: make DSC usage logging actually useful URL : https://patchwork.freedesktop.org/series/101952/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not fo

Re: [Intel-gfx] [PATCH v4 2/4] drm/i915/display/adlp: Adjust MBUS DBOX BW and B credits

On Tue, Mar 29, 2022 at 03:31:00PM -0700, José Roberto de Souza wrote: > From: Caz Yokoyama > > Alderlake-P has different MBUS DBOX BW and B credits than other > platforms, so here setting it properly. Hmm. No explicit table for these so I guess we're going by the register defaults here. Review

Re: [Intel-gfx] [PATCH v4 4/4] drm/i915/display/adlp: Fix programing of PIPE_MBUS_DBOX_CTL

On Tue, Mar 29, 2022 at 03:31:02PM -0700, José Roberto de Souza wrote: > PIPE_MBUS_DBOX_CTL was only being programmed when a pipe is being > enabled but that could potentially cause issues as it could have > mismatching values while pipes are being enabled. > > So here moving the PIPE_MBUS_DBOX_CT

Re: [Intel-gfx] [PATCH] drm/i915/dp: make DSC usage logging actually useful

On Wed, Mar 30, 2022 at 12:30:19PM +0300, Jani Nikula wrote: > Debug log when DSC is going to be used, and why, instead of > unconditionally logging the rarely used debug option setting, which > might not have any bearing on whether DSC is going to be used or not. > > Signed-off-by: Jani Nikula >

Re: [Intel-gfx] [PATCH 1/2] drm/i915/audio: unify audio codec enable/disable debug logging

On Wed, Mar 30, 2022 at 12:41:08PM +0300, Jani Nikula wrote: > The audio codec enable/disable debug logging is spread around in callers > and the platform specific hooks. Put them all together in one place on > both the enable and disable paths. > > Signed-off-by: Jani Nikula > --- > drivers/gpu

Re: [Intel-gfx] [PATCH 2/2] drm/i915/audio: move has_audio checks to within codec enable/disable

On Wed, Mar 30, 2022 at 12:41:09PM +0300, Jani Nikula wrote: > Reduce duplication. > > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/g4x_dp.c | 7 ++--- > drivers/gpu/drm/i915/display/g4x_hdmi.c | 33 +++-- > drivers/gpu/drm/i915/display/intel_audio.c

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dp: make DSC usage logging actually useful

== Series Details == Series: drm/i915/dp: make DSC usage logging actually useful URL : https://patchwork.freedesktop.org/series/101952/ State : success == Summary == CI Bug Log - changes from CI_DRM_11416 -> Patchwork_22731 Summary ---

[Intel-gfx] [PATCH 3/3] drm/i915/dmc: split out dmc registers to a separate file

Clean up the massive i915_reg.h a bit with this isolated set of registers. v2: Remove stale comment (Lucas) Signed-off-by: Jani Nikula Reviewed-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_dmc.c | 1 + drivers/gpu/drm/i915/display/intel_dmc_regs.h | 30 +++

[Intel-gfx] [PATCH 1/3] drm/i915/dmc: abstract GPU error state dump

Only intel_dmc.c should be accessing dmc details directly. Need to add an i915_error_printf() stub for CONFIG_DRM_I915_CAPTURE_ERROR=n. v2: Add the stub (kernel test robot ) Signed-off-by: Jani Nikula Reviewed-by: Lucas De Marchi # v1 --- drivers/gpu/drm/i915/display/intel_dmc.c | 15

[Intel-gfx] [PATCH 2/3] drm/i915/dmc: hide DMC version macros

The macros are now only needed within intel_dmc.c, so move them there. Signed-off-by: Jani Nikula Reviewed-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_dmc.c | 4 drivers/gpu/drm/i915/display/intel_dmc.h | 4 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a

[Intel-gfx] ✓ Fi.CI.IGT: success for drm: round_up the size to the alignment value

== Series Details == Series: drm: round_up the size to the alignment value URL : https://patchwork.freedesktop.org/series/101950/ State : success == Summary == CI Bug Log - changes from CI_DRM_11416_full -> Patchwork_22730_full Summary

[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [1/2] drm/i915/audio: unify audio codec enable/disable debug logging

== Series Details == Series: series starting with [1/2] drm/i915/audio: unify audio codec enable/disable debug logging URL : https://patchwork.freedesktop.org/series/101953/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_drrs.c:

[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/3] drm/i915/dmc: abstract GPU error state dump

== Series Details == Series: series starting with [1/3] drm/i915/dmc: abstract GPU error state dump URL : https://patchwork.freedesktop.org/series/101954/ State : failure == Summary == Applying: drm/i915/dmc: abstract GPU error state dump Using index info to reconstruct a base tree... M

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/audio: unify audio codec enable/disable debug logging

== Series Details == Series: series starting with [1/2] drm/i915/audio: unify audio codec enable/disable debug logging URL : https://patchwork.freedesktop.org/series/101953/ State : success == Summary == CI Bug Log - changes from CI_DRM_11416 -> Patchwork_22732 ===

[Intel-gfx] [RESEND 1/3] drm/i915/dmc: abstract GPU error state dump

Only intel_dmc.c should be accessing dmc details directly. Need to add an i915_error_printf() stub for CONFIG_DRM_I915_CAPTURE_ERROR=n. v2: Add the stub (kernel test robot ) Signed-off-by: Jani Nikula Reviewed-by: Lucas De Marchi # v1 --- drivers/gpu/drm/i915/display/intel_dmc.c | 15

[Intel-gfx] [RESEND 2/3] drm/i915/dmc: hide DMC version macros

The macros are now only needed within intel_dmc.c, so move them there. Signed-off-by: Jani Nikula Reviewed-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_dmc.c | 4 drivers/gpu/drm/i915/display/intel_dmc.h | 4 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a

[Intel-gfx] [RESEND 3/3] drm/i915/dmc: split out dmc registers to a separate file

Clean up the massive i915_reg.h a bit with this isolated set of registers. v2: Remove stale comment (Lucas) Signed-off-by: Jani Nikula Reviewed-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_dmc.c | 1 + drivers/gpu/drm/i915/display/intel_dmc_regs.h | 30 +++

Re: [Intel-gfx] [RFC v2 2/2] drm/doc/rfc: VM_BIND uapi definition

On Mon, Mar 07, 2022 at 12:31:46PM -0800, Niranjana Vishwanathapura wrote: > VM_BIND und related uapi definitions > > Signed-off-by: Niranjana Vishwanathapura > --- > Documentation/gpu/rfc/i915_vm_bind.h | 176 +++ Maybe as the top level comment: The point of documenting

[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [RESEND,1/3] drm/i915/dmc: abstract GPU error state dump

== Series Details == Series: series starting with [RESEND,1/3] drm/i915/dmc: abstract GPU error state dump URL : https://patchwork.freedesktop.org/series/101957/ State : failure == Summary == Applying: drm/i915/dmc: abstract GPU error state dump Using index info to reconstruct a base tree...

Re: [Intel-gfx] [PATCH 01/12] drm/edid: use struct edid * in drm_do_get_edid()

On Tue, Mar 29, 2022 at 09:42:08PM +0300, Jani Nikula wrote: > Mixing u8 * and struct edid * is confusing, switch to the latter. > > Cc: Ville Syrjälä > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/drm_edid.c | 31 +++ > 1 file changed, 15 insertions(+), 16 del

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dp: make DSC usage logging actually useful

== Series Details == Series: drm/i915/dp: make DSC usage logging actually useful URL : https://patchwork.freedesktop.org/series/101952/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11416_full -> Patchwork_22731_full Summar

[Intel-gfx] [PATCH CI 1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL

MBUS_DBOX_B2B_TRANSACTIONS_MAX, MBUS_DBOX_B2B_TRANSACTIONS_DELAY and MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN were being programmed with zeros while specification has different default values for this registers in display 12 and newer. While at it also converting all MBUS_DBOX macros to use REG_* ma

[Intel-gfx] [PATCH CI 2/4] drm/i915/display/adlp: Adjust MBUS DBOX BW and B credits

From: Caz Yokoyama Alderlake-P has different MBUS DBOX BW and B credits than other platforms, so here setting it properly. BSpec: 49213 BSpec: 50343 Cc: Matt Roper Cc: Stanislav Lisovskiy Cc: Jani Nikula Cc: Ville Syrjälä Reviewed-by: Ville Syrjälä Signed-off-by: Caz Yokoyama Signed-off-by

[Intel-gfx] [PATCH CI 4/4] drm/i915/display/adlp: Fix programing of PIPE_MBUS_DBOX_CTL

PIPE_MBUS_DBOX_CTL was only being programmed when a pipe is being enabled but that could potentially cause issues as it could have mismatching values while pipes are being enabled. So here moving the PIPE_MBUS_DBOX_CTL programming of all pipes to be executed before the function that enables all pi

[Intel-gfx] [PATCH CI 3/4] drm/i915/display: Add HAS_MBUS_JOINING

This will make easy to extend MBUS joining support to future platforms that also supports this feature. Reviewed-by: Ville Syrjälä Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/intel_pm.c | 6 +++--- 2 files changed, 5 insertions(+), 3 del

[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [CI,1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL

== Series Details == Series: series starting with [CI,1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL URL : https://patchwork.freedesktop.org/series/101961/ State : failure == Summary == Applying: drm/i915/display/tgl+: Set default values for all registe

Re: [Intel-gfx] [PATCH 01/12] drm/edid: use struct edid * in drm_do_get_edid()

On Wed, 30 Mar 2022, Ville Syrjälä wrote: > On Tue, Mar 29, 2022 at 09:42:08PM +0300, Jani Nikula wrote: >> Mixing u8 * and struct edid * is confusing, switch to the latter. >> >> Cc: Ville Syrjälä >> Signed-off-by: Jani Nikula >> --- >> drivers/gpu/drm/drm_edid.c | 31 +++-

Re: [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [RESEND,1/3] drm/i915/dmc: abstract GPU error state dump

On Wed, 30 Mar 2022, Patchwork wrote: > == Series Details == > > Series: series starting with [RESEND,1/3] drm/i915/dmc: abstract GPU error > state dump > URL : https://patchwork.freedesktop.org/series/101957/ > State : failure I don't get why this doesn't apply. It applies for me. BR, Jani

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/audio: unify audio codec enable/disable debug logging

== Series Details == Series: series starting with [1/2] drm/i915/audio: unify audio codec enable/disable debug logging URL : https://patchwork.freedesktop.org/series/101953/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11416_full -> Patchwork_22732_full =

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: avoid concurrent writes to aux_inv (rev10)

On 29/03/2022 16:59, Yang, Fei wrote: On 29/03/2022 03:30, Patchwork wrote: *Patch Details* *Series:* drm/i915: avoid concurrent writes to aux_inv (rev10) *URL:* https://patchwork.freedesktop.org/series/100772/ *State:*success *

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: avoid concurrent writes to aux_inv (rev10)

*Patch Details* *Series:* drm/i915: avoid concurrent writes to aux_inv (rev10) *URL:* https://patchwork.freedesktop.org/series/100772/ *State:* success *Details:* https://intel-gfx-ci.01.org/tree/drm-tip/Pa

Re: [Intel-gfx] [PATCH 01/12] drm/edid: use struct edid * in drm_do_get_edid()

On Wed, Mar 30, 2022 at 06:16:17PM +0300, Jani Nikula wrote: > On Wed, 30 Mar 2022, Ville Syrjälä wrote: > > On Tue, Mar 29, 2022 at 09:42:08PM +0300, Jani Nikula wrote: > >> Mixing u8 * and struct edid * is confusing, switch to the latter. > >> > >> Cc: Ville Syrjälä > >> Signed-off-by: Jani Ni

[Intel-gfx] [PATCH CIv2 1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL

MBUS_DBOX_B2B_TRANSACTIONS_MAX, MBUS_DBOX_B2B_TRANSACTIONS_DELAY and MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN were being programmed with zeros while specification has different default values for this registers in display 12 and newer. While at it also converting all MBUS_DBOX macros to use REG_* ma

[Intel-gfx] [PATCH CIv2 2/4] drm/i915/display/adlp: Adjust MBUS DBOX BW and B credits

From: Caz Yokoyama Alderlake-P has different MBUS DBOX BW and B credits than other platforms, so here setting it properly. BSpec: 49213 BSpec: 50343 Cc: Matt Roper Cc: Stanislav Lisovskiy Cc: Jani Nikula Cc: Ville Syrjälä Reviewed-by: Ville Syrjälä Signed-off-by: Caz Yokoyama Signed-off-by

[Intel-gfx] [PATCH CIv2 3/4] drm/i915/display: Add HAS_MBUS_JOINING

This will make easy to extend MBUS joining support to future platforms that also supports this feature. Reviewed-by: Ville Syrjälä Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/intel_pm.c | 6 +++--- 2 files changed, 5 insertions(+), 3 del

[Intel-gfx] [PATCH CIv2 4/4] drm/i915/display/adlp: Fix programing of PIPE_MBUS_DBOX_CTL

PIPE_MBUS_DBOX_CTL was only being programmed when a pipe is being enabled but that could potentially cause issues as it could have mismatching values while pipes are being enabled. So here moving the PIPE_MBUS_DBOX_CTL programming of all pipes to be executed before the function that enables all pi

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: avoid concurrent writes to aux_inv (rev10)

On 30/03/2022 16:37, Yang, Fei wrote: *Patch Details* *Series:* drm/i915: avoid concurrent writes to aux_inv (rev10) *URL:* https://patchwork.freedesktop.org/series/100772/ *State:*success *Details:* https://intel-gfx-ci.01.org/t

Re: [Intel-gfx] [PATCH] drm/i915/guc: Use iosys_map interface to update lrc_desc

Sorry, only just seen this patch. Please do not do this! The entire lrc_desc_pool entity is being dropped as part of the update to GuC v70. That's why there was a recent patch set to significantly re-organise how/where it is used. That patch set explicitly said - this is all in preparation fo

[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [CIv2,1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL

== Series Details == Series: series starting with [CIv2,1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL URL : https://patchwork.freedesktop.org/series/101963/ State : failure == Summary == Applying: drm/i915/display/tgl+: Set default values for all regis

Re: [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [CIv2,1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL

On Wed, 2022-03-30 at 15:54 +, Patchwork wrote: > == Series Details == > > Series: series starting with [CIv2,1/4] drm/i915/display/tgl+: Set default > values for all registers in PIPE_MBUS_DBOX_CTL > URL : https://patchwork.freedesktop.org/series/101963/ > State : failure > > == Summary =

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/adlp: Fix register corruption after DDI clock enabling (rev2)

== Series Details == Series: drm/i915/adlp: Fix register corruption after DDI clock enabling (rev2) URL : https://patchwork.freedesktop.org/series/101712/ State : success == Summary == CI Bug Log - changes from CI_DRM_11416 -> Patchwork_22718 ===

[Intel-gfx] [PATCH CI v3 1/3] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL

MBUS_DBOX_B2B_TRANSACTIONS_MAX, MBUS_DBOX_B2B_TRANSACTIONS_DELAY and MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN were being programmed with zeros while specification has different default values for this registers in display 12 and newer. While at it also converting all MBUS_DBOX macros to use REG_* ma

[Intel-gfx] [PATCH CI v3 2/3] drm/i915/display/adlp: Adjust MBUS DBOX BW and B credits

From: Caz Yokoyama Alderlake-P has different MBUS DBOX BW and B credits than other platforms, so here setting it properly. BSpec: 49213 BSpec: 50343 Cc: Matt Roper Cc: Stanislav Lisovskiy Cc: Jani Nikula Cc: Ville Syrjälä Reviewed-by: Ville Syrjälä Signed-off-by: Caz Yokoyama Signed-off-by

[Intel-gfx] [PATCH CI v3 3/3] drm/i915/display/adlp: Fix programing of PIPE_MBUS_DBOX_CTL

PIPE_MBUS_DBOX_CTL was only being programmed when a pipe is being enabled but that could potentially cause issues as it could have mismatching values while pipes are being enabled. So here moving the PIPE_MBUS_DBOX_CTL programming of all pipes to be executed before the function that enables all pi

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Refactor the display power domain mappings (rev3)

== Series Details == Series: drm/i915: Refactor the display power domain mappings (rev3) URL : https://patchwork.freedesktop.org/series/99476/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11416 -> Patchwork_22722 Summary -

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,v3,1/3] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL

== Series Details == Series: series starting with [CI,v3,1/3] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL URL : https://patchwork.freedesktop.org/series/101965/ State : warning == Summary == $ dim checkpatch origin/drm-tip a389720ee911 drm/i915/display/tg

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,v3,1/3] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL

== Series Details == Series: series starting with [CI,v3,1/3] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL URL : https://patchwork.freedesktop.org/series/101965/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast m

[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [CI,v3,1/3] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL

== Series Details == Series: series starting with [CI,v3,1/3] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL URL : https://patchwork.freedesktop.org/series/101965/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i

Re: [Intel-gfx] [PATCH 01/12] drm/edid: use struct edid * in drm_do_get_edid()

On Wed, 30 Mar 2022, Ville Syrjälä wrote: > On Wed, Mar 30, 2022 at 06:16:17PM +0300, Jani Nikula wrote: >> On Wed, 30 Mar 2022, Ville Syrjälä wrote: >> > On Tue, Mar 29, 2022 at 09:42:08PM +0300, Jani Nikula wrote: >> >> Mixing u8 * and struct edid * is confusing, switch to the latter. >> >> >>

Re: [Intel-gfx] [PATCH v3 1/2] drm/i915/gt: Split intel-gtt functions by arch

On 3/30/22 03:23, Jani Nikula wrote: On Wed, 30 Mar 2022, Tvrtko Ursulin wrote: On 30/03/2022 00:58, Casey Bowman wrote: Some functions defined in the intel-gtt module are used in several areas, but is only supported on x86 platforms. By separating these calls and their static underlying f

Re: [Intel-gfx] [PATCH v3 1/2] drm/i915/gt: Split intel-gtt functions by arch

On 3/30/22 03:16, Jani Nikula wrote: On Tue, 29 Mar 2022, Casey Bowman wrote: +/* Stubs for non-x86 platforms */ +#else +static inline void intel_gt_gmch_gen5_chipset_flush(struct intel_gt *gt) +{ +} +static inline int intel_gt_gmch_gen5_probe(struct i915_ggtt *ggtt) +{ + /* No HW shou

Re: [Intel-gfx] [PATCH 1/2] drm/i915/audio: unify audio codec enable/disable debug logging

On Wed, 30 Mar 2022, Ville Syrjälä wrote: > On Wed, Mar 30, 2022 at 12:41:08PM +0300, Jani Nikula wrote: >> The audio codec enable/disable debug logging is spread around in callers >> and the platform specific hooks. Put them all together in one place on >> both the enable and disable paths. >> >

Re: [Intel-gfx] [PATCH] drm/i915/dp: make DSC usage logging actually useful

On Wed, 30 Mar 2022, Ville Syrjälä wrote: > On Wed, Mar 30, 2022 at 12:30:19PM +0300, Jani Nikula wrote: >> Debug log when DSC is going to be used, and why, instead of >> unconditionally logging the rarely used debug option setting, which >> might not have any bearing on whether DSC is going to be

Re: [Intel-gfx] [PATCH v3 1/2] drm/i915/gt: Split intel-gtt functions by arch

On 3/30/22 02:55, Tvrtko Ursulin wrote: On 30/03/2022 00:58, Casey Bowman wrote: Some functions defined in the intel-gtt module are used in several areas, but is only supported on x86 platforms. By separating these calls and their static underlying functions to another area, we are able to

Re: [Intel-gfx] [PATCH 01/12] drm/edid: use struct edid * in drm_do_get_edid()

On Wed, Mar 30, 2022 at 07:28:56PM +0300, Jani Nikula wrote: > On Wed, 30 Mar 2022, Ville Syrjälä wrote: > > On Wed, Mar 30, 2022 at 06:16:17PM +0300, Jani Nikula wrote: > >> On Wed, 30 Mar 2022, Ville Syrjälä wrote: > >> > On Tue, Mar 29, 2022 at 09:42:08PM +0300, Jani Nikula wrote: > >> >> Mixi

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Refactor the display power domain mappings (rev3)

== Series Details == Series: drm/i915: Refactor the display power domain mappings (rev3) URL : https://patchwork.freedesktop.org/series/99476/ State : success == Summary == CI Bug Log - changes from CI_DRM_11416 -> Patchwork_22722 Summary -

[Intel-gfx] [PATCH] drm/edid: fix invalid EDID extension block filtering

The invalid EDID block filtering uses the number of valid EDID extensions instead of all EDID extensions for looping the extensions in the copy. This is fine, by coincidence, if all the invalid blocks are at the end of the EDID. However, it's completely broken if there are invalid extensions in the

Re: [Intel-gfx] [PATCH 01/12] drm/edid: use struct edid * in drm_do_get_edid()

On Wed, 30 Mar 2022, Ville Syrjälä wrote: > I'd fix this up front so we don't end having to backport the whole > thing if/when some security scan gizmo stumbles on this. Sent separately [1]. I'll rebase this series on top once that gets merged, but the conflict is trivial so I think the first rou

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,v3,1/3] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL

== Series Details == Series: series starting with [CI,v3,1/3] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL URL : https://patchwork.freedesktop.org/series/101965/ State : success == Summary == CI Bug Log - changes from CI_DRM_11416 -> Patchwork_22737 ==

Re: [Intel-gfx] [PATCH] drm/edid: fix invalid EDID extension block filtering

On Wed, Mar 30, 2022 at 08:04:26PM +0300, Jani Nikula wrote: > The invalid EDID block filtering uses the number of valid EDID > extensions instead of all EDID extensions for looping the extensions in > the copy. This is fine, by coincidence, if all the invalid blocks are at > the end of the EDID. H

Re: [Intel-gfx] [PATCH v3 1/2] drm/i915/gt: Split intel-gtt functions by arch

On Wed, 30 Mar 2022, Casey Bowman wrote: > On 3/30/22 02:55, Tvrtko Ursulin wrote: >> I mean I could suggest to do something about the incosistency of: >> >> static inline void intel_gt_gmch_gen5_chipset_flush(struct intel_gt *gt) >> >> vs: >> >> static inline int intel_gt_gmch_gen5_probe(struct i

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/adlp: Fix register corruption after DDI clock enabling (rev2)

== Series Details == Series: drm/i915/adlp: Fix register corruption after DDI clock enabling (rev2) URL : https://patchwork.freedesktop.org/series/101712/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11416_full -> Patchwork_22718_full =

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/edid: fix invalid EDID extension block filtering

== Series Details == Series: drm/edid: fix invalid EDID extension block filtering URL : https://patchwork.freedesktop.org/series/101969/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not f

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Refactor the display power domain mappings (rev3)

== Series Details == Series: drm/i915: Refactor the display power domain mappings (rev3) URL : https://patchwork.freedesktop.org/series/99476/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11416_full -> Patchwork_22722_full

Re: [Intel-gfx] [PATCH v3 1/2] drm/i915/gt: Split intel-gtt functions by arch

On 3/30/22 10:25, Jani Nikula wrote: On Wed, 30 Mar 2022, Casey Bowman wrote: On 3/30/22 02:55, Tvrtko Ursulin wrote: I mean I could suggest to do something about the incosistency of: static inline void intel_gt_gmch_gen5_chipset_flush(struct intel_gt *gt) vs: static inline int intel_gt_

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/edid: fix invalid EDID extension block filtering

== Series Details == Series: drm/edid: fix invalid EDID extension block filtering URL : https://patchwork.freedesktop.org/series/101969/ State : success == Summary == CI Bug Log - changes from CI_DRM_11416 -> Patchwork_22738 Summary ---

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,v3,1/3] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL

== Series Details == Series: series starting with [CI,v3,1/3] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL URL : https://patchwork.freedesktop.org/series/101965/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11416_full -> Patchwork_22737_f

Re: [Intel-gfx] [PATCH i-g-t 01/11] lib: Helper library for parsing i915 fdinfo output

On Tue, Feb 22, 2022 at 01:55:55PM +, Tvrtko Ursulin wrote: From: Tvrtko Ursulin Tests and intel_gpu_top will share common code for parsing this file. Signed-off-by: Tvrtko Ursulin --- lib/igt_drm_fdinfo.c | 183 +++ lib/igt_drm_fdinfo.h | 48 ++

Re: [Intel-gfx] [PATCH] drm/i915/guc: Use iosys_map interface to update lrc_desc

On Wed, Mar 30, 2022 at 08:53:11AM -0700, John Harrison wrote: > Sorry, only just seen this patch. > > Please do not do this! > > The entire lrc_desc_pool entity is being dropped as part of the update to > GuC v70. That's why there was a recent patch set to significantly > re-organise how/where i

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 02/11] tests/i915/drm_fdinfo: Basic and functional tests for GPU busyness exported via fdinfo

This looks very similar to existing perf_pmu tests with the slight change that the busyness is now captured from the fdinfo. lgtm, Reviewed-by: Umesh Nerlige Ramappa Umesh On Tue, Feb 22, 2022 at 01:55:56PM +, Tvrtko Ursulin wrote: From: Tvrtko Ursulin Mostly inherited from the perf_pm

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,v3,1/3] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL

On Wed, 2022-03-30 at 19:29 +, Patchwork wrote: Patch Details Series: series starting with [CI,v3,1/3] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL URL:https://patchwork.freedesktop.org/series/101965/ State: failure Details: https://intel-gfx-c

[Intel-gfx] [CI 0/6] Add driver for GSC controller

Same as the v11 version already fully reviewed (bar a very minor rebase), but with an added patch to force the new aux driver to be built in CI. Resend to test with updated IGT. Test-with: 20220330183259.3003663-1-daniele.ceraolospu...@intel.com Cc: Alexander Usyskin Alexander Usyskin (2): me

[Intel-gfx] [CI 6/6] HAX: drm/i915: force INTEL_MEI_GSC on for CI

After the new config option is merged we'll enable it by default in the CI config, but for now just force it on via the i915 Kconfig so we can get pre-merge CI results for it. Signed-off-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/Kconfig.debug | 1 + 1 file changed, 1 insertion(+) diff

[Intel-gfx] [CI 1/6] drm/i915/gsc: add gsc as a mei auxiliary device

From: Tomas Winkler GSC is a graphics system controller, it provides a chassis controller for graphics discrete cards. There are two MEI interfaces in GSC: HECI1 and HECI2. Both interfaces are on the BAR0 at offsets 0x00258000 and 0x00259000. GSC is a GT Engine (class 4: instance 6). HECI1 inte

[Intel-gfx] [CI 5/6] mei: gsc: retrieve the firmware version

From: Alexander Usyskin Add a hook to retrieve the firmware version of the GSC devices to bus-fixup. GSC has a different MKHI clients GUIDs but the same message structure to retrieve the firmware version as MEI so mei_fwver() can be reused. CC: Ashutosh Dixit Signed-off-by: Alexander Usyskin S

[Intel-gfx] [CI 2/6] mei: add support for graphics system controller (gsc) devices

From: Tomas Winkler GSC is a graphics system controller, based on CSE, it provides a chassis controller for graphics discrete cards, as well as it supports media protection on selected devices. mei_gsc binds to a auxiliary devices exposed by Intel discrete driver i915. Signed-off-by: Alexander

[Intel-gfx] [CI 4/6] mei: gsc: add runtime pm handlers

From: Tomas Winkler Implement runtime handlers for mei-gsc, to track idle state of the device properly. CC: Rodrigo Vivi Signed-off-by: Tomas Winkler Signed-off-by: Alexander Usyskin Reviewed-by: Rodrigo Vivi --- drivers/misc/mei/gsc-me.c | 67 ++- 1 file

[Intel-gfx] [CI 3/6] mei: gsc: setup char driver alive in spite of firmware handshake failure

From: Alexander Usyskin Setup char device in spite of firmware handshake failure. In order to provide host access to the firmware status registers and other information required for the manufacturing process. Signed-off-by: Alexander Usyskin Signed-off-by: Tomas Winkler Reviewed-by: Daniele Ce

Re: [Intel-gfx] [PATCH 01/12] drm/edid: use struct edid * in drm_do_get_edid()

On Wed, 30 Mar 2022, Jani Nikula wrote: > On Wed, 30 Mar 2022, Ville Syrjälä wrote: >> This one points to extension blocks too so using >> struct edid doesn't seem entirely appropriate. > > So I've gone back and forth with this. I think I want to get rid of u8* > no matter what, because it alway

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add driver for GSC controller (rev14)

== Series Details == Series: Add driver for GSC controller (rev14) URL : https://patchwork.freedesktop.org/series/98066/ State : warning == Summary == $ dim checkpatch origin/drm-tip 690fddb652c2 drm/i915/gsc: add gsc as a mei auxiliary device -:65: WARNING:FILE_PATH_CHANGES: added, moved or d

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add driver for GSC controller (rev14)

== Series Details == Series: Add driver for GSC controller (rev14) URL : https://patchwork.freedesktop.org/series/98066/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.DOCS: warning for Add driver for GSC controller (rev14)

== Series Details == Series: Add driver for GSC controller (rev14) URL : https://patchwork.freedesktop.org/series/98066/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not found ./drivers/g

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Refactor the display power domain mappings (rev3)

== Series Details == Series: drm/i915: Refactor the display power domain mappings (rev3) URL : https://patchwork.freedesktop.org/series/99476/ State : success == Summary == CI Bug Log - changes from CI_DRM_11416_full -> Patchwork_22722_full

[Intel-gfx] [PATCH v4 RFC] drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES

Newer platforms have DSS that aren't necessarily available for both geometry and compute, two queries will need to exist. This introduces the first, when passing a valid engine class and engine instance in the flags returns a topology describing geometry. v2: fix white space errors v3: change flag

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/edid: fix invalid EDID extension block filtering

== Series Details == Series: drm/edid: fix invalid EDID extension block filtering URL : https://patchwork.freedesktop.org/series/101969/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11416_full -> Patchwork_22738_full Summa

[Intel-gfx] ✗ Fi.CI.BAT: failure for Add driver for GSC controller (rev14)

== Series Details == Series: Add driver for GSC controller (rev14) URL : https://patchwork.freedesktop.org/series/98066/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11416 -> Patchwork_22739 Summary --- **FAILURE**

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES (rev4)

== Series Details == Series: drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES (rev4) URL : https://patchwork.freedesktop.org/series/101219/ State : warning == Summary == $ dim checkpatch origin/drm-tip 6f3dde840f67 drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES -:133: CHECK:SPACING:

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