[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display/debugfs: Add connector debugfs for "output_bpc" (rev2)

== Series Details == Series: drm/i915/display/debugfs: Add connector debugfs for "output_bpc" (rev2) URL : https://patchwork.freedesktop.org/series/101858/ State : success == Summary == CI Bug Log - changes from CI_DRM_11415 -> Patchwork_22712 ==

Re: [Intel-gfx] [Linaro-mm-sig] [PATCH 1/2] dma-buf/sync-file: fix logic error in new fence merge code

For the series, Reviewed-by: Thomas Hellström On 3/29/22 09:00, Christian König wrote: When the array is empty because everything is signaled we can't use add_fence() to add something because that would filter the signaled fence again. Signed-off-by: Christian König Fixes: 519f490db07e ("dm

Re: [Intel-gfx] [CI 1/4] drm/i915/gt: Explicitly clear BB_OFFSET for new contexts

On 28/03/2022 18:25, Matthew Auld wrote: From: Chris Wilson Even though the initial protocontext we load onto HW has the register cleared, by the time we save it into the default image, BB_OFFSET has had the enable bit set. Reclear BB_OFFSET for each new context. Intriguing - is there any i

Re: [Intel-gfx] [PATCH] drm/i915: avoid concurrent writes to aux_inv

On 28/03/2022 18:16, fei.y...@intel.com wrote: From: Fei Yang GPU hangs have been observed when multiple engines write to the same aux_inv register at the same time. To avoid this each engine should only invalidate its own auxiliary table. The function gen12_emit_flush_xcs() currently invalid

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: avoid concurrent writes to aux_inv (rev10)

On 29/03/2022 03:30, Patchwork wrote: *Patch Details* *Series:* drm/i915: avoid concurrent writes to aux_inv (rev10) *URL:* https://patchwork.freedesktop.org/series/100772/ *State:*success *Details:* https://intel-gfx-ci.01.org

Re: [Intel-gfx] [PATCH v7 9/9] drm/i915/migrate: Evict and restore the flatccs capable lmem obj

On 3/28/22 21:07, Ramalingam C wrote: When we are swapping out the local memory obj on flat-ccs capable platform, we need to capture the ccs data too along with main meory and we need to restore it when we are swapping in the content. When lmem object is swapped into a smem obj, smem obj will

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display/debugfs: Add connector debugfs for "output_bpc" (rev2)

== Series Details == Series: drm/i915/display/debugfs: Add connector debugfs for "output_bpc" (rev2) URL : https://patchwork.freedesktop.org/series/101858/ State : success == Summary == CI Bug Log - changes from CI_DRM_11415_full -> Patchwork_22712_full

Re: [Intel-gfx] [PATCH 1/2] dma-buf/sync-file: fix logic error in new fence merge code

On Tue, Mar 29, 2022 at 09:00:00AM +0200, Christian König wrote: > When the array is empty because everything is signaled we can't use > add_fence() to add something because that would filter the signaled > fence again. > > Signed-off-by: Christian König > Fixes: 519f490db07e ("dma-buf/sync-file:

Re: [Intel-gfx] [PATCH 2/2] dma-buf: handle empty dma_fence_arrays gracefully

On Tue, Mar 29, 2022 at 09:00:01AM +0200, Christian König wrote: > A bug inside the new sync-file merge code created empty dma_fence_array > instances. > > Warn about that and handle those without crashing. > > Signed-off-by: Christian König > --- > drivers/dma-buf/dma-fence-array.c | 5 +

Re: [Intel-gfx] [PATCH 2/2] dma-buf: handle empty dma_fence_arrays gracefully

On Tue, Mar 29, 2022 at 10:48:10AM +0200, Daniel Vetter wrote: > On Tue, Mar 29, 2022 at 09:00:01AM +0200, Christian König wrote: > > A bug inside the new sync-file merge code created empty dma_fence_array > > instances. > > > > Warn about that and handle those without crashing. > > > > Signed-o

Re: [Intel-gfx] [PATCH 1/2] dma-buf/sync-file: fix logic error in new fence merge code

I finally managed to find a machine and tested this series. If it is not too late The series is Tested-by: Nirmoy Das On 3/29/2022 9:00 AM, Christian König wrote: When the array is empty because everything is signaled we can't use add_fence() to add something because that would filter the sig

[Intel-gfx] [CI v2] drm/i915: Move intel_vtd_active and run_as_guest to i915_utils

From: Tvrtko Ursulin Continuation of the effort to declutter i915_drv.h. Also, component specific helpers which consult the iommu/virtualization helpers moved to respective component source/header files as appropriate. v2: * s/dev_priv/i915/ in intel_scanout_needs_vtd_wa. (Lucas) Signed-off-b

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/edid: constify EDID parsing, with fixes (rev3)

== Series Details == Series: drm/edid: constify EDID parsing, with fixes (rev3) URL : https://patchwork.freedesktop.org/series/101883/ State : warning == Summary == $ dim checkpatch origin/drm-tip 42edbd32ada4 drm/edid: don't modify EDID while parsing 837379bc0347 drm/edid: fix reduced blankin

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/edid: constify EDID parsing, with fixes (rev3)

== Series Details == Series: drm/edid: constify EDID parsing, with fixes (rev3) URL : https://patchwork.freedesktop.org/series/101883/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +./drivers/g

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/edid: constify EDID parsing, with fixes (rev3)

== Series Details == Series: drm/edid: constify EDID parsing, with fixes (rev3) URL : https://patchwork.freedesktop.org/series/101883/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not fou

Re: [Intel-gfx] [PATCH 1/4] drm/i915: Remove locks around skl+ scaler programming

On Thu, Feb 24, 2022 at 06:51:00PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > All the skl+ scaler registers are suitably confined to their own > cachelines so we don't need the uncore.lock to globally serialize > access to these registers. We actually already dropped some of this > in

Re: [Intel-gfx] [PATCH 2/4] drm/i915: Make ilk+ pfit regiser unlocked

On Thu, Feb 24, 2022 at 06:51:01PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > The ilk+ panel fitter register are sitting nicely on their own > cacheline, so no need for global serialization via uncore.lock. > > Signed-off-by: Ville Syrjälä Reviewed-by: Stanislav Lisovskiy > --- >

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Split pipe+output CSC programming to noarm+arm pair

On Thu, Feb 24, 2022 at 06:51:03PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > Move most of the pipe+output CSC programming to the > .color_commit_noarm() hook which runs before vblank evasion. > Only PIPE_CSC_MODE (the arming register) needs to remain in > inside the critical section.

Re: [Intel-gfx] [PATCH 3/4] drm/i915: Split color_commit() into noarm+arm pair

On Thu, Feb 24, 2022 at 06:51:02PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > To reduce the amount of registers written during the vblank evade > critical section let's also split the .color_commit() hook to > noarm+arm pair. The noarm hook runs before the vblank evasion > with the arm

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Move intel_vtd_active and run_as_guest to i915_utils (rev2)

== Series Details == Series: drm/i915: Move intel_vtd_active and run_as_guest to i915_utils (rev2) URL : https://patchwork.freedesktop.org/series/101874/ State : warning == Summary == $ dim checkpatch origin/drm-tip c4372f7544c7 drm/i915: Move intel_vtd_active and run_as_guest to i915_utils -:

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/edid: constify EDID parsing, with fixes (rev3)

== Series Details == Series: drm/edid: constify EDID parsing, with fixes (rev3) URL : https://patchwork.freedesktop.org/series/101883/ State : success == Summary == CI Bug Log - changes from CI_DRM_11416 -> Patchwork_22713 Summary ---

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Move intel_vtd_active and run_as_guest to i915_utils (rev2)

== Series Details == Series: drm/i915: Move intel_vtd_active and run_as_guest to i915_utils (rev2) URL : https://patchwork.freedesktop.org/series/101874/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separat

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Move intel_vtd_active and run_as_guest to i915_utils (rev2)

== Series Details == Series: drm/i915: Move intel_vtd_active and run_as_guest to i915_utils (rev2) URL : https://patchwork.freedesktop.org/series/101874/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_dr

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/4] drm/i915/gt: Explicitly clear BB_OFFSET for new contexts (rev2)

== Series Details == Series: series starting with [CI,1/4] drm/i915/gt: Explicitly clear BB_OFFSET for new contexts (rev2) URL : https://patchwork.freedesktop.org/series/101899/ State : warning == Summary == $ dim checkpatch origin/drm-tip d7e2ab52888e drm/i915/gt: Explicitly clear BB_OFFSET

Re: [Intel-gfx] [bug report] High refresh rates broken on eDP display with Optimus

Hi, Please file bug to gitlab: https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs > -Original Message- > From: Intel-gfx On Behalf Of Jeffrey > Ellison > Sent: tiistai 29. maaliskuuta 2022 5.38 > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [bug report]

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/4] drm/i915/gt: Explicitly clear BB_OFFSET for new contexts (rev2)

== Series Details == Series: series starting with [CI,1/4] drm/i915/gt: Explicitly clear BB_OFFSET for new contexts (rev2) URL : https://patchwork.freedesktop.org/series/101899/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit

[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [CI,1/4] drm/i915/gt: Explicitly clear BB_OFFSET for new contexts (rev2)

== Series Details == Series: series starting with [CI,1/4] drm/i915/gt: Explicitly clear BB_OFFSET for new contexts (rev2) URL : https://patchwork.freedesktop.org/series/101899/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_drr

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Move intel_vtd_active and run_as_guest to i915_utils (rev2)

== Series Details == Series: drm/i915: Move intel_vtd_active and run_as_guest to i915_utils (rev2) URL : https://patchwork.freedesktop.org/series/101874/ State : success == Summary == CI Bug Log - changes from CI_DRM_11416 -> Patchwork_22714

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/4] drm/i915/gt: Explicitly clear BB_OFFSET for new contexts (rev2)

== Series Details == Series: series starting with [CI,1/4] drm/i915/gt: Explicitly clear BB_OFFSET for new contexts (rev2) URL : https://patchwork.freedesktop.org/series/101899/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11416 -> Patchwork_22715 ===

Re: [Intel-gfx] [PATCH v2] drm: add a check to verify the size alignment

On Tue, 29 Mar 2022 at 12:17, Arunpravin Paneer Selvam wrote: > > > > On 23/03/22 1:15 pm, Christian König wrote: > > Am 23.03.22 um 08:34 schrieb Arunpravin Paneer Selvam: > >> Add a simple check to reject any size not aligned to the > >> min_page_size. > >> > >> handle instances when size is not

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/edid: constify EDID parsing, with fixes (rev3)

== Series Details == Series: drm/edid: constify EDID parsing, with fixes (rev3) URL : https://patchwork.freedesktop.org/series/101883/ State : success == Summary == CI Bug Log - changes from CI_DRM_11416_full -> Patchwork_22713_full Summary

[Intel-gfx] [PATCH 1/2] dma-buf/sync-file: fix logic error in new fence merge code

When the array is empty because everything is signaled we can't use add_fence() to add something because that would filter the signaled fence again. Signed-off-by: Christian König Fixes: 519f490db07e ("dma-buf/sync-file: fix warning about fence containers") --- drivers/dma-buf/sync_file.c | 2 +-

[Intel-gfx] [PATCH 2/2] dma-buf: handle empty dma_fence_arrays gracefully

A bug inside the new sync-file merge code created empty dma_fence_array instances. Warn about that and handle those without crashing. Signed-off-by: Christian König --- drivers/dma-buf/dma-fence-array.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/dma-buf/dma-fence-array.c

Re: [Intel-gfx] [PATCH] drm/i915/adl_p: Increase CDCLK by 15% if PSR2 is used

On Tue, Mar 22, 2022 at 03:36:10PM +0200, Souza, Jose wrote: > On Tue, 2022-03-22 at 09:49 +0200, Lisovskiy, Stanislav wrote: > > On Mon, Mar 21, 2022 at 07:01:27PM +0200, Souza, Jose wrote: > > > On Mon, 2022-03-21 at 12:49 +0200, Stanislav Lisovskiy wrote: > > > > We are currently getting FIFO un

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] dma-buf/sync-file: fix logic error in new fence merge code

== Series Details == Series: series starting with [1/2] dma-buf/sync-file: fix logic error in new fence merge code URL : https://patchwork.freedesktop.org/series/101923/ State : failure == Summary == Applying: dma-buf/sync-file: fix logic error in new fence merge code Using index info to reco

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for docs: gpu: i915.rst: Fix DRRS documentation (rev2)

On Tue, 2022-03-29 at 00:00 +, Patchwork wrote: Patch Details Series: docs: gpu: i915.rst: Fix DRRS documentation (rev2) URL:https://patchwork.freedesktop.org/series/101806/ State: success Details: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22699/index.html CI Bug Log - cha

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Start reordering modeset clock calculations (rev2)

== Series Details == Series: drm/i915: Start reordering modeset clock calculations (rev2) URL : https://patchwork.freedesktop.org/series/101789/ State : warning == Summary == $ dim checkpatch origin/drm-tip 0cc647463e24 drm/i915: Make .get_dplls() return int 26c2cde200f7 drm/i915: Pass dev_pri

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Start reordering modeset clock calculations (rev2)

== Series Details == Series: drm/i915: Start reordering modeset clock calculations (rev2) URL : https://patchwork.freedesktop.org/series/101789/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Start reordering modeset clock calculations (rev2)

== Series Details == Series: drm/i915: Start reordering modeset clock calculations (rev2) URL : https://patchwork.freedesktop.org/series/101789/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable

Re: [Intel-gfx] [PATCH v7 3/9] drm/i915/gt: Optimize the migration and clear loop

On 29.03.2022 00:37, Ramalingam C wrote: > Move the static calculations out of the loops for copy and clear. > > Signed-off-by: Ramalingam C > Reviewed-by: Thomas Hellström > --- > drivers/gpu/drm/i915/gt/intel_migrate.c | 44 - > 1 file changed, 21 insertions(+), 23 del

Re: [Intel-gfx] [PATCH] drm/i915/adl_p: Increase CDCLK by 15% if PSR2 is used

On Tue, 2022-03-29 at 16:10 +0300, Lisovskiy, Stanislav wrote: > On Tue, Mar 22, 2022 at 03:36:10PM +0200, Souza, Jose wrote: > > On Tue, 2022-03-22 at 09:49 +0200, Lisovskiy, Stanislav wrote: > > > On Mon, Mar 21, 2022 at 07:01:27PM +0200, Souza, Jose wrote: > > > > On Mon, 2022-03-21 at 12:49 +02

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Move intel_vtd_active and run_as_guest to i915_utils (rev2)

== Series Details == Series: drm/i915: Move intel_vtd_active and run_as_guest to i915_utils (rev2) URL : https://patchwork.freedesktop.org/series/101874/ State : success == Summary == CI Bug Log - changes from CI_DRM_11416_full -> Patchwork_22714_full ==

Re: [Intel-gfx] [PATCH] drm/i915/adl_p: Increase CDCLK by 15% if PSR2 is used

On Tue, Mar 29, 2022 at 04:24:30PM +0300, Souza, Jose wrote: > On Tue, 2022-03-29 at 16:10 +0300, Lisovskiy, Stanislav wrote: > > On Tue, Mar 22, 2022 at 03:36:10PM +0200, Souza, Jose wrote: > > > On Tue, 2022-03-22 at 09:49 +0200, Lisovskiy, Stanislav wrote: > > > > On Mon, Mar 21, 2022 at 07:01:2

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Start reordering modeset clock calculations (rev2)

== Series Details == Series: drm/i915: Start reordering modeset clock calculations (rev2) URL : https://patchwork.freedesktop.org/series/101789/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11416 -> Patchwork_22717 Summary

Re: [Intel-gfx] [PATCH] drm/i915: Add RPL-S PCI IDs

On Mon, Mar 28, 2022 at 09:29:51AM +, Gupta, Anshuman wrote: > > > > -Original Message- > > From: Intel-gfx On Behalf Of > > Surendrakumar Upadhyay, TejaskumarX > > Sent: Monday, March 28, 2022 2:52 PM > > To: intel-gfx@lists.freedesktop.org > > Subject: Re: [Intel-gfx] [PATCH] drm/i

[Intel-gfx] [PATCH 00/11] drm/i915: Finish off static DRRS

From: Ville Syrjälä (Hopefully) finish the static DRRS work: - Finish off a bunch of fixed mode refactoring - Allow fixed modes with any refresh rate, including ones that exceed the panel's preferred mode. Useful for laptops with high refresh rate panels (120-300Hz seen in the wild so far)

[Intel-gfx] [PATCH 01/11] drm/i915: Extract intel_edp_has_drrs()

From: Ville Syrjälä Pull all the eDP specific platform/port checks out from intel_drrs_init() into intel_edp_has_drrs(). Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dp.c | 35 ++- drivers/gpu/drm/i915/display/intel_drrs.c | 24 2 f

[Intel-gfx] [PATCH 02/11] drm/i915: Put fixed modes directly onto the panel's fixed_modes list

From: Ville Syrjälä Rather than having the connector init get the fixed mode back from intel_panel and then feed it straight back into intel_panel_init() let's just make the fixed mode lookup put the mode directly onto the panel's fixed_modes list. Avoids the pointless round trip and opens the do

[Intel-gfx] [PATCH 04/11] drm/i915: Nuke intel_drrs_init()

From: Ville Syrjälä intel_drrs_init() is a mostly pointless wrapper around intel_panel_add_edid_downclock_mode(), get rid of it. The only really useful thing left in there is the debug print regarding the DRRS type supported by the connector. Let's just move that into intel_panel_init(). Signed

[Intel-gfx] [PATCH 05/11] drm/i915: Combine the EDID fixed_mode+downclock_mode lookup into one

From: Ville Syrjälä The intel_panel_add_edid_fixed_mode() vs. intel_panel_add_edid_downclock_mode() split is not really helpful. Let's just roll those into a single function so that the connector init code doesn't have to care too much about this. All we need to know is whether DRRS should be all

[Intel-gfx] [PATCH 03/11] drm/i915: Refactor non-EDID fixed mode duplication

From: Ville Syrjälä All the non-EDID fixed mode functions basically do the exact same thing. Let's refactor the common bits into a shared function. There are minor differences on how the mode types are populated, whether the display info physical size is updated, and the debug print. The differe

[Intel-gfx] [PATCH 06/11] drm/i915: Stop duplicating the EDID fixed/downclock modes

From: Ville Syrjälä Instead of duplicating the fixed/downclock modes we can just grab the originals straight from the probed_modes list and keep them. The next .get_modes() is going to repopulate the probed_modes list anyway so whatever we leave there is just going to sit around until that time w

[Intel-gfx] [PATCH 09/11] drm/i915: Move intel_drrs_compute_config() into intel_dp.c

From: Ville Syrjälä intel_drrs_compute_config() is 100% DP specific. DRRS on other types of encoders wouldn't do any of these M2/N2 calculations etc. So let's move this into intel_dp.c so all the DP state calculation is more concentrated into one place. Signed-off-by: Ville Syrjälä --- drivers

[Intel-gfx] [PATCH 08/11] drm/i915: Allow higher refresh rate alternate fixed modes

From: Ville Syrjälä We shouldn't restrict ourselves to just downclock modes with lower refresh rate than the preferred mode. Laptops these days can offer higher refresh rate modes as well. Remove the arbitrary limit and allow all modes that, apart from the clock, match the preferred mode. Close

[Intel-gfx] [PATCH 11/11] drm/i915: Allow static DRRS on LVDS

From: Ville Syrjälä Nothing special about static DRRS on LVDS, it's just your bog standard modeset. Let's allow it. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_lvds.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/inte

[Intel-gfx] [PATCH 10/11] drm/i915: Allow static DRRS on all eDP ports

From: Ville Syrjälä Only seamless DRRS has specific hardware requirements so we can allow static DRRS on any eDP port. And we can replace these port checks and whatnot with a simple check to make sure the transcoder(s) we're about to use are capable of seamless DRRS. Signed-off-by: Ville Syrjäl

[Intel-gfx] [PATCH 07/11] drm/i915: Allow an arbitrary number of downclock modes

From: Ville Syrjälä Remove the "two fixed modes only" limit and grab as many downclock modes from the EDID as we can find. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_panel.c | 44 +++--- 1 file changed, 13 insertions(+), 31 deletions(-) diff --git a/dr

Re: [Intel-gfx] [PATCH 22/23] drm/i915: drop bo->moving dependency

On Mon, Mar 21, 2022 at 02:58:55PM +0100, Christian König wrote: > That should now be handled by the common dma_resv framework. > > Signed-off-by: Christian König > Cc: intel-gfx@lists.freedesktop.org Reviewed-by: Daniel Vetter > --- > drivers/gpu/drm/i915/gem/i915_gem_object.c | 29 ++-

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: avoid concurrent writes to aux_inv (rev10)

> On 29/03/2022 03:30, Patchwork wrote: >> *Patch Details* >> *Series:*drm/i915: avoid concurrent writes to aux_inv (rev10) >> *URL:* https://patchwork.freedesktop.org/series/100772/ >> >> *State:* success >> *Details:* >> https://in

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/adlp: Fix register corruption after DDI clock enabling (rev2)

== Series Details == Series: drm/i915/adlp: Fix register corruption after DDI clock enabling (rev2) URL : https://patchwork.freedesktop.org/series/101712/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separa

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/adlp: Fix register corruption after DDI clock enabling (rev2)

== Series Details == Series: drm/i915/adlp: Fix register corruption after DDI clock enabling (rev2) URL : https://patchwork.freedesktop.org/series/101712/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_d

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/dg2: Add Wa_22014226127 (rev4)

== Series Details == Series: drm/i915/dg2: Add Wa_22014226127 (rev4) URL : https://patchwork.freedesktop.org/series/101792/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not found ./driver

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/adlp: Fix register corruption after DDI clock enabling (rev2)

== Series Details == Series: drm/i915/adlp: Fix register corruption after DDI clock enabling (rev2) URL : https://patchwork.freedesktop.org/series/101712/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11416 -> Patchwork_22718 ===

[Intel-gfx] [PATCH v3 05/18] drm/i915: Move the HSW power well flags to a common bitfield

Save some space by grouping the HSW power well descriptor flags along with other flags in one bitfield. This change also lets simplifying the definition of power well descriptors sharing the same flags in an upcoming patch. Signed-off-by: Imre Deak Reviewed-by: Jouni Högander --- .../i915/disp

[Intel-gfx] [PATCH v3 13/18] drm/i915: Sanitize the ADL-S power well definition

Instead of the skip_mask special casing of the ADL-S power well descriptors, add a power well descriptor list for ADL-S as well reusing the TGL descriptors, w/o the TC-cold power well. ADL-S doesn't have TypeC PHYs, so a better way would be having ADL-S specific AUX descriptors, but I left changing

[Intel-gfx] [PATCH v3 04/18] drm/i915: Move the dg2 fixed_enable_delay power well param to a common bitfield

The DG2 fixed delay duration is always 600usec, so save some space in the power well descriptors by converting the parameter to a flag. While at it also use a bitfield for both the always_on and fixed_enable_delay flag. This change also lets simplifying the definiton of power wells sharing the sam

[Intel-gfx] [PATCH v3 07/18] drm/i915: Sanitize the power well names

Use the shortest descriptive name for all power wells for simplicity and to use the same name for the same type of power wells on multiple platforms. Signed-off-by: Imre Deak Reviewed-by: Jouni Högander --- .../i915/display/intel_display_power_map.c| 254 +- 1 file changed,

[Intel-gfx] [PATCH v3 15/18] drm/i915: Remove the aliasing of power domain enum values

Aliasing the intel_display_power_domain enum values was required because of the u64 power domain mask size limit. This makes the dmesg/debugfs printouts of the domain names somewhat unclear, for instance domain names for port D are shown on D12+ platforms where the corresponding port is called TC1.

[Intel-gfx] [PATCH v3 18/18] drm/i915: Remove the XELPD specific AUX and DDI power domains

The spec calls the XELPD_D/E ports just D/E, the platform prefix in the domain names was only needed by the port->domain mapping relying on matching enum values for the whole port/domain range (and the corresponding aliasing between the platform specific domain enums). Since a previous patch we can

[Intel-gfx] [PATCH v3 17/18] drm/i915: Remove duplicate DDI/AUX power domain mappings

The DDI and AUX domain -> power well mappings are identical for a few platforms/power well instances, reuse the mappings of earlier platforms for these removing the duplicate mapping of new platforms. Signed-off-by: Imre Deak Reviewed-by: Jouni Högander --- .../i915/display/intel_display_power_

[Intel-gfx] [PATCH v3 11/18] drm/i915: Allow platforms to share power well descriptors

Some power wells - like always-on and skl+/icl+ PW_1 - with the same name, domain list, flags, ops are used by multiple platforms, so allow platforms to reuse the descriptors of such power wells. This change also lets the follow up patches to simplify the DG1/RKL power well definitions, and remove

[Intel-gfx] [PATCH v3 14/18] drm/i915: Sanitize the port -> DDI/AUX power domain mapping for each platform

Atm the port -> DDI and AUX power domain mapping is specified by relying on the aliasing of the platform specific intel_display_power_domain enum values. For instance D12+ platforms refer to the 'D' port and power domain instances, which doesn't match the bspec terminology, on these platforms the c

[Intel-gfx] [PATCH v3 16/18] drm/i915: Remove the ICL specific TBT power domains

The spec calls the ICL TBT AUX power well instances TBT1-4 (similarly to all later platforms), align the power domain names with the spec. Signed-off-by: Imre Deak Reviewed-by: Jouni Högander --- .../gpu/drm/i915/display/intel_display_power.c | 10 +- .../gpu/drm/i915/display/intel_di

[Intel-gfx] [PATCH v3 08/18] drm/i915: Convert the power well descriptor domain mask to an array of domains

The next patch converts the i915_power_well_desc::domain mask from a u64 mask to a bitmap. I didn't find a reasonably simple way to initialize bitmaps statically, so prepare for the next patch here by converting the masks to an array of domain enums and initing the masks from these arrays during mo

[Intel-gfx] [PATCH v3 09/18] drm/i915: Convert the u64 power well domains mask to a bitmap

To remove the aliasing of the power domain enum values in a follow-up patch in this patchset (requiring a bigger mask) and allow for defining additional power domains in the future (at least some upcoming TypeC changes requires this) convert the u64 i915_power_well_desc::domains mask to a bitmap.

[Intel-gfx] [PATCH v3 12/18] drm/i915: Simplify the DG1 power well descriptors

Simplify the definition of DG1 power wells by reusing the identical RKL DDI/AUX descriptors. This reorders the DG1 DDI/AUX vs. PW4/5 power wells, but this shouldn't make a difference (it is the order on RKL and the DDI/AUX power wells don't have a dependency on PW4/5). Signed-off-by: Imre Deak R

[Intel-gfx] [PATCH v3 00/18] drm/i915: Refactor the display power domain mappings

This is v3 of the second half of [1], rebased on drm-tip (containing the first half [2]), addressing the review comments from Jouni and with a minor documentation/rename change in patch 3. [1] https://patchwork.freedesktop.org/series/99476/ [2] https://patchwork.freedesktop.org/series/100591/ Cc:

[Intel-gfx] [PATCH v3 02/18] drm/i915: Unexport the for_each_power_well() macros

The for_each_power_well() macros are only used in intel_display_power.c and intel_display_power_well.c, so unexport them. Signed-off-by: Imre Deak Reviewed-by: Jouni Högander --- .../drm/i915/display/intel_display_power.c| 8 .../drm/i915/display/intel_display_power.h| 20

[Intel-gfx] [PATCH v3 01/18] drm/i915: Move per-platform power well hooks to intel_display_power_well.c

Move the implementation of platform specific power well hooks to intel_display_power_well.c, to reduce the clutter in intel_display_power.c. The locking of all the power domain/power well state is handled in the power domain functions in intel_display_power.c using i915_power_domains::lock. This p

[Intel-gfx] [PATCH v3 03/18] drm/i915: Move the power domain->well mappings to intel_display_power_map.c

Move the list of platform specific power domain -> power well definitions to intel_display_power_map.c. While at it group the platforms' power domain macros with the corresponding power well lists and keep all the power domain lists in the same order (matching the enum order). No functional change

[Intel-gfx] [PATCH v3 06/18] drm/i915: Rename the power domain names to end with pipes/ports

Make all power domain names end with the pipe/port instance for consistency. No functional changes. Signed-off-by: Imre Deak Reviewed-by: Jouni Högander --- drivers/gpu/drm/i915/display/icl_dsi.c| 8 +- drivers/gpu/drm/i915/display/intel_ddi.c | 2 +- drivers/gpu/drm/i915/disp

[Intel-gfx] [PATCH v3 10/18] drm/i915: Simplify power well definitions by adding power well instances

All the port specific AUX/DDI_IO power wells share the same power well ops struct and flags, so we can save some space and simplify the definition of these by listing for all such power wells only the params specific to them (name, domains, power well register index, id). Move these params to a new

Re: [Intel-gfx] [PATCH 1/2] drm/i915/ats-m: add ATS-M platform info

Looks good to me. Reviewed-by: Balasubramani Vivekanandan On 28.03.2022 17:08, Matt Roper wrote: > ATS-M is a server platform based on Xe_HPG and Xe_HPM, but without > display support. From a driver point of view, it's easiest to just > handle it as DG2 (including identifying as PLATFORM_DG2),

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Finish off static DRRS

== Series Details == Series: drm/i915: Finish off static DRRS URL : https://patchwork.freedesktop.org/series/101928/ State : failure == Summary == Applying: drm/i915: Extract intel_edp_has_drrs() Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/display/intel_dp.c Fal

Re: [Intel-gfx] [PATCH] drm/i915/debugfs: Dump i915 children runtime status

On 28-03-2022 15:52, Anshuman Gupta wrote: i915 doesn't use pm_suspend_ignore_children() which warrants that any runtime active child of i915 will block the runtime suspend of i915. i915_runtime_pm_status only exposes i915 runtime pm usage_count, which is not sufficient to debug in the scenari

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add driver for GSC controller (rev13)

== Series Details == Series: Add driver for GSC controller (rev13) URL : https://patchwork.freedesktop.org/series/98066/ State : warning == Summary == $ dim checkpatch origin/drm-tip 8a042c9ddfdf drm/i915/gsc: add gsc as a mei auxiliary device -:65: WARNING:FILE_PATH_CHANGES: added, moved or d

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add driver for GSC controller (rev13)

== Series Details == Series: Add driver for GSC controller (rev13) URL : https://patchwork.freedesktop.org/series/98066/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dg2: Add Wa_22014226127 (rev4)

== Series Details == Series: drm/i915/dg2: Add Wa_22014226127 (rev4) URL : https://patchwork.freedesktop.org/series/101792/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11416 -> Patchwork_22719 Summary --- **FAILURE

[Intel-gfx] ✗ Fi.CI.DOCS: warning for Add driver for GSC controller (rev13)

== Series Details == Series: Add driver for GSC controller (rev13) URL : https://patchwork.freedesktop.org/series/98066/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not found ./drivers/g

[Intel-gfx] ✗ Fi.CI.BAT: failure for Add driver for GSC controller (rev13)

== Series Details == Series: Add driver for GSC controller (rev13) URL : https://patchwork.freedesktop.org/series/98066/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11416 -> Patchwork_22721 Summary --- **FAILURE**

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Refactor the display power domain mappings (rev3)

== Series Details == Series: drm/i915: Refactor the display power domain mappings (rev3) URL : https://patchwork.freedesktop.org/series/99476/ State : warning == Summary == $ dim checkpatch origin/drm-tip b760be68ea17 drm/i915: Move per-platform power well hooks to intel_display_power_well.c

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Refactor the display power domain mappings (rev3)

== Series Details == Series: drm/i915: Refactor the display power domain mappings (rev3) URL : https://patchwork.freedesktop.org/series/99476/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Refactor the display power domain mappings (rev3)

== Series Details == Series: drm/i915: Refactor the display power domain mappings (rev3) URL : https://patchwork.freedesktop.org/series/99476/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable'

Re: [Intel-gfx] [PATCH v3 1/3] drm/i915/display: Program PIPE_MBUS_DBOX_CTL with adl-p values

> -Original Message- > From: Intel-gfx On Behalf Of José > Roberto de Souza > Sent: Tuesday, March 29, 2022 12:46 AM > To: intel-gfx@lists.freedesktop.org > Cc: Nikula, Jani > Subject: [Intel-gfx] [PATCH v3 1/3] drm/i915/display: Program > PIPE_MBUS_DBOX_CTL with adl-p values > > From:

Re: [Intel-gfx] [PATCH v3 1/3] drm/i915/display: Program PIPE_MBUS_DBOX_CTL with adl-p values

On Mon, Mar 28, 2022 at 12:16:15PM -0700, José Roberto de Souza wrote: > From: Caz Yokoyama > > B credits set by IFWI do not match with specification default, so here > programming the right value. > > Also while at it, taking the oportunity to do a read-modify-write to > not overwrite all other

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Refactor the display power domain mappings (rev3)

== Series Details == Series: drm/i915: Refactor the display power domain mappings (rev3) URL : https://patchwork.freedesktop.org/series/99476/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11416 -> Patchwork_22722 Summary -

[Intel-gfx] [PATCH 00/12] drm/edid: cleanup and refactoring around validity checks

Another day, another batch of EDID code refactoring. Mostly the goal was to simplify drm_do_get_edid(), but trying to extract a const function for checking a single block validity lead me down a rabbit hole... BR, Jani. Cc: Ville Syrjälä Cc: Emil Velikov Jani Nikula (12): drm/edid: use str

[Intel-gfx] [PATCH 01/12] drm/edid: use struct edid * in drm_do_get_edid()

Mixing u8 * and struct edid * is confusing, switch to the latter. Cc: Ville Syrjälä Signed-off-by: Jani Nikula --- drivers/gpu/drm/drm_edid.c | 31 +++ 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_ed

[Intel-gfx] [PATCH 02/12] drm/edid: clean up EDID block checksum functions

Have two clear functions, one to compute the checksum over the EDID, and another to get the checksum from the EDID. Throw away the diff function. Ditch the drm_ prefix for static functions, and accept const void * to help transition to struct edid * usage. Cc: Ville Syrjälä Signed-off-by: Jani N

[Intel-gfx] [PATCH 03/12] drm/edid: add edid_block_tag() helper to get the EDID extension tag

The extension tag at offset 0 is not present in struct edid, add a helper for it to reduce the need to use u8 *. Cc: Ville Syrjälä Signed-off-by: Jani Nikula --- drivers/gpu/drm/drm_edid.c | 13 ++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/drm_edi

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