Hi
As I understand the config patch should go to
https://gitlab.freedesktop.org/gfx-ci/i915-infra kconfig/debug, branch "master".
Thus, this series does not need this change. Am I right?
--
Thanks,
Sasha
> -Original Message-
> From: Ceraolo Spurio, Daniele
> Sent: Tuesday, March 22,
This new debugfs will expose the connector's max supported bpc
and the bpc currently using. It is very useful for verifying
whether we enter the correct output color depth from IGT.
Example:
cat /sys/kernel/debug/dri/0/DP-1/output_bpc
Current: 8
Maximum: 10
Cc: Ville Syrjälä
Cc: Uma Shankar
Cc:
On 25/03/2022 01:03, Chuansheng Liu wrote:
The below memory leak information is caught:
unreferenced object 0x997dd4e3b240 (size 64):
comm "gem_tiled_fence", pid 10332, jiffies 4294959326 (age
220778.420s)
hex dump (first 32 bytes):
01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0
== Series Details ==
Series: drm/i915/display/debugfs: Add connector debugfs for "output_bpc"
URL : https://patchwork.freedesktop.org/series/101858/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_en
== Series Details ==
Series: drm/i915/display/debugfs: Add connector debugfs for "output_bpc"
URL : https://patchwork.freedesktop.org/series/101858/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11407 -> Patchwork_22693
Sum
On 28/03/2022 04:16, fei.y...@intel.com wrote:
From: Fei Yang
GPU hangs have been observed when multiple engines write to the
same aux_inv register at the same time. To avoid this each engine
should only invalidate its own auxiliary table. The function
gen12_emit_flush_xcs() currently invalid
+ Joonas
On 25/03/2022 23:03, Francisco Jerez wrote:
Matt Atwood writes:
Newer platforms have DSS that aren't necessarily available for both
geometry and compute, two queries will need to exist. This introduces
the first, when passing a valid engine class and engine instance in the
flags re
== Series Details ==
Series: drm/i915/display/debugfs: Add connector debugfs for "output_bpc"
URL : https://patchwork.freedesktop.org/series/101858/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11407_full -> Patchwork_22693_full
===
On 3/25/2022 9:33 PM, Ceraolo Spurio, Daniele wrote:
On 3/25/2022 11:37 AM, Das, Nirmoy wrote:
On 3/25/2022 6:58 PM, Daniele Ceraolo Spurio wrote:
In intel_gt_wait_for_idle, we use the remaining timeout returned from
intel_gt_retire_requests_timeout to wait on the GuC being idle.
However,
On 3/25/22 10:09, Matthew Auld wrote:
During execbuf DG2 currently just hits:
"execbuf with unknown ring: 5"
It looks like the fix is to convert the test over to using the
non-legacy API where we instead fill the ctx with all the physical
engines and then engine/ring becomes the index
v2 of https://patchwork.freedesktop.org/series/101787/ addressing some
review comments from Ville.
Jani Nikula (11):
drm/edid: don't modify EDID while parsing
drm/edid: fix reduced blanking support check
drm/edid: slightly restructure timing and non-timing descriptor
structs
drm/edid:
We'll want to keep the EDID immutable while parsing. Stop modifying the
EDID because of the quirks.
In theory, this does have userspace implications, but the userspace is
supposed to use the modes exposed via KMS API, not by parsing the EDID
directly.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
The reduced blanking bit is valid only for CVT, indicated by display
range limits flags 0x04.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 1b552fe54f38..
The pixel clock is conceptually part of the detailed timings, while it's
just zero padding for display descriptors. Modify the structures to
reflect this. Rename struct detailed_non_pixel to
edid_display_descriptor to better reflect spec while at it. (Further
struct renames are left for follow-up w
Use struct member access instead of direct offsets to avoid lots of
casts all over the place.
Use BUILD_BUG_ON() for sanity check.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 27 ---
1 file changed, 16 insertions(+), 11 deletions(-)
di
Use struct struct detailed_data_monitor_range member access instead of
direct offsets to avoid casting.
Use BUILD_BUG_ON() for sanity check.
v2:
- Rename timing to descriptor (Ville)
- Return and use struct detailed_data_monitor_range
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/g
Use struct detailed_timing member access instead of direct offsets to
avoid casting.
Use BUILD_BUG_ON() for sanity check.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
Note: Why can we use range.formula.cvt.flags directly in is_rb() while
gtf2 functions check for range.flags == 0x02 first
Moving one level higher, constify struct detailed_timing pointers in
callbacks.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 40 --
1 file changed, 21 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/d
Finalize detailed timing parsing constness by making struct edid also
const in callbacks and closure.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 48 +++---
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git a/drivers/
Constify the first level of struct edid in detailed timing parsing. Also
switch to struct edid instead of u8.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 48 ++
1 file changed, 23 insertions(+), 25 deletions(-)
diff --git a/
With this, the remaining non-const parts are the ones that actually
modify the EDID, for example to fix corrupt EDID.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 21 +++--
include/drm/drm_edid.h | 10 +-
2 files changed, 16 insertion
Start constifying the struct detailed_timing pointers being passed
around from bottom up.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 40 +++---
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/drm_
Gentle reminder to review below change.
Thanks,
Tejas
> -Original Message-
> From: Surendrakumar Upadhyay, TejaskumarX
> Sent: 25 March 2022 12:17
> To: intel-gfx@lists.freedesktop.org
> Cc: Roper, Matthew D ; Meena, Mahesh
>
> Subject: RE: [PATCH] drm/i915: Add RPL-S PCI IDs
>
> Can an
> -Original Message-
> From: Intel-gfx On Behalf Of
> Surendrakumar Upadhyay, TejaskumarX
> Sent: Monday, March 28, 2022 2:52 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Add RPL-S PCI IDs
>
> Gentle reminder to review below change.
>
> Thanks,
From: CQ Tang
On some systems lmem can be as large as 16G, which seems to trigger
various CI timeouts, and in the best case just takes a long time. For
the purposes of the test we should be able to limit to 4G, without any
big loss in coverage.
v2:
- No need to try again without the modparam; i
On Mon, Mar 28, 2022 at 10:29:59AM +0100, Matthew Auld wrote:
> From: CQ Tang
>
> On some systems lmem can be as large as 16G, which seems to trigger
> various CI timeouts, and in the best case just takes a long time. For
> the purposes of the test we should be able to limit to 4G, without any
>
On Mon, 28 Mar 2022, Jani Nikula wrote:
> The pixel clock is conceptually part of the detailed timings, while it's
> just zero padding for display descriptors. Modify the structures to
> reflect this. Rename struct detailed_non_pixel to
> edid_display_descriptor to better reflect spec while at it.
From: CQ Tang
On some systems lmem can be as large as 16G, which seems to trigger
various CI timeouts, and in the best case just takes a long time. For
the purposes of the test we should be able to limit to 4G, without any
big loss in coverage.
v2:
- No need to try again without the modparam; i
i915 doesn't use pm_suspend_ignore_children() which warrants that
any runtime active child of i915 will block the runtime suspend
of i915.
i915_runtime_pm_status only exposes i915 runtime pm usage_count,
which is not sufficient to debug in the scenarios when i915 has
zero usage_count but there are
Signed-off-by: Christian König
Signed-off-by: Tejas Upadhyay
---
drivers/dma-buf/dma-fence-array.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/dma-buf/dma-fence-array.c
b/drivers/dma-buf/dma-fence-array.c
index 52b85d292383..5c8a7084577b 100644
--- a/drivers/dma-buf/dma-fen
On Fri, 25 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Get rid of the confusing back and forth between bools and ints
> in the .get_dplls() stuff. Just make everything return an int.
Reviewed-by: Jani Nikula
There was at least one call to bxt_ddi_hdmi_pll_dividers() where the
retu
On Fri, 25 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Stop passing around the drm_device and just pass the
> dev_priv instead.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> drivers/gpu/drm/i915/display/
On Fri, 25 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> All platforms have dpll_funcs. Remove the pointless NULL checks.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 4
> 1 file changed, 4 deletions(-)
>
> d
On Fri, 25 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Pass the full atomic state+crtc rather than the redundant
> crtc+crtc_state pair. We already need the full atomic state
> in the hsw+ codepath anyway.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers
On Fri, 25 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Move some checks into intel_dpll_crtc_compute_clock() from the
> caller. Avoids the caller from having to worry about all this
> crap.
>
> We'll also reorder the hw.enable vs. shared_dpll checks since
> it makes sense to sanity c
On Fri, 25 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> All .crtc_compute_clock() implementations do the same memset() to
> clear the dpll_hw_state (since we preserve it across
> intel_crtc_prepare_cleared_state()). Move the memset() to the common
> wrapper.
>
> Also clear it when we'
On Fri, 25 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Clear the dpll_hw_state when we're about disable the pipe.
> Previously it looks like we just left the old junk in there.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_d
On Fri, 25 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> DG2 doesn't currently used the shared_dpll stuff so let's just
> split it out from hsw_crtc_compute_clock() entirely.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_dpll.
On Fri, 25 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Start splitting the .compute_crtc_clock() into two parts; one
> part does the computation, the second part does the shared dpll
> assignment. I want to move the actual computation part much earlier
> into the compute_config() pha
On Fri, 25 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The debugs in lower level DPLL code don't really provide any
> useful extra information AFAICS. Better just streamline the
> code and just put the necessary debugs (to identify at which
> step the modeset failed) into the higher
On Mon, Mar 28, 2022 at 11:08:59AM +0100, Matthew Auld wrote:
> From: CQ Tang
>
> On some systems lmem can be as large as 16G, which seems to trigger
> various CI timeouts, and in the best case just takes a long time. For
> the purposes of the test we should be able to limit to 4G, without any
>
On Fri, 25 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Split the DPLL state computation into a separate function
> from the current .get_dplls() which currently serves a dual duty
> by also reserving the shared DPLLs.
>
> Signed-off-by: Ville Syrjälä
Didn't do a thorough review yet
On Wed, 23 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> All the other intel_panel functions take struct intel_connector,
> so might as well make init()/fini() take one as well.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/icl_dsi.
On Wed, 23 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Replace all drm_mode_debug_printmodeline() calls with
> DRM_MODE_FMT+DRM_MODE_ARG(). Makes the debug output a bit more
> terse in places where we previously had a newline in the precedeing
> drm_dbg_kms(), and avoids anything els
On Wed, 23 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Pull the drm_connector_set_panel_orientation_with_quirk()
> into intel_edp_add_properties() to match how the DSI encoders
> do it. Less clutter in intel_edp_init_connector() overall.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by
On Wed, 23 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use intel_panel_preferred_fixed_mode() for all the orientation
> quirk setup and compute_is_dual_link_lvds()). All of these
> happen after intel_panel_init() so the panel fixed_mode list
> is already in place.
>
> Signed-off-by:
On Wed, 23 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Rename intel_panel_vbt_fixed_mode() to
> intel_panel_vbt_lfp_fixed_mode() to be more descriptive.
> We'll have another VBT fixed mode function soon and we
> don't want to confuse the two.
>
> Signed-off-by: Ville Syrjälä
Never
On Wed, 23 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We have a function for duplicating the VBT LFP mode. Add the same
> for the VBT SDVO mode.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_panel.c | 20 +++
On Wed, 23 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Apart from the EDID and VBT based mechanism we also sometimes
> use the encoder's current mode as the panel fixed mode. We
> currently have the same code for that duplicated in two places.
> Let's unify.
>
> Signed-off-by: Ville
On Wed, 23 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Despite the name intel_panel_edid_fixed_mode() doesn't actually
> look in the EDID. All it does is dig out the preferred mode from
> the connector's probed_modes list. That is also what the SDVO
> LVDS code is doing by hand. Let'
On Wed, 23 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> SDVO is the only connector type currently returning the VBT
> fixed mode directly from .get_modes(), everyone else just
> adds it to the fixed_modes list and then returns that from
> .get_modes(). Adjust SDVO to follow the common
Hi Jani,
I love your patch! Perhaps something to improve:
[auto build test WARNING on drm/drm-next]
[also build test WARNING on drm-intel/for-linux-next drm-tip/drm-tip v5.17
next-20220328]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we
On Fri, Mar 25, 2022 at 04:08:01PM +, Patchwork wrote:
> == Series Details ==
>
> Series: Remove check for ComboPHY I/O voltage for DP source rate (rev5)
> URL : https://patchwork.freedesktop.org/series/96293/
> State : success
Thanks for the patchset, pushed.
>
> == Summary ==
>
> CI Bu
Hi Jani,
I love your patch! Yet something to improve:
[auto build test ERROR on drm/drm-next]
[also build test ERROR on drm-intel/for-linux-next drm-tip/drm-tip v5.17
next-20220328]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to
From: Tvrtko Ursulin
Continuation of the effort to declutter i915_drv.h.
Also, component specific helpers which consult the iommu/virtualization
helpers moved to respective component source/header files as appropriate.
Signed-off-by: Tvrtko Ursulin
Cc: Jani Nikula
Cc: Lucas De Marchi
Acked-b
Hi Jani,
I love your patch! Yet something to improve:
[auto build test ERROR on drm/drm-next]
[also build test ERROR on drm-intel/for-linux-next drm-tip/drm-tip v5.17
next-20220328]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to
Looks like somebody is creating an empty dma_fence_array.
Signed-off-by: Christian König
---
drivers/dma-buf/dma-fence-array.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/dma-buf/dma-fence-array.c
b/drivers/dma-buf/dma-fence-array.c
index 52b85d292383..5c8a7084577b 100644
-
NING on drm/drm-next]
> [also build test WARNING on drm-intel/for-linux-next drm-tip/drm-tip v5.17
> next-20220328]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https
On Mon, 28 Mar 2022, Jani Nikula wrote:
> v2 of https://patchwork.freedesktop.org/series/101787/ addressing some
> review comments from Ville.
Please ignore this series.
>
> Jani Nikula (11):
> drm/edid: don't modify EDID while parsing
> drm/edid: fix reduced blanking support check
> drm/e
On 21.03.2022 16:07, Lucas De Marchi wrote:
> Now Cc'ing Daniel properly
>
> Lucas De Marchi
>
> On Mon, Mar 21, 2022 at 04:00:56PM -0700, Lucas De Marchi wrote:
> > +Thomas Zimmermann and +Daniel Vetter
> >
> > Could you take a look below regarding the I/O to I/O memory access?
> >
> > On Thu,
v3 of https://patchwork.freedesktop.org/series/101787/ and
https://patchwork.freedesktop.org/series/101862/
I screwed up with the struct renamings in v2, so there's some falling
back to v1 and general confusion here. Sorry.
BR,
Jani.
Jani Nikula (12):
drm/edid: don't modify EDID while parsing
The reduced blanking bit is valid only for CVT, indicated by display
range limits flags 0x04.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
i
We'll want to keep the EDID immutable while parsing. Stop modifying the
EDID because of the quirks.
In theory, this does have userspace implications, but the userspace is
supposed to use the modes exposed via KMS API, not by parsing the EDID
directly.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
Use struct member access instead of direct offsets to avoid lots of
casts all over the place.
Use BUILD_BUG_ON() for sanity check.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 27 ---
1 file changed, 16 insertions(+), 11 deletions(-)
di
Use struct detailed_timing member access instead of direct offsets to
avoid casting.
Use BUILD_BUG_ON() for sanity check.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/d
Moving one level higher, constify struct detailed_timing pointers in
callbacks.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 40 --
1 file changed, 21 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/d
Use struct member access instead of direct offsets to avoid a cast.
Use BUILD_BUG_ON() for sanity check.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/
Use struct detailed_timing member access instead of direct offsets to
avoid casting.
Use BUILD_BUG_ON() for sanity check.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 57 +-
1 file changed, 37 insertions(+), 20 deletions(-)
Constify the first level of struct edid in detailed timing parsing. Also
switch to struct edid instead of u8.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 48 ++
1 file changed, 23 insertions(+), 25 deletions(-)
diff --git a/
Finalize detailed timing parsing constness by making struct edid also
const in callbacks and closure.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 48 +++---
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git a/drivers/
Start constifying the struct detailed_timing pointers being passed
around from bottom up.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 40 +++---
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/drm_
With this, the remaining non-const parts are the ones that actually
modify the EDID, for example to fix corrupt EDID.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 21 +++--
include/drm/drm_edid.h | 10 +-
2 files changed, 16 insertion
Reduce the size of the function that actually modifies the EDID.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 42 ++
1 file changed, 24 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index d1
== Series Details ==
Series: drm/edid: constify EDID parsing, with some fixes
URL : https://patchwork.freedesktop.org/series/101862/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
6bf277e7683e drm/edid: don't modify EDID while parsing
29064813a1c5 drm/edid: fix reduced blanking
== Series Details ==
Series: drm/edid: constify EDID parsing, with some fixes
URL : https://patchwork.freedesktop.org/series/101862/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not
found
== Series Details ==
Series: drm/edid: constify EDID parsing, with some fixes
URL : https://patchwork.freedesktop.org/series/101862/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11411 -> Patchwork_22694
Summary
---
We need add some checks around DMC reloading to
prevents the rare possibility of some adversary
writing to a random mmio register
BSpec: 49193
Cc: Imre Deak
Signed-off-by: Anusha Srivatsa
---
.../drm/i915/display/intel_display_power.c| 23 +++
drivers/gpu/drm/i915/i915_reg.
On Mon, Mar 28, 2022 at 09:44:36AM +0100, Tvrtko Ursulin wrote:
>
> + Joonas
>
> On 25/03/2022 23:03, Francisco Jerez wrote:
> > Matt Atwood writes:
> >
> > > Newer platforms have DSS that aren't necessarily available for both
> > > geometry and compute, two queries will need to exist. This int
Provide accurate max bw information for DG2
cc: Ville Syrjälä
cc: Stanislav Lisovskiy
Vinod Govindapillai (1):
drm/i915: Handle the DG2 max bw properly
drivers/gpu/drm/i915/display/intel_bw.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
--
2.25.1
DG2 has a constant bandwidth regardless of the number of planes
enabled. Handle the DG2 bw separately.
cc: Ville Syrjälä
cc: Stanislav Lisovskiy
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_bw.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
== Series Details ==
Series: drm/i915/debugfs: Dump i915 children runtime status
URL : https://patchwork.freedesktop.org/series/101866/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not
fo
On Mon, Mar 28, 2022 at 12:17:16PM +0300, Jani Nikula wrote:
> The reduced blanking bit is valid only for CVT, indicated by display
> range limits flags 0x04.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/drm_edid.c | 2 +-
> 1 file changed, 1 insertion(+),
On Mon, Mar 28, 2022 at 07:10:25PM +0300, Vinod Govindapillai wrote:
> DG2 has a constant bandwidth regardless of the number of planes
> enabled. Handle the DG2 bw separately.
>
> cc: Ville Syrjälä
> cc: Stanislav Lisovskiy
>
> Signed-off-by: Vinod Govindapillai
> ---
> drivers/gpu/drm/i915/d
== Series Details ==
Series: dma-buf: Check for empty dma_fence_array
URL : https://patchwork.freedesktop.org/series/101867/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a933bca7bc97 dma-buf: Check for empty dma_fence_array
-:10: WARNING:COMMIT_MESSAGE: Missing commit descript
== Series Details ==
Series: dma-buf: Check for empty dma_fence_array
URL : https://patchwork.freedesktop.org/series/101867/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not
found
./drive
== Series Details ==
Series: drm/i915/debugfs: Dump i915 children runtime status
URL : https://patchwork.freedesktop.org/series/101866/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11412 -> Patchwork_22695
Summary
---
> -Original Message-
> From: Ville Syrjälä
> Sent: Thursday, March 24, 2022 6:31 PM
> To: Shankar, Uma
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [v4] drm/i915/display: Extend DP HDR support to hsw+
>
> On Thu, Mar 24, 2022 at 05:34:38PM +0530, Uma Shankar wrote:
> > HSW+ pl
Hi,
Yes, the series doesn't need an update, but on the other hand I don't
think we can update the config repo before the new config option is
merged, which we can't do without first running CI with the config
enabled, so we have a catch-22 situation. That's why I suggested that
you resend the
== Series Details ==
Series: dma-buf: Check for empty dma_fence_array
URL : https://patchwork.freedesktop.org/series/101867/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11412 -> Patchwork_22696
Summary
---
**FAILUR
From: Fei Yang
GPU hangs have been observed when multiple engines write to the
same aux_inv register at the same time. To avoid this each engine
should only invalidate its own auxiliary table. The function
gen12_emit_flush_xcs() currently invalidate the auxiliary table for
all engines because the
From: Chris Wilson
In order to keep the context image parser simple, we assume that all
commands follow a similar format. A few, especially not MI commands on
the render engines, have fixed lengths not encoded in a length field.
This caused us to incorrectly skip over 3D state commands, and start
From: Chris Wilson
When testing whether we can get the GPU to leak information about
non-privileged state, we first need to ensure that the output buffer is
set to a known value as the HW may opt to skip the write into memory for
a non-privileged read of a sensitive register. We chose POISON_INUS
From: Chris Wilson
Ensure that we always signal the semaphore when timing out, so that if it
happens to be stuck waiting for the semaphore we will quickly recover
without having to wait for a reset.
Reported-by: CQ Tang
Signed-off-by: Chris Wilson
Cc: CQ Tang
cc: Joonas Lahtinen
Signed-off-b
From: Chris Wilson
Even though the initial protocontext we load onto HW has the register
cleared, by the time we save it into the default image, BB_OFFSET has
had the enable bit set. Reclear BB_OFFSET for each new context.
Testcase: igt/i915_selftests/gt_lrc
Signed-off-by: Chris Wilson
Cc: Mik
On Mon, Mar 28, 2022 at 05:34:23PM +0300, Jani Nikula wrote:
> The reduced blanking bit is valid only for CVT, indicated by display
> range limits flags 0x04.
>
> Cc: Ville Syrjälä
> Signed-off-by: Jani Nikula
Let's repeat here in so it doesn't get lost.
Reviewed-by: Ville Syrjälä
> ---
> dr
On Mon, Mar 28, 2022 at 05:34:24PM +0300, Jani Nikula wrote:
> Use struct member access instead of direct offsets to avoid lots of
> casts all over the place.
>
> Use BUILD_BUG_ON() for sanity check.
>
> Cc: Ville Syrjälä
> Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
> ---
> drive
On Mon, Mar 28, 2022 at 05:34:25PM +0300, Jani Nikula wrote:
> Use struct member access instead of direct offsets to avoid a cast.
>
> Use BUILD_BUG_ON() for sanity check.
>
> Cc: Ville Syrjälä
> Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/drm_edid.c | 8 ++
On Mon, Mar 28, 2022 at 05:34:26PM +0300, Jani Nikula wrote:
> Use struct detailed_timing member access instead of direct offsets to
> avoid casting.
>
> Use BUILD_BUG_ON() for sanity check.
>
> Cc: Ville Syrjälä
> Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/dr
On Mon, Mar 28, 2022 at 05:34:27PM +0300, Jani Nikula wrote:
> Use struct detailed_timing member access instead of direct offsets to
> avoid casting.
>
> Use BUILD_BUG_ON() for sanity check.
>
> Cc: Ville Syrjälä
> Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/dr
On Mon, Mar 28, 2022 at 05:34:28PM +0300, Jani Nikula wrote:
> Start constifying the struct detailed_timing pointers being passed
> around from bottom up.
>
> Cc: Ville Syrjälä
> Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/drm_edid.c | 40 +++
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