> -Original Message-
> From: C, Ramalingam
> Sent: Tuesday, February 15, 2022 11:22 AM
> To: intel-gfx ; dri-devel de...@lists.freedesktop.org>
> Cc: Ville Syrjälä ; Shankar, Uma
> ; Roper, Matthew D ;
> Dhanavanthri, Swathi ; De Marchi, Lucas
> ; Souza, Jose ; C, Ramalingam
>
> Subjec
> -Original Message-
> From: C, Ramalingam
> Sent: Tuesday, February 15, 2022 11:22 AM
> To: intel-gfx ; dri-devel de...@lists.freedesktop.org>
> Cc: Ville Syrjälä ; Shankar, Uma
> ; Roper, Matthew D ;
> Srivatsa, Anusha ; Souza, Jose
> ; C, Ramalingam
> Subject: [PATCH 2/3] drm/i915/d
> -Original Message-
> From: C, Ramalingam
> Sent: Tuesday, February 15, 2022 11:22 AM
> To: intel-gfx ; dri-devel de...@lists.freedesktop.org>
> Cc: Ville Syrjälä ; Shankar, Uma
> ; Hogander, Jouni ; C,
> Ramalingam
> Subject: [PATCH 3/3] drm/i915: Fix for PHY_MISC_TC1 offset
>
> Fro
== Series Details ==
Series: drm/mm: Add an iterator to optimally walk over holes suitable for an
allocation
URL : https://patchwork.freedesktop.org/series/100136/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11230_full -> Patchwork_22273_full
===
On 2/15/22 12:20 PM, Nikula, Jani wrote:
> As the excessive #includes from i915_drv.h were axed, kvmgt.c build
> started failing. Add the necessary #include where needed.
>
> Reported-by: Stephen Rothwell
> Fixes: 14da21cc4671 ("drm/i915: axe lots of unnecessary includes from
> i915_drv.h")
> Cc
On Tue, Feb 15, 2022 at 07:25:36PM -0800, Navare, Manasi wrote:
> On Tue, Feb 15, 2022 at 08:31:57PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Adjust the cursor dst coordinates appripriately when it's on
> > the bigjoiner slave pipe. intel_atomic_plane_check_clipping()
> > alrea
On Mon, Feb 14, 2022 at 10:13:41PM -0800, Matt Roper wrote:
> A few of our MCH registers are defined with absolute register offsets.
> For consistency, let's switch their definitions to be relative offsets
> from MCHBAR_MIRROR_BASE.
>
> Cc: Ville Syrjälä
> Suggested-by: Ville Syrjälä
> Signed-of
On Mon, Feb 14, 2022 at 10:13:42PM -0800, Matt Roper wrote:
> Registers that exist within the MCH BAR and are mirrored into the GPU's
> MMIO space are a good candidate to separate out into their own header.
>
> For reference, the mirror of the MCH BAR starts at the following
> locations in the gra
On Tue, Feb 15, 2022 at 11:21:54AM +0530, Ramalingam C wrote:
> From: Jouni Högander
>
> Currently ICL_PHY_MISC macro is returning offset 0x64C10 for PHY_E
> port. Correct offset is 0x64C14.
Why is it PHY_E and not PHY_F?
>
> Fix this by handling PHY_E port seprately.
>
> Signed-off-by: Matt
On Tue, 15 Feb 2022, Andy Shevchenko wrote:
> On Tue, Feb 15, 2022 at 07:14:49PM +0200, Jani Nikula wrote:
>> On Tue, 15 Feb 2022, Andy Shevchenko
>> wrote:
>> > It's hard to parse for-loop which has some magic calculations inside.
>> > Much cleaner to use while-loop directly.
>>
>> I assume yo
On Wed, 16 Feb 2022, Jiapeng Chong wrote:
> Eliminate the follow smatch warning:
>
> drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:4640
> guc_create_virtual() warn: assigning (-2) to unsigned variable
> 've->base.instance'.
>
> drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:4641
> guc_creat
On Wed, Feb 16, 2022 at 9:55 AM Jani Nikula wrote:
> On Tue, 15 Feb 2022, Andy Shevchenko
> wrote:
> > On Tue, Feb 15, 2022 at 07:14:49PM +0200, Jani Nikula wrote:
> >> On Tue, 15 Feb 2022, Andy Shevchenko
> >> wrote:
> >> > It's hard to parse for-loop which has some magic calculations inside.
Add helper functions for calculating FRL capacity and DFM
requirements with given compressed bpp.
v2: Fixed:
-Build warnings/errors: Removed unused variables.
-Checkpatch warnings.
Signed-off-by: Ankit Nautiyal
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/drm_frl_dfm_helper.c | 303
On Wed, Feb 16, 2022 at 11:02:06AM +0200, Jani Nikula wrote:
> On Wed, 16 Feb 2022, Jiapeng Chong wrote:
> > Eliminate the follow smatch warning:
> >
> > drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:4640
> > guc_create_virtual() warn: assigning (-2) to unsigned variable
> > 've->base.instance
== Series Details ==
Series: drm/i915/guc: Initialize GuC submission locks and queues early
URL : https://patchwork.freedesktop.org/series/100138/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11230_full -> Patchwork_22274_full
=
On Fri, 11 Feb 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Exfiltrate intel_plane_atomic_calc_changes() and its friends from
> intel_display.c to intel_atomic_plane.c since that is a much better
> fit.
>
> While at it also nuke the official looking kernel docs for
> intel_wm_need_update(
On Wed, 2022-02-16 at 10:50 +0200, Ville Syrjälä wrote:
> On Tue, Feb 15, 2022 at 11:21:54AM +0530, Ramalingam C wrote:
> > From: Jouni Högander
> >
> > Currently ICL_PHY_MISC macro is returning offset 0x64C10 for PHY_E
> > port. Correct offset is 0x64C14.
>
> Why is it PHY_E and not PHY_F?
Thi
On Fri, 11 Feb 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> No reason the high level intel_update_crtc() needs to know
> that there is something magical about the commit order of
> planes between different platforms. So let's hide that
> detail even better.
>
> Signed-off-by: Ville Syrjäl
On Fri, 11 Feb 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Add another plane bitmask, this time tracking which planes are
> scaled. This is going to be useful in ILK watermark computations,
> and skl+ pipe scaler assignments.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
On Fri, 11 Feb 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use the {active,scaled}_planes bitmasks from the crtc state
> rather than poking at the plane state directly. One step
> towards eliminating the last use of the somewhat questionble
> intel_atomic_crtc_state_for_each_plane_state(
On Fri, 11 Feb 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> snb_wm_latency_quirk() already boosts up the latency values
> so the extra warning about the SSKPD value being insufficient
> is now redundant. Drop it.
>
> Signed-off-by: Ville Syrjälä
I just might not understand what's going
On 16/02/2022 09:19, Ville Syrjälä wrote:
On Wed, Feb 16, 2022 at 11:02:06AM +0200, Jani Nikula wrote:
On Wed, 16 Feb 2022, Jiapeng Chong wrote:
Eliminate the follow smatch warning:
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:4640
guc_create_virtual() warn: assigning (-2) to unsigned
On Fri, 11 Feb 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We treat SSKPD as a 64 bit register. Add the support macros
> to define/extract bits in such registers.
>
> v2: Fix 32bit builds
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_reg
On Wed, Feb 16, 2022 at 09:36:02AM +, Hogander, Jouni wrote:
> On Wed, 2022-02-16 at 10:50 +0200, Ville Syrjälä wrote:
> > On Tue, Feb 15, 2022 at 11:21:54AM +0530, Ramalingam C wrote:
> > > From: Jouni Högander
> > >
> > > Currently ICL_PHY_MISC macro is returning offset 0x64C10 for PHY_E
>
On Wed, Feb 16, 2022 at 11:54:00AM +0200, Jani Nikula wrote:
> On Fri, 11 Feb 2022, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > snb_wm_latency_quirk() already boosts up the latency values
> > so the extra warning about the SSKPD value being insufficient
> > is now redundant. Drop it.
> >
On Fri, 11 Feb 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Give names to the SSKPD/MLTR fields, and use the
> REG_GENMASK* and REG_FIELD_GET*.
>
> Also drop the bogus non-mirrored SSKP register define.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm
== Series Details ==
Series: drm/i915/perf: Skip the i915_perf_init for dg2
URL : https://patchwork.freedesktop.org/series/100150/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11230_full -> Patchwork_22276_full
Summary
---
On Fri, 11 Feb 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use REG_GENMASK() & co. for ilk+ watermarm registers.
*watermark
>
> Signed-off-by: Ville Syrjälä
> ---
> .../drm/i915/display/intel_display_debugfs.c | 2 +-
> drivers/gpu/drm/i915/i915_reg.h | 41 +++
On Wed, 16 Feb 2022, Tvrtko Ursulin wrote:
> On 16/02/2022 09:19, Ville Syrjälä wrote:
>> On Wed, Feb 16, 2022 at 11:02:06AM +0200, Jani Nikula wrote:
>>> On Wed, 16 Feb 2022, Jiapeng Chong wrote:
Eliminate the follow smatch warning:
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.
On Wed, Feb 16, 2022 at 12:29:52PM +0200, Jani Nikula wrote:
> On Fri, 11 Feb 2022, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Use REG_GENMASK() & co. for ilk+ watermarm registers.
>
> *watermark
>
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > .../drm/i915/display/intel_display_d
On 2/16/2022 12:02 AM, Ville Syrjala wrote:
From: Ville Syrjälä
Since we now have the bigjoiner_pipes bitmask the boolean
is redundant. Get rid of it.
Also, populating bigjoiner_pipes already during
encoder->compute_config() allows us to use it much earlier
during the state calculation as we
On Wed, Feb 16, 2022 at 04:27:49PM +0530, Nautiyal, Ankit K wrote:
>
> On 2/16/2022 12:02 AM, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Since we now have the bigjoiner_pipes bitmask the boolean
> > is redundant. Get rid of it.
> >
> > Also, populating bigjoiner_pipes already during
> >
On Wed, Feb 09, 2022 at 11:19:27AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Make sure we don't assign an error pointer to crtc_state->mode_blob
> as that will break all kinds of places that assume either NULL or a
> valid pointer (eg. drm_property_blob_put()).
>
> Reported-by: fuyuf
== Series Details ==
Series: series starting with [v2,1/2] drm/i915: Define MCH registers relative
to MCHBAR_MIRROR_BASE
URL : https://patchwork.freedesktop.org/series/100153/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11230_full -> Patchwork_22278_full
===
On 2/16/2022 4:34 PM, Ville Syrjälä wrote:
On Wed, Feb 16, 2022 at 04:27:49PM +0530, Nautiyal, Ankit K wrote:
On 2/16/2022 12:02 AM, Ville Syrjala wrote:
From: Ville Syrjälä
Since we now have the bigjoiner_pipes bitmask the boolean
is redundant. Get rid of it.
Also, populating bigjoiner_pi
On Tue, Feb 15, 2022 at 08:32:05PM +0200, Ville Syrjala wrote:
> @@ -2788,8 +2788,9 @@ static void intel_crtc_readout_derived_state(struct
> intel_crtc_state *crtc_state
> /* Populate the "user" mode with full numbers */
> drm_mode_copy(mode, pipe_mode);
> intel_mode_from_crtc_ti
On 15/02/2022 16:39, Ceraolo Spurio, Daniele wrote:
On 2/15/2022 1:09 AM, Tvrtko Ursulin wrote:
On 15/02/2022 01:11, Daniele Ceraolo Spurio wrote:
Move initialization of submission-related spinlock, lists and workers to
init_early. This fixes an issue where if the GuC init fails we might
sti
On Tue, 15 Feb 2022 at 16:37, Simon Ser wrote:
>
> On Tuesday, February 15th, 2022 at 15:38, Emil Velikov
> wrote:
>
> > On Tue, 15 Feb 2022 at 13:55, Simon Ser wrote:
> > >
> > > On Tuesday, February 15th, 2022 at 13:04, Emil Velikov
> > > wrote:
> > >
> > > > Greetings everyone,
> > > >
> >
On 15/02/2022 15:22, Usyskin, Alexander wrote:
+{
+ irq_set_chip_and_handler_name(irq, &gsc_irq_chip,
+ handle_simple_irq, "gsc_irq_handler");
+
+ return irq_set_chip_data(irq, dev_priv);
I am not familiar with this interrupt scheme - does dev
== Series Details ==
Series: iommu/vt-d: Add RPLS to quirk list to skip TE disabling
URL : https://patchwork.freedesktop.org/series/100165/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11230_full -> Patchwork_22280_full
Su
LGTM.
Reviewed-by: Ankit Nautiyal
On 2/16/2022 12:02 AM, Ville Syrjala wrote:
From: Ville Syrjälä
Replace the hardcoded 2 pipe assumptions when we're massaging
pipe_mode and the pipe_src rect to be suitable for bigjoiner.
Instead we can just count the number of pipes in the bitmask.
Signed-
On Tue, Feb 15, 2022 at 08:32:07PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Replace the hardcoded 2 pipe assumptions when we're massaging
> pipe_mode and the pipe_src rect to be suitable for bigjoiner.
> Instead we can just count the number of pipes in the bitmask.
>
> Signed-off-by
On Wed, Feb 16, 2022 at 11:38:44AM +0200, Jani Nikula wrote:
> On Fri, 11 Feb 2022, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > No reason the high level intel_update_crtc() needs to know
> > that there is something magical about the commit order of
> > planes between different platforms.
On 2/16/2022 12:01 AM, Ville Syrjala wrote:
From: Ville Syrjälä
We just copied over the whole master crtc state, including
cpu_transcoder+has_audio. No need to copy those again.
Also get rid of the unhelpful comment.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dis
On Wed, 16 Feb 2022, Ville Syrjälä wrote:
> On Wed, Feb 16, 2022 at 11:38:44AM +0200, Jani Nikula wrote:
>> On Fri, 11 Feb 2022, Ville Syrjala wrote:
>> > From: Ville Syrjälä
>> >
>> > No reason the high level intel_update_crtc() needs to know
>> > that there is something magical about the commi
A new programming step was added to combo and TC PLL sequences.
If override_AFC_startup is set in VBT, driver should overwrite
AFC_startup value to 0x0 or 0x7 in PLL's div0 register.
The current understating is that only TGL needs this and all other
display 12 and newer platforms will have a older
On Tue, 2022-02-15 at 15:47 +0200, Lisovskiy, Stanislav wrote:
> On Thu, Feb 10, 2022 at 10:52:23AM -0800, José Roberto de Souza wrote:
> > PSR2 workaround required when mode has delayed vblank.
> >
> > BSpec: 52890
> > BSpec: 49421
> > Cc: Jouni Högander
> > Signed-off-by: José Roberto de Souza
On Tue, 2022-02-15 at 12:31 +, Hogander, Jouni wrote:
> On Thu, 2022-02-10 at 10:52 -0800, José Roberto de Souza wrote:
> > PSR2 workaround required when mode has delayed vblank.
> >
> > BSpec: 52890
> > BSpec: 49421
> > Cc: Jouni Högander
> > Signed-off-by: José Roberto de Souza
> > ---
> >
On Wed, 2022-02-16 at 12:07 +0200, Ville Syrjälä wrote:
> On Wed, Feb 16, 2022 at 09:36:02AM +, Hogander, Jouni wrote:
> > On Wed, 2022-02-16 at 10:50 +0200, Ville Syrjälä wrote:
> > > On Tue, Feb 15, 2022 at 11:21:54AM +0530, Ramalingam C wrote:
> > > > From: Jouni Högander
> > > >
> > > > C
On Wed, Feb 16, 2022 at 02:11:54PM +, Hogander, Jouni wrote:
> On Wed, 2022-02-16 at 12:07 +0200, Ville Syrjälä wrote:
> > On Wed, Feb 16, 2022 at 09:36:02AM +, Hogander, Jouni wrote:
> > > On Wed, 2022-02-16 at 10:50 +0200, Ville Syrjälä wrote:
> > > > On Tue, Feb 15, 2022 at 11:21:54AM +0
The VBT DSI video transfer mode field values have been defined in terms
of the VLV MIPI_VIDEO_MODE_FORMAT register. The ICL DSI code maps that
to ICL DSI_TRANS_FUNC_CONF() register. The values are the same, though
the shift is different.
Make a clean break and disassociate the values from each oth
The VLV (including CHV, BXT, and GLK) DSI registers have fairly isolated
usage. Split the register macros to separated files.
Cc: Matt Roper
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 3 +-
drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 1 +
drivers/gpu/
The ICL DSI registers have fairly isolated usage. Split the register
macros to a separate file.
Cc: Matt Roper
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/icl_dsi.c | 1 +
drivers/gpu/drm/i915/display/icl_dsi_regs.h | 342
drivers/gpu/drm/i915/i915_ir
Having a separate definition will be useful for splitting VLV and ICL
register files.
Cc: Matt Roper
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h| 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/
Reviewed-by: Caz Yokoyama
-caz
On Tue, 2022-02-15 at 13:45 -0800, Matt Roper wrote:
> DG2 hardware will start showing up in CI shortly; let's make sure
> it's
> recognized by the driver.
>
> Bspec: 44477
> Cc: Rodrigo Vivi
> Cc: Jani Nikula
> Cc: Joonas Lahtinen
> Cc: Tvrtko Ursulin
> Signed
On Tue, Feb 15, 2022 at 10:17:40AM -0800, Kees Cook wrote:
> On Tue, Feb 15, 2022 at 11:47:43AM -0600, Gustavo A. R. Silva wrote:
> > There is a regular need in the kernel to provide a way to declare
> > having a dynamically sized set of trailing elements in a structure.
> > Kernel code should alwa
Eliminate the follow smatch warning:
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:4640
guc_create_virtual() warn: assigning (-2) to unsigned variable
've->base.instance'.
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:4641
guc_create_virtual() warn: assigning (-2) to unsigned variable
've
On Mon, Feb 14, 2022 at 11:58:20AM -0800, Tong Zhang wrote:
> drm/i915 adds some extra cflags, namely -Wall, which causes
> instances of -Wformat-security to appear when building with clang, even
> though this warning is turned off kernel-wide in the main Makefile:
>
> > drivers/gpu/drm/i915/gt/in
There is a regular need in the kernel to provide a way to declare
having a dynamically sized set of trailing elements in a structure.
Kernel code should always use “flexible array members”[1] for these
cases. The older style of one-element or zero-length arrays should
no longer be used[2].
This co
On Tue, Feb 15, 2022 at 09:19:29PM +0200, Leon Romanovsky wrote:
> On Tue, Feb 15, 2022 at 01:21:10PM -0600, Gustavo A. R. Silva wrote:
> > On Tue, Feb 15, 2022 at 10:17:40AM -0800, Kees Cook wrote:
> > > On Tue, Feb 15, 2022 at 11:47:43AM -0600, Gustavo A. R. Silva wrote:
> > >
> > > These all lo
> -Original Message-
> From: Tvrtko Ursulin
> Sent: Wednesday, February 16, 2022 14:04
> To: Usyskin, Alexander ; Greg Kroah-
> Hartman ; Jani Nikula
> ; Joonas Lahtinen
> ; Vivi, Rodrigo ;
> David Airlie ; Daniel Vetter
> Cc: linux-ker...@vger.kernel.org; Winkler, Tomas
> ; Lubart, Vit
When running the mock selftests we currently blow up with:
<6> [299.836278] i915: Running
i915_gem_huge_page_mock_selftests/igt_mock_memory_region_huge_pages
<1> [299.836356] BUG: kernel NULL pointer dereference, address: 00c8
<1> [299.836361] #PF: supervisor read access in kernel mod
original: https://patchwork.freedesktop.org/series/99378/
v2: https://patchwork.freedesktop.org/series/99711/#rev1,
https://patchwork.freedesktop.org/series/99711/#rev2
Main changes from previous version:
- Unrelated patches to iosys-map conversion have landed
- Remove unecess
Convert intel_guc_ads_create() and initialization to use iosys_map
rather than plain pointer and save it in the guc struct. This will help
with additional updates to the ads_blob after the
creation/initialization by abstracting the IO vs system memory.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Dan
Add helpers on top of iosys_map_read_field() /
iosys_map_write_field() functions so they always use the right
arguments and make code easier to read.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De M
In certain situations it's useful to be able to write to an
offset of the mapping. Add a dst_offset to iosys_map_memcpy_to().
Cc: Sumit Semwal
Cc: Christian König
Cc: Thomas Zimmermann
Cc: dri-de...@lists.freedesktop.org
Cc: linux-ker...@vger.kernel.org
Signed-off-by: Lucas De Marchi
Reviewed-
Add a variant of shmem_read() that takes a iosys_map pointer rather
than a plain pointer as argument. It's mostly a copy __shmem_rw() but
adapting the api and removing the write support since there's currently
only need to use iosys_map as destination.
Reworking __shmem_rw() to share the implement
Use the saved ads_map to prepare the golden context. One difference from
the init context is that this function can be called before there is a
gem object (and thus the guc->ads_map) to calculare the size of the
golden context that should be allocated for that object.
So in this case the function
Now the map is saved during creation, so use it to initialize the
golden context, reading from shmem and writing to either system or IO
memory.
v2: Do not use a map iterator: add an offset to keep track of
destination
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc:
Use iosys_map to write the fields ads.capture_*.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 10 +-
1 file changed, 5 insertions(
Use iosys_map to read fields from the dma_blob so access to IO and
system memory is abstracted away.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Atwood
---
drivers/gpu/
In the other places in this function, guc->ads_map is being protected
from access when it's not yet set. However the last check is actually
about guc->ads_golden_ctxt_size been set before. These checks should
always match as the size is initialized on the first call to
guc_prep_golden_context(), b
Use iosys_map to write the policies update so access to IO and system
memory is abstracted away.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Atwood
---
drivers/gpu/drm
Now that all the called functions from __guc_ads_init() are converted to
use ads_map, stop using ads_blob in __guc_ads_init().
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
---
drivers/gpu
Use iosys_map_memset() to zero the private data as ADS may be either
on system or IO memory.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c |
First the simplest ones:
- iosys_map_memset(): when abstracting system and I/O memory,
just like the memcpy() use case, memset() also has dedicated
functions to be called for using IO memory.
- iosys_map_memcpy_from(): we may need to copy data from I/O
Now we have the access to content of GuC ADS either using iosys_map
API or using a temporary buffer. Remove guc->ads_blob as there shouldn't
be updates using the bare pointer anymore.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo
Now that the regset list is prepared, convert guc_mmio_reg_state_init()
to use iosys_map to copy the array to the final location and
initialize additional fields in ads.reg_state_list.
v2: Just use an offset instead of temporary iosys_map.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Use iosys_map to write the fields system_info.mapping_table[][].
Since we already have the info_map around where needed, just use it
instead of going through guc->ads_map.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Sig
From: Ville Syrjälä
While pokingaround the watermarks/etc. I noticed our SAGV code
has a bunch of bugs. Let's try to fix it.
Pushed a few patches from v1 already. And based on the discussion
with Stan I added a few extra refactoring patches to the end in the
hopes of making the logic less confus
From: Ville Syrjälä
When changing between SAGV vs. no SAGV on tgl+ we have to
update the use_sagv_wm flag for all the crtcs or else
an active pipe not already in the state will end up using
the wrong watermarks. That is especially bad when we end up
with the tighter non-SAGV watermarks with SAGV
From: Ville Syrjälä
If the only thing that is changing is SAGV vs. no SAGV but
the number of active planes and the total data rates end up
unchanged we currently bail out of intel_bw_atomic_check()
early and forget to actually compute the new WGV point
mask and thus won't actually enable/disable
From: Ville Syrjälä
To further reduce the confusion between the pre-icl vs. icl+
SAGV codepaths let's do a full split.
Cc: Stanislav Lisovskiy
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 120
1 file changed, 77 insertions(+), 43 deletion
From: Ville Syrjälä
Add some debugs on what exactly we're doing to the QGV point mask
in the icl+ sagv pre/post plane update hooks. Currently we're just
guessing.
v2: s/u32/u16/ for consistency with the mask sizes (Stan)
Reviewed-by: Stanislav Lisovskiy
Signed-off-by: Ville Syrjälä
---
drive
From: Ville Syrjälä
Declutter intel_bw_atomic_check() a bit by pulling
the max QGV mask calculation out.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bw.c | 35 -
1 file changed, 22 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915
From: Ville Syrjälä
Extract the data rate calculation loop out from
intel_bw_atomic_check() to make it a bit less confusing.
Cc: Stanislav Lisovskiy
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bw.c | 63 +++--
1 file changed, 37 insertions(+), 26 de
== Series Details ==
Series: drm/i915/gvt: #include drm_edid.h for drm_edid_block_valid()
URL : https://patchwork.freedesktop.org/series/100169/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11236 -> Patchwork_22281
Summary
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/fbdev: add
intel_fbdev_framebuffer() helper
URL : https://patchwork.freedesktop.org/series/100170/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b96b00c05a02 drm/i915/fbdev: add intel_fbdev_framebuffer() helpe
SLPC unset param H2G only needs one parameter - the id of the
param.
Fixes: 025cb07bebfa ("drm/i915/guc/slpc: Cache platform frequency limits")
Suggested-by: Umesh Nerlige Ramappa
Signed-off-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 2 +-
1 file changed, 1 insertio
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/fbdev: add
intel_fbdev_framebuffer() helper
URL : https://patchwork.freedesktop.org/series/100170/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11236 -> Patchwork_22282
==
== Series Details ==
Series: DGFX OpRegion (rev2)
URL : https://patchwork.freedesktop.org/series/99738/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
6d79d75ff620 drm/i915/opregion: Add intel_opregion_init() wrapper
768f0a166cf5 drm/i915/opregion: Abstract opregion function
-:2
== Series Details ==
Series: DGFX OpRegion (rev2)
URL : https://patchwork.freedesktop.org/series/99738/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Tue, Feb 15, 2022 at 8:24 PM Gustavo A. R. Silva
wrote:
>
> On Tue, Feb 15, 2022 at 09:19:29PM +0200, Leon Romanovsky wrote:
> > On Tue, Feb 15, 2022 at 01:21:10PM -0600, Gustavo A. R. Silva wrote:
> > > On Tue, Feb 15, 2022 at 10:17:40AM -0800, Kees Cook wrote:
> > > > On Tue, Feb 15, 2022 at
== Series Details ==
Series: DGFX OpRegion (rev2)
URL : https://patchwork.freedesktop.org/series/99738/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11236 -> Patchwork_22283
Summary
---
**SUCCESS**
No regressions
On Wed, Feb 16, 2022 at 10:39:56AM +0200, Ville Syrjälä wrote:
> On Tue, Feb 15, 2022 at 07:25:36PM -0800, Navare, Manasi wrote:
> > On Tue, Feb 15, 2022 at 08:31:57PM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > Adjust the cursor dst coordinates appripriately when it's on
>
On Tue, Feb 15, 2022 at 08:31:59PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Do the s/dev_priv/i915/ and s/pipe_config/crtc_state/ renames
> to intel_crtc_compute_config(). I want to start splitting this
> up a bit and doing the renames now avoids spreading these old
> nameing convent
On Tue, Feb 15, 2022 at 08:32:01PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Deduplicate the code to convert the full timings to
> per-pipe timings for bigjoiner usage.
>
> Signed-off-by: Ville Syrjälä
Makes sense to have a helper to do this:
Reviewed-by: Manasi Navare
Manasi
>
On Tue, Feb 15, 2022 at 08:32:02PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> intel_crtc_compute_config() doesn't really tell a unified story.
> Let's chunk it up into pieces. We'll start with
> intel_crtc_compute_pipe_src().
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Manasi Nava
On Tue, Feb 15, 2022 at 08:32:03PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Pull intel_crtc_compute_pipe_mode() out from
> intel_crtc_compute_config(). Since it's semi related
> we'll suck in the max dotclock/double wide checks in
> as well.
>
> And we'll pimp the debugs while at it
On Wed, Feb 16, 2022 at 11:35:39AM -0800, Navare, Manasi wrote:
> On Tue, Feb 15, 2022 at 08:32:02PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > intel_crtc_compute_config() doesn't really tell a unified story.
> > Let's chunk it up into pieces. We'll start with
> > intel_crtc_comp
1 - 100 of 178 matches
Mail list logo
