On Mon, 14 Feb 2022 at 06:32, Christian König
wrote:
>
> Am 13.02.22 um 09:52 schrieb Arunpravin:
> > - Make drm_buddy_alloc a single function to handle
> >range allocation and non-range allocation demands
> >
> > - Implemented a new function alloc_range() which allocates
> >the requested
From: Ville Syrjälä
While pokingaround the watermarks/etc. I noticed our SAGV code
has a bunch of bugs. Let's try to fix it.
Cc: Stanislav Lisovskiy
Ville Syrjälä (6):
drm/i915: Correctly populate use_sagv_wm for all pipes
drm/i915: Fix bw atomic check when switching between SAGV vs. no SA
From: Ville Syrjälä
When changing between SAGV vs. no SAGV on tgl+ we have to
update the use_sagv_wm flag for all the crtcs or else
an active pipe not already in the state will end up using
the wrong watermarks. That is especially bad when we end up
with the tighter non-SAGV watermarks with SAGV
From: Ville Syrjälä
If the only thing that is changing is SAGV vs. no SAGV but
the number of active planes and the total data rates end up
unchanged we currently bail out of intel_bw_atomic_check()
early and forget to actually compute the new WGV point
mask and thus won't actually enable/disable
From: Ville Syrjälä
adlp+ adds some extra bits to the QGV point mask. The code attempts
to handle that but forgot to actually make sure we can store those
bits in the bw state. Fix it.
Cc: sta...@vger.kernel.org
Cc: Stanislav Lisovskiy
Fixes: 192fbfb76744 ("drm/i915: Implement PSF GV point supp
From: Ville Syrjälä
intel_sagv_{pre,post}_plane_update() can accidentally forget
to bail out early on pre-icl and proceed down the icl+ codepath
at the end of the function. Fortunately it'll bail out before
it gets too far due to old_qgv_mask==new_qgv_mask==0 so no real
bug here. But lets make th
From: Ville Syrjälä
Add some debugs on what exactly we're doing to the QGV point mask
in the icl+ sagv pre/post plane update hooks. Currently we're just
guessing.
Cc: Stanislav Lisovskiy
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 37 -
1
From: Ville Syrjälä
To further reduce the confusion between the pre-icl vs. icl+
SAGV codepaths let's do a full split.
Cc: Stanislav Lisovskiy
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 120
1 file changed, 77 insertions(+), 43 deletion
On Mon, Feb 14, 2022 at 11:18:11AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Add some debugs on what exactly we're doing to the QGV point mask
> in the icl+ sagv pre/post plane update hooks. Currently we're just
> guessing.
>
> Cc: Stanislav Lisovskiy
> Signed-off-by: Ville Syrjälä
The below patches add support for data flow metering
as mentioned in the section 6.5.6 FRL data flow metering
of HDMI 2.1 specification.
Add functions to calclulate the DFM parameters
for the given frl config, which is further used to evaluate the
data flow metering requirement as specified in the
Define frl_dfm structure to hold frl characteristics
needed for frl capacity computation in order to
meet the data flow metering requirement.
Signed-off-by: Vandita Kulkarni
---
include/drm/drm_frl_dfm_helper.h | 124 +++
1 file changed, 124 insertions(+)
create mode
Add helper functions for computing non dsc frl
link characteristics
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/drm_frl_dfm_helper.c | 396 +++
1 file changed, 396 insertions(+)
create mode 100644 drivers/gpu/drm/drm_frl_dfm_helper.c
diff --git a/drivers/gpu/drm
Add helpers to compute DFM variables and to verify if the
DFM requirements are met or not in non dsc cases.
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/drm_frl_dfm_helper.c | 161 +++
include/drm/drm_frl_dfm_helper.h | 2 +
2 files changed, 163 insertions(+)
From: Ankit Nautiyal
Add helper functions for calculating FRL capacity and DFM
requirements with given compressed bpp.
Signed-off-by: Ankit Nautiyal
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/drm_frl_dfm_helper.c | 297 +++
include/drm/drm_frl_dfm_helper.h
Add the new frl_dfm_helper file to drm Makefile
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/Makefile | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 8675c2af7ae1..81fe3df8bfda 100644
--- a/drivers/gpu/drm/Ma
On Mon, Feb 14, 2022 at 11:18:07AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> If the only thing that is changing is SAGV vs. no SAGV but
> the number of active planes and the total data rates end up
> unchanged we currently bail out of intel_bw_atomic_check()
> early and forget to actu
On Mon, Feb 14, 2022 at 11:18:06AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> When changing between SAGV vs. no SAGV on tgl+ we have to
> update the use_sagv_wm flag for all the crtcs or else
> an active pipe not already in the state will end up using
> the wrong watermarks. That is es
On Mon, Feb 14, 2022 at 12:05:36PM +0200, Lisovskiy, Stanislav wrote:
> On Mon, Feb 14, 2022 at 11:18:07AM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > If the only thing that is changing is SAGV vs. no SAGV but
> > the number of active planes and the total data rates end up
> > unc
On Mon, Feb 14, 2022 at 12:00:11PM +0200, Lisovskiy, Stanislav wrote:
> On Mon, Feb 14, 2022 at 11:18:11AM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Add some debugs on what exactly we're doing to the QGV point mask
> > in the icl+ sagv pre/post plane update hooks. Currently we'r
From: Ville Syrjälä
The current implementation of the async flip wm0/ddb optimization
does not work at all. The biggest problem is that we skip the
whole intel_pipe_update_{start,end}() dance and thus never actually
complete the commit that is trying to do the wm/ddb change.
To fix this we need
From: Ville Syrjälä
Print the offending plane/crtc id+name in the async flip debugs.
Cc: Stanislav Lisovskiy
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 63 ++--
1 file changed, 44 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm
From: Ville Syrjälä
data_rate==0 no longer means a plane is disabled, it could
also mean we want to use the minimum ddb allocation for it.
Hence we can't bail out early during ddb allocation or
else we'll simply forget to allocate any ddb for such planes.
Cc: Stanislav Lisovskiy
Fixes: 6a4d8cc6
From: Ville Syrjälä
Turns out the async flip wm0/ddb optimization doesn't work
at all currently. Let's fix it. It also had problems with
leaving SAGV on mistakenly but those were handled via a
separate series since it was a more generic issue.
Cc: Stanislav Lisovskiy
Ville Syrjälä (4):
drm/i
From: Ville Syrjälä
Since the async flip state check is done very late and
thus it can see potentially all the planes in the state
(due to the wm/ddb optimization) we need to move the
"can the requested plane do async flips at all?" check
much earlier. For this purpose we introduce
intel_async_fl
On Thu, 10 Feb 2022, Tvrtko Ursulin wrote:
> On 10/02/2022 15:45, Jani Nikula wrote:
>> I've sent parts of this before. Another rebase round.
>
> All look good to me.
>
> Acked-by: Tvrtko Ursulin
Thanks a bunch, pushed the lot!
> Going forward you can maybe impress the readers even more by incl
Move i915_gem_object_needs_bit17_swizzle() next to the other
bit_17_swizzle functions. Also un-inline while at it; does not seem like
this is a function needed in hot paths.
Cc: Tvrtko Ursulin
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 8
drivers/gpu/
On 14/02/2022 13:24, Jani Nikula wrote:
Move i915_gem_object_needs_bit17_swizzle() next to the other
bit_17_swizzle functions. Also un-inline while at it; does not seem like
this is a function needed in hot paths.
Cc: Tvrtko Ursulin
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/gt/in
Wrap accessing struct intel_fbdev guts in a helper.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 6 +++---
drivers/gpu/drm/i915/display/intel_fbdev.c | 8
drivers/gpu/drm/i915/display/intel_fbdev.h | 7 +++
3 files changed
As all access to struct intel_fbdev guts is nicely stowed away in
intel_fbdev.c, we can hide the struct definition there too.
Signed-off-by: Jani Nikula
---
.../drm/i915/display/intel_display_types.h| 21 ---
drivers/gpu/drm/i915/display/intel_fbdev.c| 17 +++
Jani Nikula (2):
drm/i915/fbdev: add intel_fbdev_to_framebuffer() helper
drm/i915/fbdev: hide struct intel_fbdev in intel_fbdev.c
.../drm/i915/display/intel_display_debugfs.c | 6 ++---
.../drm/i915/display/intel_display_types.h| 21
drivers/gpu/drm/i915/display/intel_f
From: Wang Qing
It is better to use time_xxx() directly instead of jiffies judgment
for understanding.
Signed-off-by: Wang Qing
---
drivers/block/xen-blkback/blkback.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/block/xen-blkback/blkback.c
b/drivers/block/
From: Wang Qing
It is better to use time_xxx() directly instead of jiffies judgment
for understanding.
Signed-off-by: Wang Qing
---
drivers/media/dvb-frontends/stv0299.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/media/dvb-frontends/stv0299.c
b/drivers/med
It is illegal to add a dma_fence_chain as timeline point. Flatten out
the fences into a dma_fence_array instead.
Signed-off-by: Christian König
---
drivers/gpu/drm/drm_syncobj.c | 61 ---
1 file changed, 56 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/d
On Thu 10 Feb 13:12 PST 2022, Dmitry Baryshkov wrote:
> On Thu, 10 Feb 2022 at 23:54, Bjorn Andersson
> wrote:
> >
> > On Tue 08 Feb 02:39 PST 2022, Greg Kroah-Hartman wrote:
> >
> > > On Mon, Feb 07, 2022 at 08:43:27PM -0800, Bjorn Andersson wrote:
> > > > In some implementations, such as the Qu
From: Wang Qing
It is better to use time_xxx() directly instead of jiffies judgment
for understanding.
Signed-off-by: Wang Qing
---
drivers/md/dm-writecache.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/md/dm-writecache.c b/drivers/md/dm-writecache.c
index
On Sat, Feb 12, 2022 at 10:51:06PM -0800, Tong Zhang wrote:
> drm/i915 target adds some extra cflags, especially it does re-apply -Wall.
> In clang this will override -Wno-format-security and cause the build to
> fail when CONFIG_DRM_I915_WERROR=y. While with GCC this does not happen.
> We reapply
From: Wang Qing
It is better to use time_xxx() directly instead of jiffies judgment
for understanding.
Signed-off-by: Wang Qing
---
drivers/md/dm-thin.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/md/dm-thin.c b/drivers/md/dm-thin.c
index f4234d6..dced764
--- a/
>>On Thu, Feb 10, 2022 at 06:30:23PM -0800, Qing Wang wrote:
>> From: Wang Qing
>>
>> It is better to use time_is_xxx() directly instead of jiffies judgment
>> for understanding.
>
>Hi Wang,
>
>"judgement" doesn't really make sense as a description to an English
>speaker. The following a commi
On 05/11/2021 06:04, Sean Paul wrote:
From: Sean Paul
This patch adds HDCP 1.x support to msm DP connectors using the new HDCP
helpers.
Sean, is this something that you'd like to pursue further?
We have picked up patches 8-11, which were independent from the rest of
the changes. The rest see
From: Wang Qing
It is better to use time_xxx() directly instead of jiffies judgment
for understanding.
Signed-off-by: Wang Qing
---
drivers/media/dvb-frontends/si21xx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/media/dvb-frontends/si21xx.c
b/drivers/media/dvb
- On Feb 9, 2022, at 2:45 PM, Namhyung Kim namhy...@kernel.org wrote:
> On Wed, Feb 9, 2022 at 11:28 AM Mathieu Desnoyers
> wrote:
>>
>> - On Feb 9, 2022, at 2:22 PM, Namhyung Kim namhy...@kernel.org wrote:
>> > I'm also concerning dynamic allocated locks in a data structure.
>> > If we k
From: Wang Qing
It is better to use time_xxx() directly instead of jiffies judgment
for understanding.
Signed-off-by: Wang Qing
---
drivers/media/test-drivers/vivid/vivid-kthread-cap.c | 3 ++-
drivers/media/test-drivers/vivid/vivid-kthread-out.c | 3 ++-
drivers/media/test-drivers/vivid/v
From: Wang Qing
It is better to use time_xxx() directly instead of jiffies judgment
for understanding.
Signed-off-by: Wang Qing
---
drivers/input/serio/ps2-gpio.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/input/serio/ps2-gpio.c b/drivers/input/serio/ps2-gp
From: Wang Qing
It is better to use time_xxx() directly instead of jiffies judgment
for understanding.
Signed-off-by: Wang Qing
---
drivers/media/dvb-frontends/tda8083.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/media/dvb-frontends/tda8083.c
b/drivers/media/d
- On Feb 9, 2022, at 2:22 PM, Namhyung Kim namhy...@kernel.org wrote:
> Hello,
>
> On Wed, Feb 9, 2022 at 11:02 AM Waiman Long wrote:
>>
>> On 2/9/22 13:29, Mathieu Desnoyers wrote:
>> > - On Feb 9, 2022, at 1:19 PM, Waiman Long long...@redhat.com wrote:
>> >
>> >> On 2/9/22 04:09, Peter
On Mon 07 Feb 23:40 PST 2022, Greg Kroah-Hartman wrote:
> On Mon, Feb 07, 2022 at 08:43:28PM -0800, Bjorn Andersson wrote:
> > The Qualcomm DisplayPort driver contains traces of the necessary
> > plumbing to hook up USB HPD, in the form of the dp_hpd module and the
> > dp_usbpd_cb struct. Use this
From: Wang Qing
It is better use time_xxx() directly instead of jiffies judgment
for understanding.
Signed-off-by: Wang Qing
---
drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.c
b/
From: Wang Qing
It is better use time_xxx() directly instead of jiffies judgment
for understanding.
Signed-off-by: Wang Qing
---
drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.c
b/
i915_pmu_cpu_online() calls cpumask_weight() to check if any bit of a
given cpumask is set. We can do it more efficiently with cpumask_empty()
because cpumask_empty() stops traversing the cpumask as soon as it finds
first set bit, while cpumask_weight() counts all bits unconditionally.
Signed-off-
From: Wang Qing
It is better to use time_xxx() directly instead of jiffies judgment
for understanding.
Signed-off-by: Wang Qing
---
drivers/hid/intel-ish-hid/ipc/ipc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/hid/intel-ish-hid/ipc/ipc.c
b/drivers/hid/intel-i
On Tue 08 Feb 02:39 PST 2022, Greg Kroah-Hartman wrote:
> On Mon, Feb 07, 2022 at 08:43:27PM -0800, Bjorn Andersson wrote:
> > In some implementations, such as the Qualcomm platforms, the display
> > driver has no way to query the current HPD state and as such it's
> > impossible to distinguish be
On Thu, 10 Feb 2022 at 23:54, Bjorn Andersson
wrote:
>
> On Tue 08 Feb 02:39 PST 2022, Greg Kroah-Hartman wrote:
>
> > On Mon, Feb 07, 2022 at 08:43:27PM -0800, Bjorn Andersson wrote:
> > > In some implementations, such as the Qualcomm platforms, the display
> > > driver has no way to query the cu
From: Wang Qing
It is better use time_xxx() directly instead of jiffies judgment
for understanding.
Signed-off-by: Wang Qing
---
drivers/clk/mvebu/armada-37xx-periph.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/mvebu/armada-37xx-periph.c
b/drivers/clk/mv
From: Wang Qing
It is better to use time_is_xxx() directly instead of jiffies judgment
for understanding.
Batch them in a series suggested by Joe.
Wang Qing (14):
block: xen: use time_is_before_eq_jiffies() instead of jiffies judgment
clk: mvebu: use time_is_before_eq_jiffies() instead of j
Am 14.02.22 um 09:36 schrieb Matthew Auld:
On Mon, 14 Feb 2022 at 06:32, Christian König
wrote:
Am 13.02.22 um 09:52 schrieb Arunpravin:
- Make drm_buddy_alloc a single function to handle
range allocation and non-range allocation demands
- Implemented a new function alloc_range() which
- On Feb 9, 2022, at 1:19 PM, Waiman Long long...@redhat.com wrote:
> On 2/9/22 04:09, Peter Zijlstra wrote:
>> On Tue, Feb 08, 2022 at 10:41:56AM -0800, Namhyung Kim wrote:
>>
>>> Eventually I'm mostly interested in the contended locks only and I
>>> want to reduce the overhead in the fast pa
From: Wang Qing
It is better to use time_xxx() directly instead of jiffies judgment
for understanding.
Signed-off-by: Wang Qing
---
drivers/media/radio/wl128x/fmdrv_common.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/media/radio/wl128x/fmdrv_common.c
b/drive
drm/i915 target adds some extra cflags, especially it does re-apply -Wall.
In clang this will override -Wno-format-security and cause the build to
fail when CONFIG_DRM_I915_WERROR=y. While with GCC this does not happen.
We reapply -Wno-format-security here to get around this issue.
drivers/gpu/drm
- On Feb 9, 2022, at 2:02 PM, Waiman Long long...@redhat.com wrote:
> On 2/9/22 13:29, Mathieu Desnoyers wrote:
>> - On Feb 9, 2022, at 1:19 PM, Waiman Long long...@redhat.com wrote:
>>
>>> On 2/9/22 04:09, Peter Zijlstra wrote:
On Tue, Feb 08, 2022 at 10:41:56AM -0800, Namhyung Kim w
From: Wang Qing
It is better to use time_xxx() directly instead of jiffies judgment
for understanding.
Signed-off-by: Wang Qing
---
drivers/gpu/drm/radeon/radeon_pm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c
b/drivers/gpu/drm/rad
Am 13.02.22 um 09:52 schrieb Arunpravin:
- Make drm_buddy_alloc a single function to handle
range allocation and non-range allocation demands
- Implemented a new function alloc_range() which allocates
the requested power-of-two block comply with range limitations
- Moved order computation
On Mon, Feb 14, 2022 at 12:24:57PM +0200, Ville Syrjälä wrote:
> On Mon, Feb 14, 2022 at 12:05:36PM +0200, Lisovskiy, Stanislav wrote:
> > On Mon, Feb 14, 2022 at 11:18:07AM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > If the only thing that is changing is SAGV vs. no SAGV bu
On Mon, Feb 14, 2022 at 11:18:08AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> adlp+ adds some extra bits to the QGV point mask. The code attempts
> to handle that but forgot to actually make sure we can store those
> bits in the bw state. Fix it.
>
> Cc: sta...@vger.kernel.org
> Cc: S
Always use forward declarations instead of includes in headers if
possible.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.
Move the static inline next to the only caller.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/gt/intel_context_sseu.c | 1 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 11 +++
drivers/gpu/drm/i915/gt/intel_lrc.h | 11 ---
drivers/gpu/drm/i915/i915_perf.c
Prefer forward declarations over includes if possible.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 2 ++
drivers/gpu/drm/i915/gt/intel_lrc.h | 5 +++--
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i
On Mon, Feb 14, 2022 at 11:18:09AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> intel_sagv_{pre,post}_plane_update() can accidentally forget
> to bail out early on pre-icl and proceed down the icl+ codepath
> at the end of the function. Fortunately it'll bail out before
> it gets too far
Date: Mon, 14 Feb 2022 19:39:28 +0200
From: "Lisovskiy, Stanislav"
To: Ville Syrjala
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 4/6] drm/i915: Unconfuse pre-icl vs. icl+
intel_sagv_{pre,post}_plane_update()
User-Agent: Mutt/1.9.4 (2018-02-28)
On Mon, Feb 14, 2022 at 11:18:09AM +020
On Mon, Feb 14, 2022 at 12:27:30PM +0200, Ville Syrjälä wrote:
> On Mon, Feb 14, 2022 at 12:00:11PM +0200, Lisovskiy, Stanislav wrote:
> > On Mon, Feb 14, 2022 at 11:18:11AM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > Add some debugs on what exactly we're doing to the QGV po
On Mon, Feb 07, 2022 at 08:43:27PM -0800, Bjorn Andersson wrote:
> In some implementations, such as the Qualcomm platforms, the display
> driver has no way to query the current HPD state and as such it's
> impossible to distinguish between disconnect and attention events.
>
> Add a parameter to dr
On Mon, Feb 14, 2022 at 12:27:30PM +0200, Ville Syrjälä wrote:
> On Mon, Feb 14, 2022 at 12:00:11PM +0200, Lisovskiy, Stanislav wrote:
> > On Mon, Feb 14, 2022 at 11:18:11AM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > Add some debugs on what exactly we're doing to the QGV po
On Fri, Feb 11, 2022 at 9:44 AM Sebastian Andrzej Siewior
wrote:
>
> On 2022-01-27 00:29:37 [+0100], Mario Kleiner wrote:
> > Hi, first thank you for implementing these preempt disables according to
> Hi Mario,
>
> > the markers i left long ago. And sorry for the rather late reply.
> >
> > I had a
There are a few sections in the driver which are not compatible with
PREEMPT_RT. They trigger warnings and can lead to deadlocks at runtime.
Disable the i915 driver on a PREEMPT_RT enabled kernel. This way
PREEMPT_RT itself can be enabled without needing to address the i915
issues first. The RT re
Matt, just a final confirmation on below
> > > > >
> > > > > On Fri, 2022-02-04 at 10:19 -0800, Matthew Brost wrote:
> > > > > > On Wed, Jan 26, 2022 at 02:48:18AM -0800, Alan Previn wrote:
> > > > > > >
> > If the object lives at the GuC level, operate on it at the GuC level.
> >
> > e.g.
> >
On Mon, Feb 14, 2022 at 07:03:05PM +0200, Lisovskiy, Stanislav wrote:
> On Mon, Feb 14, 2022 at 12:24:57PM +0200, Ville Syrjälä wrote:
> > On Mon, Feb 14, 2022 at 12:05:36PM +0200, Lisovskiy, Stanislav wrote:
> > > On Mon, Feb 14, 2022 at 11:18:07AM +0200, Ville Syrjala wrote:
> > > > From: Ville S
On Mon, Feb 14, 2022 at 05:02:06PM +0200, Jani Nikula wrote:
> Wrap accessing struct intel_fbdev guts in a helper.
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_display_debugfs.c | 6 +++---
> drivers/gpu/drm/i915/display/intel_fbdev.c | 8
> driver
The first patch is a drm core patch that replaces the for loop in
drm_mm_insert_node_in_range() with the iterator and would not
cause any functional changes. The second patch is a i915 driver
specific patch that also uses the iterator but solves a different
problem.
Cc: Tvrtko Ursulin
Cc: Nirmoy
This iterator relies on drm_mm_first_hole() and drm_mm_next_hole()
functions to identify suitable holes for an allocation of a given
size by efficiently traversing the rbtree associated with the given
allocator.
It replaces the for loop in drm_mm_insert_node_in_range() and can
also be used by drm
On platforms capable of allowing 8K (7680 x 4320) modes, pinning 2 or
more framebuffers/scanout buffers results in only one that is mappable/
fenceable. Therefore, pageflipping between these 2 FBs where only one
is mappable/fenceable creates latencies large enough to miss alternate
vblanks thereby
am beginning to wonder if you guys run stuff through your CI before
relasing to linux-next. Especially important when removing #include
statements from include files :-)
I have used the drm-intel tree from next-20220214 for today.
--
Cheers,
Stephen Rothwell
pgpEN1JYDctRF.pgp
Description: OpenPGP digital signature
Move initialization of submission-related spinlock, lists and workers to
init_early. This fixes an issue where if the GuC init fails we might
still try to get the lock in the context cleanup code. Note that it is
safe to call the GuC context cleanup code even if the init failed
because all contexts
Looks like trying to move the vma up into guc-upper is impacting many other
functions
in intel_guc_log and intel_guc_log_debugfs. I'll have to take it back (the
level of
redesign i shall attempt with this series).
I'll just move the log_stats back into intel_guc_log and have intel_guc_capture
ha
On Tue, Feb 15, 2022 at 9:17 AM Gabriel Krisman Bertazi
wrote:
>
> Hsin-Yi Wang writes:
>
> > drm_dev_register() sets connector->registration_state to
> > DRM_CONNECTOR_REGISTERED and dev->registered to true. If
> > drm_connector_set_panel_orientation() is first called after
> > drm_dev_register(
On Thu, Feb 10, 2022 at 07:10:32AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/dg1: Update DMC_DEBUG3 register
> URL : https://patchwork.freedesktop.org/series/99942/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11207_full -> Patchwork_22233_
i915_perf is not enabled for dg2 yet, hence skip the feature
initialization.
Signed-off-by: Ramalingam C
cc: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
ind
Fixing the 5th Display output for DG2.
Jouni Högander (1):
drm/i915: Fix for PHY_MISC_TC1 offset
Matt Roper (2):
drm/i915/dg2: Enable 5th display
drm/i915/dg2: Drop 38.4 MHz MPLLB tables
drivers/gpu/drm/i915/display/intel_gmbus.c| 16 +-
drivers/gpu/drm/i915/display/intel_snps_phy.c
From: Matt Roper
DG2 supports a 5th display output which the hardware refers to as "TC1,"
even though it isn't a Type-C output. This behaves similarly to the TC1
on past platforms with just a couple minor differences:
* DG2's TC1 bit in SDEISR is at bit 25 rather than 24 as it is on
ICP/TGP
From: Matt Roper
Our early understanding of DG2 was incorrect; since the 5th display
isn't actually a Type-C output, 38.4 MHz input clocks are never used on
this platform and we can drop the corresponding MPLLB tables.
Cc: Anusha Srivatsa
Cc: José Roberto de Souza
Signed-off-by: Matt Roper
Si
From: Jouni Högander
Currently ICL_PHY_MISC macro is returning offset 0x64C10 for PHY_E
port. Correct offset is 0x64C14.
Fix this by handling PHY_E port seprately.
Signed-off-by: Matt Roper
Signed-off-by: Jouni Högander
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/display/intel_snps
On Fri, Feb 11, 2022 at 10:41:53AM +0200, Ville Syrjälä wrote:
> On Thu, Feb 10, 2022 at 03:12:17PM -0800, Matt Roper wrote:
> > Registers that exist within the MCH BAR and are mirrored into the GPU's
> > MMIO space are a good candidate to separate out into their own header.
> >
> > For reference,
On 2/11/22 05:51, Tvrtko Ursulin wrote:
On 11/02/2022 11:55, Jani Nikula wrote:
On Thu, 10 Feb 2022, Casey Bowman wrote:
In this RFC I would like to ask the community their thoughts
on how we can best handle splitting architecture-specific
calls.
I would like to address the following:
1.
A few of our MCH registers are defined with absolute register offsets.
For consistency, let's switch their definitions to be relative offsets
from MCHBAR_MIRROR_BASE.
Cc: Ville Syrjälä
Suggested-by: Ville Syrjälä
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_reg.h | 12 ++--
Registers that exist within the MCH BAR and are mirrored into the GPU's
MMIO space are a good candidate to separate out into their own header.
For reference, the mirror of the MCH BAR starts at the following
locations in the graphics MMIO space (the end of the MCHBAR range
differs slightly on each
From: Ville Syrjälä
Adjust the cursor dst coordinates appripriately when it's on
the bigjoiner slave pipe. intel_atomic_plane_check_clipping()
already did this but with the cursor we discard those results
(apart from uapi.visible and error checks) since the hardware
will be doing the clipping for
On Mon, Feb 14, 2022 at 10:05:56PM -0800, Casey Bowman wrote:
On 2/11/22 05:51, Tvrtko Ursulin wrote:
On 11/02/2022 11:55, Jani Nikula wrote:
On Thu, 10 Feb 2022, Casey Bowman wrote:
In this RFC I would like to ask the community their thoughts
on how we can best handle splitting architectur
On Mon, Feb 14, 2022 at 10:03:25PM -0800, Matt Roper wrote:
> On Fri, Feb 11, 2022 at 10:41:53AM +0200, Ville Syrjälä wrote:
> > On Thu, Feb 10, 2022 at 03:12:17PM -0800, Matt Roper wrote:
> > > Registers that exist within the MCH BAR and are mirrored into the GPU's
> > > MMIO space are a good cand
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