On Mon, Feb 07, 2022 at 08:28:13AM +, Wang, Zhi A wrote:
> 1) About having the mmio_table.h, I would like to keep the stuff in a
> dedicated header as putting them in intel_gvt.h might needs i915 guys to
> maintain it.
> 2) The other one is about if we should move the mmio_table.c into i915
Hi
Am 04.02.22 um 20:44 schrieb Lucas De Marchi:
[...]
I only came up with such a macro after doing the rest of the patches and
noticing a pattern that is hard to debug otherwise. I expanded the
explanation in the doc above this macro.
Maybe something like:
#define IOSYS_MAP_INIT_OFFSET(map_,
On flat-ccs capable platform we need to evict and resore the ccs data
along with the corresponding main memory.
This ccs data can only be access through BLT engine through a special
cmd ( )
To support above requirement of flat-ccs enabled i915 platforms this
series adds new param called ccs_pages
While evicting the local memory data on flat-ccs capable platform we
need to evict the ccs data associated to the data. For this, we are
adding extra pages ((size / 256) >> PAGE_SIZE) into the ttm_tt.
To achieve this we are adding a new param into the ttm_tt_init as
ccs_pages_needed, which will be
When we are swapping out the local memory obj on flat-ccs capable platform,
we need to capture the ccs data too along with main meory and we need to
restore it when we are swapping in the content.
Extracting and restoring the CCS data is done through a special cmd called
XY_CTRL_SURF_COPY_BLT
Sig
On Mon, Feb 07, 2022 at 09:30:48AM +0200, Lisovskiy, Stanislav wrote:
> On Fri, Feb 04, 2022 at 04:18:18PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > On TGL/RKL the BIOS likes to use some kind of bogus DBUF layout
> > that doesn't match what the spec recommends. With a single act
Hi, Ram,
On 2/7/22 10:37, Ramalingam C wrote:
While evicting the local memory data on flat-ccs capable platform we
need to evict the ccs data associated to the data.
For this, we are
adding extra pages ((size / 256) >> PAGE_SIZE) into the ttm_tt.
To achieve this we are adding a new param
On 07/02/2022 10:37, Ramalingam C wrote:
While evicting the local memory data on flat-ccs capable platform we
need to evict the ccs data associated to the data. For this, we are
adding extra pages ((size / 256) >> PAGE_SIZE) into the ttm_tt.
To achieve this we are adding a new param into the t
On 04/02/2022 01:19, Vivek Kasireddy wrote:
This iterator relies on drm_mm_first_hole() and drm_mm_next_hole()
functions to identify suitable holes for an allocation of a given
size by efficiently traversing the rbtree associated with the given
allocator.
It replaces the for loop in drm_mm_ins
On Mon, 07 Feb 2022, Christoph Hellwig wrote:
> On Mon, Feb 07, 2022 at 08:28:13AM +, Wang, Zhi A wrote:
>> 1) About having the mmio_table.h, I would like to keep the stuff in a
>> dedicated header as putting them in intel_gvt.h might needs i915 guys
>> to maintain it.
>> 2) The other one is a
== Series Details ==
Series: drm/i915/ttm: Evict and store of compressed object
URL : https://patchwork.freedesktop.org/series/99759/
State : failure
== Summary ==
Applying: drm/i915/ttm: Add extra pages for handling ccs data
Applying: drm/i915/migrate: Evict and restore the ccs data
Using ind
On 04/02/2022 01:22, Vivek Kasireddy wrote:
On platforms capable of allowing 8K (7680 x 4320) modes, pinning 2 or
more framebuffers/scanout buffers results in only one that is mappable/
fenceable. Therefore, pageflipping between these 2 FBs where only one
is mappable/fenceable creates latencies
On Thu, Feb 03, 2022 at 05:22:10PM -0800, Vivek Kasireddy wrote:
> On platforms capable of allowing 8K (7680 x 4320) modes, pinning 2 or
> more framebuffers/scanout buffers results in only one that is mappable/
> fenceable. Therefore, pageflipping between these 2 FBs where only one
> is mappable/fe
On Sun, 06 Feb 2022, Anshuman Gupta wrote:
> Abstract opregion operations like get opregion base, get rvda and
> opregion cleanup in form of i915_opregion_ops.
> This will be required to converge igfx and dgfx opregion.
> This keeps intel_opregion_setup() as static function, and adds
> a new funct
On 04/02/2022 01:45, Patchwork wrote:
== Series Details ==
Series: series starting with [1/2] drm/mm: Add an iterator to optimally walk
over holes for an allocation (rev2)
URL : https://patchwork.freedesktop.org/series/99597/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
On Sun, 06 Feb 2022, Anshuman Gupta wrote:
> It need to register opregion_func only for graphics sku
> which has display. Use HAS_DISPLAY() to register
> opregion_func.
>
> Cc: Badal Nilawar
> Cc: Jani Nikula
> Cc: Uma Shankar
> Signed-off-by: Anshuman Gupta
> ---
> drivers/gpu/drm/i915/displ
Op 04-02-2022 om 19:29 schreef Christian König:
> Oh, that's on my TODO list for years!
>
> Am 04.02.22 um 18:48 schrieb Maarten Lankhorst:
>> Suballocating a buffer object is something that is not driver
>> generic, and is useful for other drivers as well.
>>
>> Signed-off-by: Maarten Lankhorst
>
On 07/02/2022 10:58, Ville Syrjälä wrote:
On Thu, Feb 03, 2022 at 05:22:10PM -0800, Vivek Kasireddy wrote:
On platforms capable of allowing 8K (7680 x 4320) modes, pinning 2 or
more framebuffers/scanout buffers results in only one that is mappable/
fenceable. Therefore, pageflipping between th
On Fri, 28 Jan 2022 at 18:52, Ramalingam C wrote:
>
> An indirect ctx wabb is implemented as per Wa_22011450934 to avoid rcs
> restore hang during context restore of a preempted context in GPGPU mode
>
> Signed-off-by: Ramalingam C
> cc: Chris Wilson
Acked-by: Matthew Auld
On 07/02/2022 11:48, Matthew Auld wrote:
On Fri, 28 Jan 2022 at 18:52, Ramalingam C wrote:
An indirect ctx wabb is implemented as per Wa_22011450934 to avoid rcs
restore hang during context restore of a preempted context in GPGPU mode
Signed-off-by: Ramalingam C
cc: Chris Wilson
Acked-by:
On 2/7/22 05:48, Jani Nikula wrote:
On Mon, 07 Feb 2022, Christoph Hellwig wrote:
On Mon, Feb 07, 2022 at 08:28:13AM +, Wang, Zhi A wrote:
1) About having the mmio_table.h, I would like to keep the stuff in a
dedicated header as putting them in intel_gvt.h might needs i915 guys
to maintai
On 04/02/2022 16:37, Michael Cheng wrote:
Drop invalidate_csb_entries and directly call drm_clflush_virt_range.
This allows for one less function call, and prevent complier errors when
building for non-x86 architectures.
v2(Michael Cheng): Drop invalidate_csb_entries function and directly
On 04/02/2022 16:37, Michael Cheng wrote:
This patch series re-work a few i915 functions to use drm_clflush_virt_range
instead of calling clflush or clflushopt directly. This will prevent errors
when building for non-x86 architectures.
v2: s/PAGE_SIZE/sizeof(value) for Re-work intel_write_stat
On Mon, Feb 07, 2022 at 06:57:13AM -0500, Zhi Wang wrote:
> Hi Christoph and Jani:
>
> Thanks for the comments. It would be nice that people can achieve a
> agreement. I am OK with both of the options and also moving some files into
> different folders doesn't needs me to do the full test run aga
On Mon, 07 Feb 2022, Christoph Hellwig wrote:
> On Mon, Feb 07, 2022 at 06:57:13AM -0500, Zhi Wang wrote:
>> Hi Christoph and Jani:
>>
>> Thanks for the comments. It would be nice that people can achieve a
>> agreement. I am OK with both of the options and also moving some files into
>> differen
On Mon, 07 Feb 2022, Tvrtko Ursulin wrote:
> On 04/02/2022 16:37, Michael Cheng wrote:
>> This patch series re-work a few i915 functions to use drm_clflush_virt_range
>> instead of calling clflush or clflushopt directly. This will prevent errors
>> when building for non-x86 architectures.
>>
>> v
On Thu, 20 Jan 2022, Casey Bowman wrote:
> In this RFC I would like to ask the community their thoughts
> on how we can best handle splitting architecture-specific
> calls.
>
> I would like to address the following:
>
> 1. How do we want to split architecture calls? Different object files
> per pl
On Mon, Feb 07, 2022 at 11:47:16AM +, Tvrtko Ursulin wrote:
>
> On 07/02/2022 10:58, Ville Syrjälä wrote:
> > On Thu, Feb 03, 2022 at 05:22:10PM -0800, Vivek Kasireddy wrote:
> >> On platforms capable of allowing 8K (7680 x 4320) modes, pinning 2 or
> >> more framebuffers/scanout buffers resul
From: Ville Syrjälä
Apparently I totally fumbled the loop condition when I
removed the ARRAY_SIZE() stuff from the dbuf slice config
lookup. Comparing the loop index with the active_pipes bitmask
is utter nonsense, what we want to do is check to see if the
mask is zero or not.
Cc: sta...@vger.ke
From: Ville Syrjälä
The bogus loop from compute_dbuf_slices() was copied into
check_mbus_joined() as well. So this lookup is wrong as well.
Fix it.
Cc: sta...@vger.kernel.org
Fixes: f4dc00863226 ("drm/i915/adl_p: MBUS programming")
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm
On 07/02/2022 13:24, Ville Syrjälä wrote:
On Mon, Feb 07, 2022 at 11:47:16AM +, Tvrtko Ursulin wrote:
On 07/02/2022 10:58, Ville Syrjälä wrote:
On Thu, Feb 03, 2022 at 05:22:10PM -0800, Vivek Kasireddy wrote:
On platforms capable of allowing 8K (7680 x 4320) modes, pinning 2 or
more fra
Hi, Christian,
On Mon, 2022-02-07 at 12:41 +0100, Christian König wrote:
> Am 07.02.22 um 10:37 schrieb Ramalingam C:
> > On flat-ccs capable platform we need to evict and resore the ccs data
> > along with the corresponding main memory.
> >
> > This ccs data can only be access through BLT engine
On 2022-02-07 at 12:41:59 +0100, Christian König wrote:
> Am 07.02.22 um 10:37 schrieb Ramalingam C:
> > On flat-ccs capable platform we need to evict and resore the ccs data
> > along with the corresponding main memory.
> >
> > This ccs data can only be access through BLT engine through a special
Hi Zhi,
I love your patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
[also build test WARNING on next-20220207]
[cannot apply to drm-intel/for-linux-next hch-configfs/for-next v5.17-rc3]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And
On 2022-02-07 at 15:37:09 +0100, Christian König wrote:
> Am 07.02.22 um 14:53 schrieb Ramalingam C:
> > On 2022-02-07 at 12:41:59 +0100, Christian König wrote:
> > > Am 07.02.22 um 10:37 schrieb Ramalingam C:
> > > > On flat-ccs capable platform we need to evict and resore the ccs data
> > > > alo
Thanks for the clarification, Ram!
On 07/02/2022 14:53, Ramalingam C wrote:
On 2022-02-07 at 12:41:59 +0100, Christian König wrote:
Am 07.02.22 um 10:37 schrieb Ramalingam C:
On flat-ccs capable platform we need to evict and resore the ccs data
along with the corresponding main memory.
This c
Hi, Ram,
A couple of quick questions before starting a more detailed review:
1) Does this also support migrating of compressed data LMEM->LMEM?
What-about inter-tile?
2) Do we need to block faulting of compressed data in the fault handler
as a follow-up patch?
/Thomas
On Mon, 2022-02-07 at 15
On 2022-02-07 at 20:25:42 +0530, Hellstrom, Thomas wrote:
> Hi, Ram,
>
> A couple of quick questions before starting a more detailed review:
>
> 1) Does this also support migrating of compressed data LMEM->LMEM?
> What-about inter-tile?
Honestly this series mainly facused on eviction of lmem into
On Mon, 2022-02-07 at 20:44 +0530, Ramalingam C wrote:
> On 2022-02-07 at 20:25:42 +0530, Hellstrom, Thomas wrote:
> > Hi, Ram,
> >
> > A couple of quick questions before starting a more detailed review:
> >
> > 1) Does this also support migrating of compressed data LMEM->LMEM?
> > What-about int
This is set of various patches that are stuck in my patch queue.
KVM_REQ_GET_NESTED_STATE_PAGES patch is mostly RFC, but it does seem
to work for me.
Read-only APIC ID is also somewhat RFC.
Some of these patches are preparation for support for nested AVIC
which I almost done developing, and will
When the guest doesn't enable paging, and NPT/EPT is disabled, we
use guest't paging CR3's as KVM's shadow paging pointer and
we are technically in direct mode as if we were to use NPT/EPT.
In direct mode we create SPTEs with user mode permissions
because usually in the direct mode the NPT/EPT doe
Turns out that due to review feedback and/or rebases
I accidentally moved the call to nested_svm_load_cr3 to be too early,
before the NPT is enabled, which is very wrong to do.
KVM can't even access guest memory at that point as nested NPT
is needed for that, and of course it won't initialize the
While usually, restoring the smm state makes the KVM enter
the nested guest thus a different vmcb (vmcb02 vs vmcb01),
KVM should still mark it as dirty, since hardware
can in theory cache multiple vmcbs.
Failure to do so, combined with lack of setting the
nested_run_pending (which is fixed in the
While RSM induced VM entries are not full VM entries,
they still need to be followed by actual VM entry to complete it,
unlike setting the nested state.
This patch fixes boot of hyperv and SMM enabled
windows VM running nested on KVM, which fail due
to this issue combined with lack of dirty bit se
KVM already honours few clean bits thus it makes sense
to let the nested guest know about it.
Note that KVM also doesn't check if the hardware supports
clean bits, and therefore nested KVM was
already setting clean bits and L0 KVM
was already honouring them.
Signed-off-by: Maxim Levitsky
---
a
Use a dummy unused vmexit reason to mark the 'VM exit'
that is happening when we exit to handle SMM,
which is not a real VM exit.
This makes it a bit easier to read the KVM trace,
and avoids other potential problems.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/svm/svm.c | 2 +-
1 file change
Fix a corner case in which the L1 hypervisor intercepts
interrupts (INTERCEPT_INTR) and either doesn't set
virtual interrupt masking (V_INTR_MASKING) or enters a
nested guest with EFLAGS.IF disabled prior to the entry.
In this case, despite the fact that L1 intercepts the interrupts,
KVM still nee
kvm_apic_update_apicv is called when AVIC is still active, thus IRR bits
can be set by the CPU after it is called, and don't cause the irr_pending
to be set to true.
Also logic in avic_kick_target_vcpu doesn't expect a race with this
function so to make it simple, just keep irr_pending set to true
asm/svm.h is the correct place for all values that are defined in
the SVM spec, and that includes AVIC.
Also add some values from the spec that were not defined before
and will be soon useful.
Signed-off-by: Maxim Levitsky
---
arch/x86/include/asm/msr-index.h | 1 +
arch/x86/include/asm/svm.h
If svm_deliver_avic_intr is called just after the target vcpu's AVIC got
inhibited, it might read a stale value of vcpu->arch.apicv_active
which can lead to the target vCPU not noticing the interrupt.
To fix this use load-acquire/store-release so that, if the target vCPU
is IN_GUEST_MODE, we're gu
Out of precation use vmcb01 when enabling host AVIC.
No functional change intended.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/svm/avic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c
index 4c2d622b3b9f0..c6072245f7fbb
Inhibit the AVIC of the vCPU that is running nested for the duration of the
nested run, so that all interrupts arriving from both its vCPU siblings
and from KVM are delivered using normal IPIs and cause that vCPU to vmexit.
Note that unlike normal AVIC inhibition, there is no need to
update the AV
No normal guest has any reason to change physical APIC IDs, and
allowing this introduces bugs into APIC acceleration code.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/lapic.c | 28 ++--
1 file changed, 22 insertions(+), 6 deletions(-)
diff --git a/arch/x86/kvm/lapic.c
KVM allowed to set non boot apic id via setting apic state
if using older non x2apic 32 bit apic id userspace api.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/lapic.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lap
Now that KVM doesn't allow to change APIC ID in case AVIC is
enabled, remove buggy AVIC code that tried to do so.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/svm/avic.c | 35 ---
1 file changed, 35 deletions(-)
diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/k
Apparently on some systems AVIC is disabled in CPUID but still usable.
Allow the user to override the CPUID if the user is willing to
take the risk.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/svm/svm.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/x86/
It makes more sense to print new SPTE value than the
old value.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/mmu/mmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
index 296f8723f9ae9..43c7abdd6b70f 100644
--- a/arch/x86/kv
Add an (mostly debug) option to force KVM's shadow mmu
to never have unsync pages.
This is useful in some cases to debug it.
It is also useful for some legacy guest OSes which don't
flush TLBs correctly, and thus don't work on modern
CPUs which have speculative MMUs.
Using this option together w
This is a tiny refactoring, and can be useful to check
if a GPA/GFN is within a memslot a bit more cleanly.
Signed-off-by: Maxim Levitsky
---
include/linux/kvm_host.h | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h
This will be used to enable write tracking from nested AVIC code
and can also be used to enable write tracking in GVT-g module
when it actually uses it as opposed to always enabling it,
when the module is compiled in the kernel.
No functional change intended.
Signed-off-by: Maxim Levitsky
---
a
This allows to enable the write tracking only when KVMGT is
actually used and doesn't carry any penalty otherwise.
Tested by booting a VM with a kvmgt mdev device.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/Kconfig | 3 ---
arch/x86/kvm/mmu/mmu.c | 2 +-
drivers/gpu/dr
When L2 is running without LBR virtualization, we should ensure
that L1's LBR msrs continue to update as usual.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/svm/nested.c | 11 +
arch/x86/kvm/svm/svm.c| 98 +++
arch/x86/kvm/svm/svm.h| 2 +
3 file
This was tested with kvm-unit-test that was developed
for this purpose.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/svm/nested.c | 21 +++--
arch/x86/kvm/svm/svm.c| 8
arch/x86/kvm/svm/svm.h| 1 +
3 files changed, 28 insertions(+), 2 deletions(-)
diff --git
This was tested by booting L1,L2,L3 (all Linux) and checking
that no VMLOAD/VMSAVE vmexits happened.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/svm/nested.c | 35 +--
arch/x86/kvm/svm/svm.c| 7 +++
arch/x86/kvm/svm/svm.h| 8 +++-
3 files chan
Allow L1 to use these settings if L0 disables PAUSE interception
(AKA cpu_pm=on)
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/svm/nested.c | 6 ++
arch/x86/kvm/svm/svm.c| 17 +
arch/x86/kvm/svm/svm.h| 2 ++
3 files changed, 25 insertions(+)
diff --git a/arch/x86/
On 2022-02-07 at 20:52:33 +0530, Hellstrom, Thomas wrote:
> On Mon, 2022-02-07 at 20:44 +0530, Ramalingam C wrote:
> > On 2022-02-07 at 20:25:42 +0530, Hellstrom, Thomas wrote:
> > > Hi, Ram,
> > >
> > > A couple of quick questions before starting a more detailed review:
> > >
> > > 1) Does this al
In case L1 enables vGIF for L2, the L2 cannot affect L1's GIF, regardless
of STGI/CLGI intercepts, and since VM entry enables GIF, this means
that L1's GIF is always 1 while L2 is running.
Thus in this case leave L1's vGIF in vmcb01, while letting L2
control the vGIF thus implementing nested vGIF.
This parameter will be used by VMX and SVM code to force
interception of a set of exceptions, given by a bitmask
for guest debug and/or kvm debug.
This is based on an idea first shown here:
https://patchwork.kernel.org/project/kvm/patch/20160301192822.gd22...@pd.tnic/
CC: Borislav Petkov
Signed-
Currently #TS interception is only done once.
Also exception interception is not enabled for SEV guests.
Signed-off-by: Maxim Levitsky
---
arch/x86/include/asm/kvm_host.h | 2 +
arch/x86/include/uapi/asm/kvm.h | 1 +
arch/x86/kvm/svm/svm.c | 92 -
arch/
All exceptions are supported. Some bugs might remain in regard to KVM own
interception of #PF but since this is strictly
debug feature this should be OK.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/vmx/nested.c | 8 +++
arch/x86/kvm/vmx/vmcs.h | 6 +
arch/x86/kvm/vmx/vmx.c| 47
As it turned out this request isn't really needed,
and it complicates the nested migration.
In theory this patch can break userspace if
userspace relies on updating KVM's memslots
after setting nested state but there is little reason
for it to rely on this.
However this is undocumented and there
On 20/01/2022 22:16, Casey Bowman wrote:
In this RFC I would like to ask the community their thoughts
on how we can best handle splitting architecture-specific
calls.
I would like to address the following:
1. How do we want to split architecture calls? Different object files
per platform? Sep
== Series Details ==
Series: My patch queue
URL : https://patchwork.freedesktop.org/series/99770/
State : failure
== Summary ==
Applying: KVM: x86: SVM: don't passthrough SMAP/SMEP/PKE bits in !NPT &&
!gCR0.PG case
error: sha1 information is lacking or useless (arch/x86/kvm/svm/svm.c).
error:
== Series Details ==
Series: series starting with [1/2] drm/i195: Fix dbuf slice config lookup
URL : https://patchwork.freedesktop.org/series/99764/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11196 -> Patchwork_22188
Sum
Fallback function implemented inside memcpy_from_wc functions when
copying using accelerated read is not possible.
v2: Fixed Sparse warnings
Balasubramani Vivekanandan (1):
drm/i915: Add fallback inside memcpy_from_wc functions
drivers/gpu/drm/i915/gem/i915_gem_object.c | 5 +-
drivers/gpu/d
memcpy_from_wc functions can fail if SSE4.1 is not supported or the
supplied addresses are not 16-byte aligned. It was then upto to the
caller to use memcpy as fallback.
Now fallback to memcpy is implemented inside memcpy_from_wc functions
relieving the user from checking the return value of i915_m
On Mon, Feb 07, 2022 at 03:26:59PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Apparently I totally fumbled the loop condition when I
> removed the ARRAY_SIZE() stuff from the dbuf slice config
> lookup. Comparing the loop index with the active_pipes bitmask
> is utter nonsense, what we
On 1/28/2022 10:52 AM, Ramalingam C wrote:
From: Stuart Summers
The driver is set currently to fail modprobe when GuC is disabled
(enable_guc=0) after GuC has been loaded on a previous modprobe.
For GuC deprivilege, the BIOS is setting the locked bit, so the
driver always considers the GuC t
== Series Details ==
Series: Add fallback inside memcpy_from_wc functions
URL : https://patchwork.freedesktop.org/series/99774/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915
== Series Details ==
Series: Add fallback inside memcpy_from_wc functions
URL : https://patchwork.freedesktop.org/series/99774/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11197 -> Patchwork_22190
Summary
---
**SUC
== Series Details ==
Series: series starting with [1/2] drm/i195: Fix dbuf slice config lookup
URL : https://patchwork.freedesktop.org/series/99764/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11196_full -> Patchwork_22188_full
===
Ah, sorry thanks for pointing that out. We did discuss previously. I
will go ahead and change it.
On 2022-02-07 3:57 a.m., Tvrtko Ursulin wrote:
On 04/02/2022 16:37, Michael Cheng wrote:
Drop invalidate_csb_entries and directly call drm_clflush_virt_range.
This allows for one less function ca
lgtm,
Reviewed-by: Umesh Nerlige Ramappa
Umesh
On Wed, Jan 26, 2022 at 02:48:16AM -0800, Alan Previn wrote:
Abstract out a Gen9 register list as the default for all other
platforms we don't yet formally support GuC submission on.
Signed-off-by: Alan Previn
---
.../gpu/drm/i915/gt/uc/intel_g
This is John/Rodrigo's 2 patches with some minor changes, and I added
2 patches.
"drm/i915/uapi: Add query for hwconfig blob" was changed:
* Rename DRM_I915_QUERY_HWCONFIG_TABLE to DRM_I915_QUERY_HWCONFIG_BLOB
as requested by Joonas.
* Reword commit message
* I added Acked-by to this patc
From: Rodrigo Vivi
The DRM_I915_QUERY_HWCONFIG_BLOB query item returns a blob of data
which it receives from the GuC software. This blob provides some
useful data about the hardware for drivers.
Although the blob is not fully documented at this time, the basic
format is an array of u32 values. T
From: John Harrison
Implement support for fetching the hardware description table from the
GuC. The call is made twice - once without a destination buffer to
query the size and then a second time to fill in the buffer.
Note that the table is only available on ADL-P and later platforms.
Cc: Mich
Also, document DRM_I915_QUERY_HWCONFIG_BLOB with this struct.
Cc: Daniel Vetter
Signed-off-by: Jordan Justen
---
include/uapi/drm/i915_drm.h | 24
1 file changed, 24 insertions(+)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 069d2fadfbd9
Signed-off-by: Jordan Justen
---
.../gpu/drm/i915/gt/uc/intel_guc_hwconfig.c | 26 +++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
index ce6088f112d4..695ef7a8f519 100644
--- a/
== Series Details ==
Series: GuC HWCONFIG with documentation
URL : https://patchwork.freedesktop.org/series/99787/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
CC [M] drivers/
The following changes since commit eb8ea1b46893c42edbd516f971a93b4d097730ab:
Merge branch 'v1.1.7' of https://github.com/irui-wang/linux_fw_vpu_v1.1.7
into main (2022-01-24 06:49:52 -0500)
are available in the Git repository at:
git://anongit.freedesktop.org/drm/drm-firmware dg2_guc_v69.0.3
== Series Details ==
Series: Add fallback inside memcpy_from_wc functions
URL : https://patchwork.freedesktop.org/series/99774/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11197_full -> Patchwork_22190_full
Summary
--
This patch series re-work a few i915 functions to use drm_clflush_virt_range
instead of calling clflush or clflushopt directly. This will prevent errors
when building for non-x86 architectures.
Re-work intel_write_status_page to use drm_clflush_virt_range. This
will prevent compiler errors when building for non-x86 architectures.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gt/intel_engine.h | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/driv
Use drm_clflush_virt_range instead of directly invoking clflush. This
will prevent compiler errors when building for non-x86 architectures.
v2(Michael Cheng): Remove extra clflush
v3(Michael Cheng): Remove memory barrier since drm_clflush_virt_range
takes care of it.
Signed-of
Use drm_clflush_virt_range instead of clflushopt and remove the memory
barrier, since drm_clflush_virt_range takes care of that.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu
Drop invalidate_csb_entries and directly call drm_clflush_virt_range.
This allows for one less function call, and prevent complier errors when
building for non-x86 architectures.
v2(Michael Cheng): Drop invalidate_csb_entries function and directly
invoke drm_clflush_virt_range.
Replace all occurance of cache_clflush_range with
drm_clflush_virt_range. This will prevent compile errors on non-x86
platforms.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 12 ++--
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +-
Use flush_tlb_kernel_range when invoking drm_clflush_virt_range on
arm64 platforms. Using flush_tlb_kernel_range will:
1. Make sure prior page-table updates have been completed
2. Invalidate the TLB
3. Check if the TLB invalidation has been completed
Signed-off-by: Michael Cheng
---
drivers/gpu
== Series Details ==
Series: Use drm_clflush* instead of clflush (rev5)
URL : https://patchwork.freedesktop.org/series/99450/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
01334f06e3af drm/i915/gt: Re-work intel_write_status_page
5f2ab439de24 drm/i915/gt: Drop invalidate_csb_en
== Series Details ==
Series: Use drm_clflush* instead of clflush (rev5)
URL : https://patchwork.freedesktop.org/series/99450/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
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