[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gvt: Fix intel_vgpu_default_mmio_write() kernel-doc comment

== Series Details == Series: drm/i915/gvt: Fix intel_vgpu_default_mmio_write() kernel-doc comment URL : https://patchwork.freedesktop.org/series/98681/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11059_full -> Patchwork_21950_full

Re: [Intel-gfx] [RFC 7/7] drm/i915/guc: Print the GuC error capture output register list.

On Mon, 2022-01-10 at 08:07 +, Tvrtko Ursulin wrote: > On 07/01/2022 17:03, Teres Alexis, Alan Previn wrote: > > On Fri, 2022-01-07 at 09:03 +, Tvrtko Ursulin wrote: > > > On 06/01/2022 18:33, Teres Alexis, Alan Previn wrote: > > > > On Thu, 2022-01-06 at 09:38 +, Tvrtko Ursulin wrote:

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/selftests: fix potential refcnt issue of a dma_buf object

== Series Details == Series: drm/i915/selftests: fix potential refcnt issue of a dma_buf object URL : https://patchwork.freedesktop.org/series/98684/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: fix potential refcnt issue of a dma_buf object

== Series Details == Series: drm/i915/selftests: fix potential refcnt issue of a dma_buf object URL : https://patchwork.freedesktop.org/series/98684/ State : success == Summary == CI Bug Log - changes from CI_DRM_11061 -> Patchwork_21951 Su

[Intel-gfx] [TGL-U][iGFX] Monitoring the freq of iGFX with kernel 5.10 on TGL-U i5-1145GRE

Hi all, I would like to monitor the frequency of the iGPU of my TGL platform while running glmark2 in bursts which means glmark2 is 5sec running and 5sec not running. I disabled RC6 by echo 0 > /sys/class/drm/card0/gt_rc6_enable for my tests. Furthermore, I tried to lock the iGPU frequency to m

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Discard large BIOS framebuffers causing display corruption. (rev2)

== Series Details == Series: drm/i915: Discard large BIOS framebuffers causing display corruption. (rev2) URL : https://patchwork.freedesktop.org/series/98683/ State : failure == Summary == Applying: drm/i915: Discard large BIOS framebuffers causing display corruption. error: patch failed: dr

[Intel-gfx] ✗ Fi.CI.BUILD: failure for Add missing format_mod_supported functions (rev2)

== Series Details == Series: Add missing format_mod_supported functions (rev2) URL : https://patchwork.freedesktop.org/series/98680/ State : failure == Summary == Applying: drm/plane: Make format_mod_supported truly optional Using index info to reconstruct a base tree... M drivers/gpu/dr

Re: [Intel-gfx] [TGL-U][iGFX] Monitoring the freq of iGFX with kernel 5.10 on TGL-U i5-1145GRE

On Mon, 2022-01-10 at 18:56 +, Schweikhardt, Markus wrote: > Hi all, >   > I would like to monitor the frequency of the iGPU of my TGL platform while > running glmark2 in bursts which means glmark2 is 5secrunning and 5sec not > running.I disabled RC6 by echo 0 > /sys/class/drm/card0/gt_rc6_ena

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Fix NULL vs IS_ERR checking for kernel_context

== Series Details == Series: drm/i915/selftests: Fix NULL vs IS_ERR checking for kernel_context URL : https://patchwork.freedesktop.org/series/98685/ State : success == Summary == CI Bug Log - changes from CI_DRM_11061 -> Patchwork_21952 Su

Re: [Intel-gfx] [PATCH] drm/i915/display: Enable second VDSC engine for higher moderates

Thankf for revisiting this thread. The use of max_cdclk is currently in 2 places in DSC code 1. . if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) { if (pipe_config->dsc.slice_count > 1) { pipe_config->dsc.dsc_split = true; 2. if (bigjoiner) {

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/fbc: replace DEFINE_SIMPLE_ATTRIBUTE with DEFINE_DEBUGFS_ATTRIBUTE (rev2)

== Series Details == Series: drm/i915/fbc: replace DEFINE_SIMPLE_ATTRIBUTE with DEFINE_DEBUGFS_ATTRIBUTE (rev2) URL : https://patchwork.freedesktop.org/series/98682/ State : warning == Summary == $ dim checkpatch origin/drm-tip 82610811562c drm/i915/fbc: replace DEFINE_SIMPLE_ATTRIBUTE with

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/fbc: replace DEFINE_SIMPLE_ATTRIBUTE with DEFINE_DEBUGFS_ATTRIBUTE (rev2)

== Series Details == Series: drm/i915/fbc: replace DEFINE_SIMPLE_ATTRIBUTE with DEFINE_DEBUGFS_ATTRIBUTE (rev2) URL : https://patchwork.freedesktop.org/series/98682/ State : success == Summary == CI Bug Log - changes from CI_DRM_11061 -> Patchwork_21955 ===

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: make array flex_regs static const

== Series Details == Series: i915: make array flex_regs static const URL : https://patchwork.freedesktop.org/series/98688/ State : warning == Summary == $ dim checkpatch origin/drm-tip 4d8e56b193f6 i915: make array flex_regs static const -:23: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-b

[Intel-gfx] ✓ Fi.CI.BAT: success for i915: make array flex_regs static const

== Series Details == Series: i915: make array flex_regs static const URL : https://patchwork.freedesktop.org/series/98688/ State : success == Summary == CI Bug Log - changes from CI_DRM_11061 -> Patchwork_21956 Summary --- **SUCCESS*

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: clean up i915_drv.h, part 2

== Series Details == Series: drm/i915: clean up i915_drv.h, part 2 URL : https://patchwork.freedesktop.org/series/98691/ State : warning == Summary == $ dim checkpatch origin/drm-tip 69bb96496495 drm/i915: split out i915_gem.h declarations from i915_drv.h 480ab58f49c9 drm/i915: split out i915_

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: clean up i915_drv.h, part 2

== Series Details == Series: drm/i915: clean up i915_drv.h, part 2 URL : https://patchwork.freedesktop.org/series/98691/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: clean up i915_drv.h, part 2

== Series Details == Series: drm/i915: clean up i915_drv.h, part 2 URL : https://patchwork.freedesktop.org/series/98691/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11061 -> Patchwork_21957 Summary --- **FAILURE**

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Asynchronous vma unbinding (rev7)

== Series Details == Series: drm/i915: Asynchronous vma unbinding (rev7) URL : https://patchwork.freedesktop.org/series/98055/ State : warning == Summary == $ dim checkpatch origin/drm-tip fa2206c87130 drm/i915: Initial introduction of vma resources -:249: WARNING:FILE_PATH_CHANGES: added, mov

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Asynchronous vma unbinding (rev7)

== Series Details == Series: drm/i915: Asynchronous vma unbinding (rev7) URL : https://patchwork.freedesktop.org/series/98055/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Asynchronous vma unbinding (rev7)

== Series Details == Series: drm/i915: Asynchronous vma unbinding (rev7) URL : https://patchwork.freedesktop.org/series/98055/ State : success == Summary == CI Bug Log - changes from CI_DRM_11061 -> Patchwork_21958 Summary --- **SUCC

Re: [Intel-gfx] [GIT PULL] GVT next changes for drm-intel-next-queued

On Fri, 2022-01-07 at 14:43 +, Wang, Zhi A wrote: > Hi folks: > > Happy holidays! This pull mostly contains the code re-factors patches > from Guenter Roeck and Rikard. Also a minor change from Zhenyu. > > Zhi > > The following changes since commit > 3bfa7d40ce736ffbbfe07127061f54b359ee2b12:

[Intel-gfx] [PATCH] drm/i915/snps: vswing value refined for SNPS phys

From: Clint Taylor Updated new values from BSPEC. BSPEC: 53920 Cc: Jani Nikula Cc: José Roberto de Souza Cc: Imre Deak Signed-off-by: Clint Taylor --- .../drm/i915/display/intel_ddi_buf_trans.c| 42 +-- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/dri

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: fix potential refcnt issue of a dma_buf object

== Series Details == Series: drm/i915/selftests: fix potential refcnt issue of a dma_buf object URL : https://patchwork.freedesktop.org/series/98684/ State : success == Summary == CI Bug Log - changes from CI_DRM_11061_full -> Patchwork_21951_full ==

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/snps: vswing value refined for SNPS phys

== Series Details == Series: drm/i915/snps: vswing value refined for SNPS phys URL : https://patchwork.freedesktop.org/series/98710/ State : success == Summary == CI Bug Log - changes from CI_DRM_11061 -> Patchwork_21959 Summary ---

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/selftests: Fix NULL vs IS_ERR checking for kernel_context

== Series Details == Series: drm/i915/selftests: Fix NULL vs IS_ERR checking for kernel_context URL : https://patchwork.freedesktop.org/series/98685/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11061_full -> Patchwork_21952_full ==

[Intel-gfx] [PATCH] drm/i915/pmu: Use PM timestamp instead of RING TIMESTAMP for reference

All timestamps returned by GuC for GuC PMU busyness are captured from GUC PM TIMESTAMP. Since this timestamp does not tick when GuC goes idle, kmd uses RING_TIMESTAMP to measure busyness of an engine with an active context. In further stress testing, the MMIO read of the RING_TIMESTAMP is seen to c

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/fbc: replace DEFINE_SIMPLE_ATTRIBUTE with DEFINE_DEBUGFS_ATTRIBUTE (rev2)

== Series Details == Series: drm/i915/fbc: replace DEFINE_SIMPLE_ATTRIBUTE with DEFINE_DEBUGFS_ATTRIBUTE (rev2) URL : https://patchwork.freedesktop.org/series/98682/ State : success == Summary == CI Bug Log - changes from CI_DRM_11061_full -> Patchwork_21955_full =

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/pmu: Use PM timestamp instead of RING TIMESTAMP for reference

== Series Details == Series: drm/i915/pmu: Use PM timestamp instead of RING TIMESTAMP for reference URL : https://patchwork.freedesktop.org/series/98714/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separat

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/pmu: Use PM timestamp instead of RING TIMESTAMP for reference

== Series Details == Series: drm/i915/pmu: Use PM timestamp instead of RING TIMESTAMP for reference URL : https://patchwork.freedesktop.org/series/98714/ State : success == Summary == CI Bug Log - changes from CI_DRM_11061 -> Patchwork_21960

[Intel-gfx] ✗ Fi.CI.IGT: failure for i915: make array flex_regs static const

== Series Details == Series: i915: make array flex_regs static const URL : https://patchwork.freedesktop.org/series/98688/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11061_full -> Patchwork_21956_full Summary ---

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Asynchronous vma unbinding (rev7)

== Series Details == Series: drm/i915: Asynchronous vma unbinding (rev7) URL : https://patchwork.freedesktop.org/series/98055/ State : success == Summary == CI Bug Log - changes from CI_DRM_11061_full -> Patchwork_21958_full Summary ---

Re: [Intel-gfx] [PATCH] drm/i915/display: Enable second VDSC engine for higher moderates

> -Original Message- > From: Navare, Manasi D > Sent: Tuesday, January 11, 2022 1:07 AM > To: Kulkarni, Vandita > Cc: Nikula, Jani ; Lisovskiy, Stanislav > ; Ville Syrjälä > ; > intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH] drm/i915/display: Enable second VDSC > engi

[Intel-gfx] [PATCH v3 05/11] drm/i915: Replace GFX_MODE_GEN7 with RING_MODE_GEN7

It's preferable to use parameterized register macros where possible. Cc: Jani Nikula Signed-off-by: Matt Roper Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +- drivers/gpu/drm/i915/gvt/mmio_context.c | 4 ++-- drivers/gpu/drm/i915/i915_reg.h | 1

[Intel-gfx] [PATCH v3 00/11] Start cleaning up register definitions

Let's start splitting up and cleaning up parts of i915_reg.h. Rather than starting with dead code removal as we did in v1, this time we'll switch a few macros to parameterized style, and then move a few types of registers (engine registers, SNPS PHY registers) off to their own header files. v3:

[Intel-gfx] [PATCH v3 02/11] drm/i915: Parameterize PWRCTX_MAXCNT

Rather than having separate definitions for each engine, create a single parameterized macro that takes the engine base offset. This will also ensure we get to the proper offset if we ever need to use these registers on newer platforms (where the media engine offsets have changed). Cc: Jani Nikul

[Intel-gfx] [PATCH v3 06/11] drm/i915: Introduce i915_reg_defs.h

We'd like to start splitting i915_reg.h into various domain-specific register files and cleaning them up. Let's move the basic macros and type definitions to their own header file that can be including in each of the new split headers. Cc: Jani Nikula Signed-off-by: Matt Roper --- drivers/gpu/

[Intel-gfx] [PATCH v3 08/11] drm/i915: Move SNPS PHY registers to their own header

These registers are only needed in a couple files and on specific platforms; let's keep them separate from the general register pool. v2: - Don't forget to include i915_reg_defs.h (Jani) - Ensure include guard matches header name (Jani) Cc: Jani Nikula Signed-off-by: Matt Roper Reviewed-by: J

[Intel-gfx] [PATCH v3 11/11] drm/i915: Drop unused _PORT3 and _PORT4 TC phy register offsets

All MG/DKL PHY register regions are evenly spaced offset-wise (0x168000, 0x169000, 0x16A000, 0x16B000) so the _MMIO_PORT() macro we use to access their registers only needs the first two offsets. We can drop the _PORT3 and _PORT4 offsets which are never directly referenced. Cc: Jani Nikula Signe

[Intel-gfx] [PATCH v3 07/11] drm/i915/gt: Move engine registers to their own header

Let's start breaking up and cleaning up the massive i915_reg.h file. We'll start by moving all registers that are defined in relation to an engine base to their own header. There are probably a bunch of other "engine registers" that we haven't moved yet (especially those that belong to the render

[Intel-gfx] [PATCH v3 04/11] drm/i915: Use RING_PSMI_CTL rather than per-engine macros

We have a parameterized macro for RING_PSMI_CTL; let's use that instead of the per-engine definitions where possible. Cc: Jani Nikula Signed-off-by: Matt Roper Reviewed-by: Jani Nikula --- .../gpu/drm/i915/gt/intel_ring_submission.c | 10 +- drivers/gpu/drm/i915/gt/intel_workarounds.

[Intel-gfx] [PATCH v3 03/11] drm/i915: Parameterize ECOSKPD

Combine the separate render and blitter register definitions into a single definition. We already know we have some workarounds on an upcoming platform that will need to update the ECOSKPD register for other engines too, so this helps pave the way for that. Cc: Jani Nikula Signed-off-by: Matt Ro

[Intel-gfx] [PATCH v3 09/11] drm/i915: Move combo PHY registers to their own header

These registers are only needed in a couple files and on specific platforms; let's keep them separate from the general register pool. Cc: Jani Nikula Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/display/icl_dsi.c| 1 + .../gpu/drm/i915/display/intel_combo_phy.c| 1 + .../d

[Intel-gfx] [PATCH v3 10/11] drm/i915: Move TC PHY registers to their own header

Registers representing the MG/DKL TC PHYs (including the TC DPLLs which exist inside the PHY) are only needed in a couple files and on specific platforms; let's keep them separate from the general register pool. Cc: Jani Nikula Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_dd

[Intel-gfx] [PATCH v3 01/11] drm/i915: Use parameterized GPR register definitions everywhere

Since we have an engine-parameterized macro GEN8_RING_CS_GPR, let's use that in place of the HSW_CS_GPR and BCS_GPR register definitions. Cc: Jani Nikula Signed-off-by: Matt Roper Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/i915_cmd_parser.c | 68 ++ drivers/gpu/d

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Start cleaning up register definitions (rev3)

== Series Details == Series: Start cleaning up register definitions (rev3) URL : https://patchwork.freedesktop.org/series/98575/ State : warning == Summary == $ dim checkpatch origin/drm-tip e41d2f04b72a drm/i915: Use parameterized GPR register definitions everywhere -:22: ERROR:COMPLEX_MACRO:

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Start cleaning up register definitions (rev3)

== Series Details == Series: Start cleaning up register definitions (rev3) URL : https://patchwork.freedesktop.org/series/98575/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

Re: [Intel-gfx] [PATCH] drm/i915/display: Enable second VDSC engine for higher moderates

On Mon, Jan 10, 2022 at 08:24:54PM -0800, Kulkarni, Vandita wrote: > > -Original Message- > > From: Navare, Manasi D > > Sent: Tuesday, January 11, 2022 1:07 AM > > To: Kulkarni, Vandita > > Cc: Nikula, Jani ; Lisovskiy, Stanislav > > ; Ville Syrjälä > > ; > > intel-gfx@lists.freedesktop

[Intel-gfx] ✓ Fi.CI.BAT: success for Start cleaning up register definitions (rev3)

== Series Details == Series: Start cleaning up register definitions (rev3) URL : https://patchwork.freedesktop.org/series/98575/ State : success == Summary == CI Bug Log - changes from CI_DRM_11061 -> Patchwork_21961 Summary --- **SU

Re: [Intel-gfx] [GIT PULL] GVT next changes for drm-intel-next-queued

On 1/11/2022 12:52 AM, Vivi, Rodrigo wrote: > On Fri, 2022-01-07 at 14:43 +, Wang, Zhi A wrote: >> Hi folks: >> >> Happy holidays! This pull mostly contains the code re-factors patches >> from Guenter Roeck and Rikard. Also a minor change from Zhenyu. >> >> Zhi >> >> The following changes since

Re: [Intel-gfx] [PATCH] drm/i915/display: Enable second VDSC engine for higher moderates

> -Original Message- > From: Navare, Manasi D > Sent: Tuesday, January 11, 2022 11:42 AM > To: Kulkarni, Vandita > Cc: Nikula, Jani ; Lisovskiy, Stanislav > ; Ville Syrjälä > ; > intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH] drm/i915/display: Enable second VDSC > eng

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/snps: vswing value refined for SNPS phys

== Series Details == Series: drm/i915/snps: vswing value refined for SNPS phys URL : https://patchwork.freedesktop.org/series/98710/ State : success == Summary == CI Bug Log - changes from CI_DRM_11061_full -> Patchwork_21959_full Summary -

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