== Series Details ==
Series: drm/i915/adlp: Remove require_force_probe protection (rev2)
URL : https://patchwork.freedesktop.org/series/96939/
State : failure
== Summary ==
Applying: drm/i915/adlp: Remove require_force_probe protection
Using index info to reconstruct a base tree...
M dri
== Series Details ==
Series: Introduce new i915 macros for checking PTEs (rev5)
URL : https://patchwork.freedesktop.org/series/96679/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10963_full -> Patchwork_21750_full
Summary
== Series Details ==
Series: Update to GuC version 69.0.0
URL : https://patchwork.freedesktop.org/series/97564/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10963_full -> Patchwork_21752_full
Summary
---
**FAILURE**
== Series Details ==
Series: drm/i915/gem: Use local pointer for __i915_ttm_move
URL : https://patchwork.freedesktop.org/series/97571/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10963_full -> Patchwork_21753_full
Summary
== Series Details ==
Series: drm/i915/gem: Use local pointer ttm for __i915_ttm_move
URL : https://patchwork.freedesktop.org/series/97572/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10963_full -> Patchwork_21754_full
Sum
== Series Details ==
Series: drm/i915/selftests: Follow up on increase timeout in i915_gem_contexts
selftests
URL : https://patchwork.freedesktop.org/series/97577/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10963_full -> Patchwork_21755_full
===
== Series Details ==
Series: drm/i915: Rollback seqno when request creation fails (rev2)
URL : https://patchwork.freedesktop.org/series/97562/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10963_full -> Patchwork_21756_full
From: Michał Winiarski
Use to_gt() helper consistently throughout the codebase.
Pure mechanical s/i915->gt/to_gt(i915). No functional changes.
Signed-off-by: Michał Winiarski
Signed-off-by: Andi Shyti
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 4 ++--
drivers/gpu/drm/i915/display/i
From: Michał Winiarski
Use to_gt() helper consistently throughout the codebase.
Pure mechanical s/i915->gt/to_gt(i915). No functional changes.
Signed-off-by: Michał Winiarski
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/i915_debugfs.c| 38 +++
drivers/gpu/drm/i915/i9
From: Michał Winiarski
Use to_gt() helper consistently throughout the codebase.
Pure mechanical s/i915->gt/to_gt(i915). No functional changes.
Signed-off-by: Michał Winiarski
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gvt/gvt.c | 2 +-
drivers/gpu/drm/i915/gvt/scheduler.c | 2 +-
From: Michał Winiarski
To allow further refactoring and abstract away the fact that GT is
stored inside i915 private.
No functional changes.
Signed-off-by: Michał Winiarski
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.c | 7 +--
drivers/gpu/drm/i915/i915_drv.
Use to_gt() helper consistently throughout the codebase.
Pure mechanical s/i915->gt/to_gt(i915). No functional changes.
Signed-off-by: Andi Shyti
Cc: Michał Winiarski
---
drivers/gpu/drm/i915/selftests/i915_active.c | 2 +-
drivers/gpu/drm/i915/selftests/i915_gem.c | 2 +-
.../gpu/drm/i9
From: Michał Winiarski
Use to_gt() helper consistently throughout the codebase.
Pure mechanical s/i915->gt/to_gt(i915). No functional changes.
Signed-off-by: Michał Winiarski
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 22
drivers/gpu/drm/i91
From: Michał Winiarski
We now support a per-gt uncore, yet we're not able to infer which GT
we're operating upon. Let's store a backpointer for now.
Signed-off-by: Michał Winiarski
Signed-off-by: Matt Roper
Reviewed-by: Andi Shyti
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel
From: Michał Winiarski
Use to_gt() helper consistently throughout the codebase.
Pure mechanical s/i915->gt/to_gt(i915). No functional changes.
Signed-off-by: Michał Winiarski
Singed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 +-
drivers/gpu/drm/i915/gt/int
Hi,
the first patch concludes the first stage of refactoring which
makes the use of intel_gt on the different subsystem. It's taken
from Matt's series and it has alread been reviewed. The patch has
just been replaced before any multitile patches and I think it
can be already pushed.
Patch 2-10 ar
Use to_gt() helper consistently throughout the codebase.
Pure mechanical s/i915->gt/to_gt(i915). No functional changes.
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_
In preparation of the multitile support, highlight the root GT by
calling it gt0 inside the drm i915 private data.
Signed-off-by: Andi Shyti
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Lucas De Marchi
Cc: Rodrigo Vivi
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
1 file chan
On 04/12/2021 01:38, Dixit, Ashutosh wrote:
On Fri, 03 Dec 2021 07:54:56 -0800, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Use the i915 exported data in /proc//fdinfo to show GPU utilization
per DRM client.
Didn't we just remove it? Adding it back now? Sorry for the probably dumb
question
> -Original Message-
> From: Tvrtko Ursulin
> Sent: Friday, December 3, 2021 2:57 PM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Cc: x...@kernel.org; dri-de...@lists.freedesktop.org; Ingo Molnar
> ; Borislav Petkov ; Dave Hansen
> ; Joonas Lahtinen
> ; Nikula, Jani
>
From: Michał Winiarski
GGTT is currently available both through i915->ggtt and gt->ggtt, and we
eventually want to get rid of the i915->ggtt one.
Use to_gt() for all i915->ggtt accesses to help with the future
refactoring.
Signed-off-by: Michał Winiarski
Cc: Michal Wajdeczko
Signed-off-by: And
add GEM_BUG_ON to check for NULL ptr dereferences with
obj ptr, this will help catch exceptions in CI tests.
v2 change commit text
Signed-off-by: Pallavi Mishra
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 3 +++
drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 3 ++-
2 files changed, 5 ins
We need a way to reset engines by their reset domains.
This change sets up way to fetch reset domains of each
engine globally.
Changes since V1:
- Use static reset domain array - Ville and Tvrtko
- Use BUG_ON at appropriate place - Tvrtko
Signed-off-by: Tejas Upadhyay
---
driver
Ensure we add the engine base only after we calculate the qword offset
into the PTE window.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Ramalingam C
Reviewed-by: Ramalingam C
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
No need to insert PTEs for the PTE window itself, also foreach expects a
length not an end offset, which could be gigantic here with a second
engine.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Ramalingam C
Reviewed-by: Ramalingam C
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 2 +-
Ensure we account for any object rounding due to min_page_size
restrictions.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Ramalingam C
Reviewed-by: Ramalingam C
---
drivers/gpu/drm/i915/gt/selftest_migrate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gt/s
The scratch page might not be allocated in LMEM(like on DG2), so instead
of using that as the deciding factor for where the paging structures
live, let's just query the pt before mapping it.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Ramalingam C
Reviewed-by: Ramalingam C
---
driver
== Series Details ==
Series: More preparation for multi gt patches (rev5)
URL : https://patchwork.freedesktop.org/series/97020/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
664bf127629d drm/i915: Store backpointer to GT in uncore
6126245f7f9b drm/i915: Introduce to_gt() helper
== Series Details ==
Series: More preparation for multi gt patches (rev5)
URL : https://patchwork.freedesktop.org/series/97020/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: More preparation for multi gt patches (rev5)
URL : https://patchwork.freedesktop.org/series/97020/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10965 -> Patchwork_21759
Summary
---
**FAI
== Series Details ==
Series: drm/i915: Use GEM_BUG_ON for obj ptr NULL check
URL : https://patchwork.freedesktop.org/series/97605/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10965 -> Patchwork_21760
Summary
---
**
== Series Details ==
Series: drm/i915/gt: Use hw_engine_masks as reset_domains (rev2)
URL : https://patchwork.freedesktop.org/series/97543/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/gt: Use hw_engine_masks as reset_domains (rev2)
URL : https://patchwork.freedesktop.org/series/97543/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10965 -> Patchwork_21761
Summary
On Mon, 29 Nov 2021 at 13:57, Maarten Lankhorst
wrote:
>
> Big delta, but boils down to moving set_pages to i915_vma.c, and removing
> the special handling, all callers use the defaults anyway. We only remap
> in ggtt, so default case will fall through.
>
> Because we still don't require locking i
On Mon, 29 Nov 2021 at 13:58, Maarten Lankhorst
wrote:
>
> i915_vma_wait_for_bind needs the vma lock held, fix the caller.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Matthew Auld
It is never modified, so make it const to allow the compiler to put it
in read-only memory.
Signed-off-by: Rikard Falkeborn
---
drivers/gpu/drm/i915/gvt/gtt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index
These are never modified, so make them const to allow the compiler to
put them in read-only memory.
Signed-off-by: Rikard Falkeborn
---
drivers/gpu/drm/i915/gvt/interrupt.c | 10 +-
drivers/gpu/drm/i915/gvt/interrupt.h | 2 +-
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git
Constify a number of static structs that are never modified to allow the
compiler to put them in read-only memory. In order to do this, constify a
number of local variables and pointers in structs.
This is most important for structs that contain function pointers, and
the patches for those structs
These are never modified, so make them const to allow the compiler to
put them in read-only memory.
Signed-off-by: Rikard Falkeborn
---
drivers/gpu/drm/i915/gvt/gtt.c | 4 ++--
drivers/gpu/drm/i915/gvt/gtt.h | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i
It is never modified, so make it const to allow the compiler to put it
in read-only memory. While at it, make name a const char*.
Signed-off-by: Rikard Falkeborn
---
drivers/gpu/drm/i915/gvt/vgpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/v
These are never modified, so make them const to allow the compiler to
put them in read-only memory.
Signed-off-by: Rikard Falkeborn
---
drivers/gpu/drm/i915/gvt/sched_policy.c | 2 +-
drivers/gpu/drm/i915/gvt/scheduler.h| 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/d
It is never modified, so make it const to allow the compiler to put it
in read-only memory.
Signed-off-by: Rikard Falkeborn
---
drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c
b/drivers/gpu/drm/i915/
These are never modified, so make them const to allow the compiler to
put it in read-only memory.
Signed-off-by: Rikard Falkeborn
---
drivers/gpu/drm/i915/gvt/gvt.h | 2 +-
drivers/gpu/drm/i915/gvt/handlers.c | 12 ++--
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a
These are never modified, so make them const to allow the compiler to
put them in read-only memory. WHile at it, make the description const
char* since it is never modified.
Signed-off-by: Rikard Falkeborn
---
drivers/gpu/drm/i915/gvt/fb_decoder.c | 24
1 file changed, 1
These are never modified, so make them const to allow the compiler to
put them in read-only memory.
Signed-off-by: Rikard Falkeborn
---
drivers/gpu/drm/i915/gvt/gtt.c | 62 +-
drivers/gpu/drm/i915/gvt/gtt.h | 2 +-
2 files changed, 32 insertions(+), 32 deletions(
Enable accelerated moves and clearing on DG2. On such HW we have minimum page
size restrictions when accessing LMEM from the GTT, where we now have to use 64K
GTT pages or larger. With the ppGTT the page-table also has a slightly different
layout from past generations when using the 64K GTT mode(wh
The scratch page might not be allocated in LMEM(like on DG2), so instead
of using that as the deciding factor for where the paging structures
live, let's just query the pt before mapping it.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Ramalingam C
Reviewed-by: Ramalingam C
---
driver
Ensure we add the engine base only after we calculate the qword offset
into the PTE window.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Ramalingam C
Reviewed-by: Ramalingam C
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
No need to insert PTEs for the PTE window itself, also foreach expects a
length not an end offset, which could be gigantic here with a second
engine.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Ramalingam C
Reviewed-by: Ramalingam C
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 2 +-
Ensure we account for any object rounding due to min_page_size
restrictions.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Ramalingam C
Reviewed-by: Ramalingam C
---
drivers/gpu/drm/i915/gt/selftest_migrate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gt/s
On some platforms we have alignment restrictions when accessing LMEM
from the GTT. In the next patch few patches we need to be able to modify
the page-tables directly via the GTT itself.
Suggested-by: Ramalingam C
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Ramalingam C
---
drivers/g
If this is LMEM then we get a 32 entry PT, with each PTE pointing to
some 64K block of memory, otherwise it's just the usual 512 entry PT.
This very much assumes the caller knows what they are doing.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Ramalingam C
Reviewed-by: Ramalingam C
--
This is all kinds of awkward since we now have to contend with using 64K
GTT pages when mapping anything in LMEM(including the page-tables
themselves).
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Ramalingam C
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 189 +++-
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Ramalingam C
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c
b/drivers/gpu/drm/i915/gt/intel_migrate.c
index fb658ae70a8d..0fb83d0bec91 100644
--- a/dri
== Series Details ==
Series: drm/i915/gvt: Constify static structs
URL : https://patchwork.freedesktop.org/series/97616/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ad6d0d2d2854 drm/i915/gvt: Constify intel_gvt_gtt_pte_ops
9f75a74af3af drm/i915/gvt: Constify intel_gvt_gtt_pte
== Series Details ==
Series: series starting with [1/4] drm/i915/migrate: don't check the scratch
page
URL : https://patchwork.freedesktop.org/series/97610/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10965 -> Patchwork_21762
== Series Details ==
Series: DG2 accelerated migration/clearing support (rev2)
URL : https://patchwork.freedesktop.org/series/97544/
State : failure
== Summary ==
Applying: drm/i915/migrate: don't check the scratch page
Applying: drm/i915/migrate: fix offset calculation
Applying: drm/i915/migr
== Series Details ==
Series: drm/i915/gvt: Constify static structs
URL : https://patchwork.freedesktop.org/series/97616/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10965 -> Patchwork_21763
Summary
---
**FAILURE**
Hi Matthew,
On Mon, 6 Dec 2021 at 13:32, Matthew Auld wrote:
> Enable accelerated moves and clearing on DG2. On such HW we have minimum page
> size restrictions when accessing LMEM from the GTT, where we now have to use
> 64K
> GTT pages or larger. With the ppGTT the page-table also has a slight
== Series Details ==
Series: drm/i915: Use GEM_BUG_ON for obj ptr NULL check
URL : https://patchwork.freedesktop.org/series/97605/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10965_full -> Patchwork_21760_full
Summary
---
On 06/12/2021 14:49, Daniel Stone wrote:
Hi Matthew,
On Mon, 6 Dec 2021 at 13:32, Matthew Auld wrote:
Enable accelerated moves and clearing on DG2. On such HW we have minimum page
size restrictions when accessing LMEM from the GTT, where we now have to use 64K
GTT pages or larger. With the ppG
On 06-12-2021 14:13, Matthew Auld wrote:
> On Mon, 29 Nov 2021 at 13:57, Maarten Lankhorst
> wrote:
>> Big delta, but boils down to moving set_pages to i915_vma.c, and removing
>> the special handling, all callers use the defaults anyway. We only remap
>> in ggtt, so default case will fall through
== Series Details ==
Series: drm/i915/gt: Use hw_engine_masks as reset_domains (rev2)
URL : https://patchwork.freedesktop.org/series/97543/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10965_full -> Patchwork_21761_full
Su
Hi Ville,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to drm-tip/drm-tip v5.16-rc4 next-20211206]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '-
== Series Details ==
Series: series starting with [1/4] drm/i915/migrate: don't check the scratch
page
URL : https://patchwork.freedesktop.org/series/97610/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10965_full -> Patchwork_21762_full
==
On Mon, 6 Dec 2021 at 15:18, Maarten Lankhorst
wrote:
>
> On 06-12-2021 14:13, Matthew Auld wrote:
> > On Mon, 29 Nov 2021 at 13:57, Maarten Lankhorst
> > wrote:
> >> Big delta, but boils down to moving set_pages to i915_vma.c, and removing
> >> the special handling, all callers use the defaults
On Mon, 29 Nov 2021 at 13:57, Maarten Lankhorst
wrote:
>
> Big delta, but boils down to moving set_pages to i915_vma.c, and removing
> the special handling, all callers use the defaults anyway. We only remap
> in ggtt, so default case will fall through.
>
> Because we still don't require locking i
== Series Details ==
Series: Introduce new i915 macros for checking PTEs (rev6)
URL : https://patchwork.freedesktop.org/series/96679/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Introduce new i915 macros for checking PTEs (rev6)
URL : https://patchwork.freedesktop.org/series/96679/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10965 -> Patchwork_21765
Summary
---
Hi Ville,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to drm-tip/drm-tip v5.16-rc4 next-20211206]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '-
Michal, do you know what this is complaining about?
John.
On 12/3/2021 14:27, Patchwork wrote:
== Series Details ==
Series: Update to GuC version 69.0.0
URL : https://patchwork.freedesktop.org/series/97564/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
/home/ci
On 11/11/2021 13:20, Matthew Brost wrote:
A weak implementation of parallel submission (multi-bb execbuf IOCTL) for
execlists. Doing as little as possible to support this interface for
execlists - basically just passing submit fences between each request
generated and virtual engines are not allo
== Series Details ==
Series: Introduce new i915 macros for checking PTEs (rev6)
URL : https://patchwork.freedesktop.org/series/96679/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10965_full -> Patchwork_21765_full
Summary
This series is to introduce new macros generic to i915 for checking 0 and 1
bits, instead on relying on whats defined by the mmu, since it could
be different or non-exisitent between different platforms.
v2: Corrected sender's email.
v3: Corrected spelling error.
v4: Clean up a few other macros
Certain functions within i915 uses macros that are defined for
specific architectures by the mmu, such as _PAGE_RW and _PAGE_PRESENT
(Some architectures don't even have these macros defined, like ARM64).
Instead of re-using bits defined for the CPU, we should use bits
defined for i915. This patch
On 12/3/2021 10:33 AM, john.c.harri...@intel.com wrote:
From: John Harrison
It is possible for platforms to require GuC but not HuC firmware.
Also, the firmware versions for GuC and HuC advance independently. So
split the macros up to allow the lists to be maintained separately.
Signed-off-
== Series Details ==
Series: Introduce new i915 macros for checking PTEs (rev7)
URL : https://patchwork.freedesktop.org/series/96679/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On 06.12.2021 20:29, John Harrison wrote:
> Michal, do you know what this is complaining about?
broken links definitions, fix below
Michal
diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
b/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
index d09d6a5bb63b..6aa3cf7172f7 100644
--- a/d
== Series Details ==
Series: Introduce new i915 macros for checking PTEs (rev7)
URL : https://patchwork.freedesktop.org/series/96679/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10965 -> Patchwork_21766
Summary
---
== Series Details ==
Series: Introduce new i915 macros for checking PTEs (rev7)
URL : https://patchwork.freedesktop.org/series/96679/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10965_full -> Patchwork_21766_full
Summary
Follow up on commit 5e076529e265 ("drm/i915/selftests: Increase timeout in
i915_gem_contexts selftests")
So we went from 200 msec to 1sec in that commit, and now we are going to
10sec as timeout.
Signed-off-by: Bruce Chang
Reviewed-by: Matthew Brost
Cc: John Harrison
---
drivers/gpu/drm/i915/
GuC PMU busyness gets gt wakeref if awake, but fails to release the
wakeref if a reset is in progress. Release the wakeref if it was
acquried successfully.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 8 ++--
1 file changed, 6 insertions(+), 2
== Series Details ==
Series: drm/i915/selftests: Follow up on increase timeout in i915_gem_contexts
selftests (rev2)
URL : https://patchwork.freedesktop.org/series/97577/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10965 -> Patchwork_21767
==
On Mon, 06 Dec 2021 16:45:42 -0800, Umesh Nerlige Ramappa wrote:
>
> GuC PMU busyness gets gt wakeref if awake, but fails to release the
> wakeref if a reset is in progress. Release the wakeref if it was
> acquried successfully.
>
> Signed-off-by: Umesh Nerlige Ramappa
> ---
> drivers/gpu/drm/i91
== Series Details ==
Series: drm/i915/pmu: Fix wakeref leak in PMU busyness during reset
URL : https://patchwork.freedesktop.org/series/97635/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10965 -> Patchwork_21768
Summary
-
GuC PMU busyness gets gt wakeref if awake, but fails to release the
wakeref if a reset is in progress. Release the wakeref if it was
acquried successfully.
v2: Simplify the fix (Ashutosh)
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
1 file c
On Mon, Dec 06, 2021 at 05:30:43PM -0800, Dixit, Ashutosh wrote:
On Mon, 06 Dec 2021 16:45:42 -0800, Umesh Nerlige Ramappa wrote:
GuC PMU busyness gets gt wakeref if awake, but fails to release the
wakeref if a reset is in progress. Release the wakeref if it was
acquried successfully.
Signed-o
On Mon, 06 Dec 2021 18:02:39 -0800, Umesh Nerlige Ramappa wrote:
>
> GuC PMU busyness gets gt wakeref if awake, but fails to release the
> wakeref if a reset is in progress. Release the wakeref if it was
> acquried successfully.
>
> v2: Simplify the fix (Ashutosh)
Reviewed-by: Ashutosh Dixit
> S
Increase the size of DMC on ADL-P to account for support of
new features in the current/upcoming DMC versions.
Signed-off-by: Madhumitha Tolakanahalli Pradeep
---
drivers/gpu/drm/i915/display/intel_dmc.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915
== Series Details ==
Series: drm/i915/pmu: Fix wakeref leak in PMU busyness during reset (rev2)
URL : https://patchwork.freedesktop.org/series/97635/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10965 -> Patchwork_21769
Su
== Series Details ==
Series: drm/i915/selftests: Follow up on increase timeout in i915_gem_contexts
selftests (rev2)
URL : https://patchwork.freedesktop.org/series/97577/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10965_full -> Patchwork_21767_full
== Series Details ==
Series: drm/i915/dmc: Change DMC FW size on ADL-P
URL : https://patchwork.freedesktop.org/series/97638/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10965 -> Patchwork_21770
Summary
---
**SUCCES
On Mon, Dec 06, 2021 at 01:52:45PM -0800, Michael Cheng wrote:
Certain functions within i915 uses macros that are defined for
specific architectures by the mmu, such as _PAGE_RW and _PAGE_PRESENT
(Some architectures don't even have these macros defined, like ARM64).
Instead of re-using bits defi
== Series Details ==
Series: drm/i915/pmu: Fix wakeref leak in PMU busyness during reset
URL : https://patchwork.freedesktop.org/series/97635/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10965_full -> Patchwork_21768_full
== Series Details ==
Series: drm/i915/pmu: Fix wakeref leak in PMU busyness during reset (rev2)
URL : https://patchwork.freedesktop.org/series/97635/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10965_full -> Patchwork_21769_full
==
== Series Details ==
Series: drm/i915/dmc: Change DMC FW size on ADL-P
URL : https://patchwork.freedesktop.org/series/97638/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10965_full -> Patchwork_21770_full
Summary
---
On Mon, Dec 06, 2021 at 06:37:18PM -0800, Madhumitha Tolakanahalli Pradeep
wrote:
Increase the size of DMC on ADL-P to account for support of
new features in the current/upcoming DMC versions.
I was trying to find anything related on Bspec 49193 and 49194, but
didn't find anything related to s
> -Original Message-
> From: Jani Nikula
> Sent: Tuesday, November 30, 2021 3:36 PM
> To: Ville Syrjälä
> Cc: Shankar, Uma ; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH v2 2/3] drm/i915/xelpd: Enable Pipe Degamma
>
> On Tue, 30 Nov 2021, Ville Syrjälä wrote:
> >
> -Original Message-
> From: Ville Syrjälä
> Sent: Tuesday, November 30, 2021 3:33 PM
> To: Shankar, Uma
> Cc: intel-gfx@lists.freedesktop.org; Modem, Bhanuprakash
>
> Subject: Re: [PATCH v2 3/3] drm/i915/xelpd: Add Pipe Color Lut caps to
> platform
> config
>
> On Fri, Nov 26, 2021
On Mon, Dec 06, 2021 at 07:36:39PM -0800, Lucas De Marchi wrote:
On Mon, Dec 06, 2021 at 01:52:45PM -0800, Michael Cheng wrote:
Certain functions within i915 uses macros that are defined for
specific architectures by the mmu, such as _PAGE_RW and _PAGE_PRESENT
(Some architectures don't even have
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