On Tue, 12 Oct 2021 19:11:29 +
"Shankar, Uma" wrote:
> > -Original Message-
> > From: Pekka Paalanen
> > Sent: Tuesday, October 12, 2021 5:30 PM
> > To: Simon Ser
> > Cc: Shankar, Uma ; intel-gfx@lists.freedesktop.org;
> > dri-
> > de...@lists.freedesktop.org; harry.wentl...@amd.co
Currently, enabling CONFIG_STACKDEPOT means its stack_table will be allocated
from memblock, even if stack depot ends up not actually used. The default size
of stack_table is 4MB on 32-bit, 8MB on 64-bit.
This is fine for use-cases such as KASAN which is also a config option and
has overhead on it
== Series Details ==
Series: lib/stackdepot: allow optional init and stack_table allocation by
kvmalloc() (rev3)
URL : https://patchwork.freedesktop.org/series/95549/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
50fb572ebbb4 lib/stackdepot: allow optional init and stack_table
== Series Details ==
Series: lib/stackdepot: allow optional init and stack_table allocation by
kvmalloc() (rev3)
URL : https://patchwork.freedesktop.org/series/95549/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10728 -> Patchwork_21326
==
On 2021/10/13 10:54, Matt Roper wrote:
On Tue, Oct 12, 2021 at 06:00:46PM -0700, José Roberto de Souza wrote:
This memory frequency calculated is only used to check if it is zero,
what is not useful as it will never actually be zero.
Also the calculation is wrong, we should be checking other
Hi,
sorry, just forgot to add the changelog
On Wed, Oct 13, 2021 at 12:17:38AM +0200, Andi Shyti wrote:
> From: Andi Shyti
>
> The following interfaces:
>
> i915_wedged
> i915_forcewake_user
>
> are dependent on gt values. Put them inside gt/ and drop the
> "i915_" prefix name. This would
== Series Details ==
Series: drm/i915/gt: move remaining debugfs interfaces into gt (rev12)
URL : https://patchwork.freedesktop.org/series/75333/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10728_full -> Patchwork_21322_full
==
On Tue, 12 Oct 2021 20:58:27 +
"Shankar, Uma" wrote:
> > -Original Message-
> > From: Pekka Paalanen
> > Sent: Tuesday, October 12, 2021 4:01 PM
> > To: Shankar, Uma
> > Cc: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
> > harry.wentl...@amd.com; ville.syrj...@
== Series Details ==
Series: drm/i915: Remove memory frequency calculation (rev2)
URL : https://patchwork.freedesktop.org/series/95748/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10728_full -> Patchwork_21324_full
Summar
On Tue, Oct 12, 2021 at 06:00:46PM -0700, José Roberto de Souza wrote:
> This memory frequency calculated is only used to check if it is zero,
> what is not useful as it will never actually be zero.
>
> Also the calculation is wrong, we should be checking other bit to
> select the appropriate freq
Three main ideas here:
- vlv sideband only has the name "sideband" in common with the rest of
intel_sideband.[ch]
- we may need better abstractions on the dependency,
this should help a little bit; maybe vlv_sideband.[ch] can be turned
into that abstraction layer
- we probably want to spl
The VLV/CHV sideband code is pretty distinct from the rest of the
sideband code. Split it out to new vlv_sideband.[ch].
Pure code movement with relevant #include changes, and a tiny checkpatch
fix on top.
Cc: Lucas De Marchi
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i91
== Series Details ==
Series: lib/stackdepot: allow optional init and stack_table allocation by
kvmalloc() (rev3)
URL : https://patchwork.freedesktop.org/series/95549/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10728_full -> Patchwork_21326_full
== Series Details ==
Series: drm/i915: vlv sideband
URL : https://patchwork.freedesktop.org/series/95764/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ba91b0757d4b drm/i915: split out vlv sideband to a separate file
-:666: WARNING:FILE_PATH_CHANGES: added, moved or deleted fil
On Wed, Oct 13, 2021 at 01:11:58PM +0300, Jani Nikula wrote:
> Three main ideas here:
>
> - vlv sideband only has the name "sideband" in common with the rest of
> intel_sideband.[ch]
I wouldn't put it like that. There are two actual sideband
implementtions in that file:
- vlv/chv iosf sideband
No memory should be allocated when calling i915_gem_object_wait,
because it may be called to idle a BO when evicting memory.
Fix this by using dma_resv_iter helpers to call
i915_gem_object_wait_fence() on each fence, which cleans up the code a lot.
Also remove dma_resv_prune, it's questionably.
T
On Wed, 13 Oct 2021, Ville Syrjälä wrote:
> On Wed, Oct 13, 2021 at 01:11:58PM +0300, Jani Nikula wrote:
>> Three main ideas here:
>>
>> - vlv sideband only has the name "sideband" in common with the rest of
>> intel_sideband.[ch]
>
> I wouldn't put it like that. There are two actual sideband
== Series Details ==
Series: drm/i915: vlv sideband
URL : https://patchwork.freedesktop.org/series/95764/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10728 -> Patchwork_21327
Summary
---
**SUCCESS**
No regressio
== Series Details ==
Series: drm/i915: Use dma_resv_iter for waiting in
i915_gem_object_wait_reservation.
URL : https://patchwork.freedesktop.org/series/95765/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK
On Wed, Oct 13, 2021 at 01:47:09PM +0300, Jani Nikula wrote:
> On Wed, 13 Oct 2021, Ville Syrjälä wrote:
> > On Wed, Oct 13, 2021 at 01:11:58PM +0300, Jani Nikula wrote:
> >> Three main ideas here:
> >>
> >> - vlv sideband only has the name "sideband" in common with the rest of
> >> intel_sideb
No memory should be allocated when calling i915_gem_object_wait,
because it may be called to idle a BO when evicting memory.
Fix this by using dma_resv_iter helpers to call
i915_gem_object_wait_fence() on each fence, which cleans up the code a lot.
Also remove dma_resv_prune, it's questionably.
T
On Mon, 11 Oct 2021, Len Baker wrote:
> Hi,
>
> On Sun, Oct 03, 2021 at 12:42:58PM +0200, Len Baker wrote:
>> As noted in the "Deprecated Interfaces, Language Features, Attributes,
>> and Conventions" documentation [1], size calculations (especially
>> multiplication) should not be performed in me
On Fri, 08 Oct 2021, Sujaritha Sundaresan
wrote:
> This patch adds the following new sysfs frequency attributes;
Why?
Sysfs is uapi. What's the userspace consumer for these?
More comments inline.
> - punit_req_freq_mhz
> - throttle_reason_status
> - throttle_reason_pl1
>
On Wed, Oct 13, 2021 at 02:24:05PM +0300, Jani Nikula wrote:
> On Mon, 11 Oct 2021, Len Baker wrote:
> > Hi,
> >
> > On Sun, Oct 03, 2021 at 12:42:58PM +0200, Len Baker wrote:
> >> As noted in the "Deprecated Interfaces, Language Features, Attributes,
> >> and Conventions" documentation [1], size
Hi,
On 10/13/21 12:11 PM, Jani Nikula wrote:
> The VLV/CHV sideband code is pretty distinct from the rest of the
> sideband code. Split it out to new vlv_sideband.[ch].
>
> Pure code movement with relevant #include changes, and a tiny checkpatch
> fix on top.
>
> Cc: Lucas De Marchi
> Cc: Ville
On Wed, Oct 13, 2021 at 12:54 PM Arnd Bergmann wrote:
> On Thu, Oct 7, 2021 at 11:51 AM Geert Uytterhoeven
> wrote:
>
> -msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o
> -msm-$(CONFIG_COMMON_CLK) += disp/mdp4/mdp4_lvds_pll.o
> -msm-$(CONFIG_COMMON_CLK) += hdmi/hdmi_pll_8960.o
> -msm-$(CONFIG_C
On Thu, Oct 7, 2021 at 11:51 AM Geert Uytterhoeven wrote:
> On Wed, Oct 6, 2021 at 9:28 AM Christian König
> wrote:
> > Am 06.10.21 um 09:20 schrieb Stephen Rothwell:
> > > On Tue, 5 Oct 2021 22:48:03 -0700 Randy Dunlap
> > > wrote:
> > >> on i386:
> > >>
> > >> ld: drivers/gpu/drm/msm/hdmi/hd
On Mon, Oct 04, 2021 at 02:15:51PM +0300, Ville Syrjälä wrote:
> On Tue, Jul 20, 2021 at 03:44:49PM +0200, Daniel Vetter wrote:
> > On Thu, Jul 15, 2021 at 09:49:51PM +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > Quite a few places are hand rolling the modeset lock backoff dan
On Wed, Oct 06, 2021 at 10:12:29AM -0700, Matthew Brost wrote:
> On Mon, Oct 04, 2021 at 03:36:48PM +0100, Tvrtko Ursulin wrote:
> > From: Tvrtko Ursulin
> >
> > Code added in 71ed60112d5d ("drm/i915: Add kick_backend function to
> > i915_sched_engine") and ee242ca704d3 ("drm/i915/guc: Implement
On Tue, Oct 05, 2021 at 08:51:51AM +0200, Sebastian Andrzej Siewior wrote:
> The warning poped up, it says it increase it by the number of occurrence.
> I saw it 18 times so here it is.
> It started to up since commit
>2f425cf5242a0 ("drm: Fix oops in damage self-tests by mocking damage
> prop
On Tue, Oct 05, 2021 at 03:05:25PM +0200, Thomas Hellström wrote:
> Hi, Tvrtko,
>
> On 10/5/21 13:31, Tvrtko Ursulin wrote:
> > From: Tvrtko Ursulin
> >
> > In short this makes i915 work for hybrid setups (DRI_PRIME=1 with Mesa)
> > when rendering is done on Intel dgfx and scanout/composition on
On Wed, Oct 13, 2021 at 01:59:47PM +0200, Daniel Vetter wrote:
> On Mon, Oct 04, 2021 at 02:15:51PM +0300, Ville Syrjälä wrote:
> > On Tue, Jul 20, 2021 at 03:44:49PM +0200, Daniel Vetter wrote:
> > > On Thu, Jul 15, 2021 at 09:49:51PM +0300, Ville Syrjala wrote:
> > > > From: Ville Syrjälä
> > >
On Fri, 08 Oct 2021, Matt Roper wrote:
> On a multi-tile platform, each tile has its own registers + GGTT space,
> and BAR 0 is extended to cover all of them. Upcoming patches will start
> exposing the tiles as multiple GTs within a single PCI device. In
> preparation for supporting such setups,
No memory should be allocated when calling i915_gem_object_wait,
because it may be called to idle a BO when evicting memory.
Fix this by using dma_resv_iter helpers to call
i915_gem_object_wait_fence() on each fence, which cleans up the code a lot.
Also remove dma_resv_prune, it's questionably.
T
On 2021-10-13 14:02:59 [+0200], Daniel Vetter wrote:
> On Tue, Oct 05, 2021 at 08:51:51AM +0200, Sebastian Andrzej Siewior wrote:
> > The warning poped up, it says it increase it by the number of occurrence.
> > I saw it 18 times so here it is.
> > It started to up since commit
> >2f425cf5242a0
On Fri, Oct 08, 2021 at 03:35:25PM +0200, Thomas Hellström wrote:
> Move the release callback to after fence signaling to align with
> what's done for upcoming VM_BIND user-fence signaling.
>
> Finally call the work callback regardless of whether we have a fence
> error or not and update the exist
On Fri, Oct 08, 2021 at 03:35:28PM +0200, Thomas Hellström wrote:
> The TTM managers and, possibly, the gtt address space managers will
> need to be able to order fences for async operation.
> Using dma_fence_is_later() for this will require that the fences we hand
> them are from a single fence co
On Wed, Oct 13, 2021 at 02:35:25PM +0200, Sebastian Andrzej Siewior wrote:
> On 2021-10-13 14:02:59 [+0200], Daniel Vetter wrote:
> > On Tue, Oct 05, 2021 at 08:51:51AM +0200, Sebastian Andrzej Siewior wrote:
> > > The warning poped up, it says it increase it by the number of occurrence.
> > > I sa
On 10/13/21 14:41, Daniel Vetter wrote:
On Fri, Oct 08, 2021 at 03:35:25PM +0200, Thomas Hellström wrote:
Move the release callback to after fence signaling to align with
what's done for upcoming VM_BIND user-fence signaling.
Finally call the work callback regardless of whether we have a fenc
On Fri, 01 Oct 2021, Jani Nikula wrote:
> If drm_modeset_lock() returns -EDEADLK, the caller is supposed to drop
> all currently held locks using drm_modeset_backoff(). Failing to do so
> will result in warnings and backtraces on the paths trying to lock a
> contended lock. Add support for optiona
On Wed, Oct 06, 2021 at 04:47:57PM +0300, Kai Vehmanen wrote:
> Hi,
>
> On Tue, 5 Oct 2021, Greg KH wrote:
>
> > On Wed, Sep 22, 2021 at 11:54:32AM +0300, Kai Vehmanen wrote:
> > > In current code, the devres group for aggregate master is left open
> > > after call to component_master_add_*(). Th
== Series Details ==
Series: drm/i915: vlv sideband
URL : https://patchwork.freedesktop.org/series/95764/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10728_full -> Patchwork_21327_full
Summary
---
**FAILURE**
Se
On Mon, Oct 11, 2021 at 09:41:44PM +0530, Ramalingam C wrote:
> From: Matthew Auld
>
> For local-memory objects we need to align the GTT addresses to 64K, both
> for the ppgtt and ggtt.
>
> Signed-off-by: Matthew Auld
> Signed-off-by: Stuart Summers
> Signed-off-by: Ramalingam C
> Cc: Joonas
Hi Maarten,
I love your patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip drm-exynos/exynos-drm-next
tegra-drm/drm/tegra/for-next v5.15-rc5 next-20211013]
[cannot apply to airlied/drm-next]
[If your patch is applied to
On Mon, Oct 11, 2021 at 09:41:54PM +0530, Ramalingam C wrote:
> From: Matthew Auld
>
> On discrete platforms like DG2, we need to support a minimum page size
> of 64K when dealing with device local-memory. This is quite tricky for
> various reasons, so try to document the new implicit uapi for th
On Mon, Oct 11, 2021 at 09:41:55PM +0530, Ramalingam C wrote:
> Details of the new features getting added as part of DG2 enabling and their
> implicit impact on the uAPI.
>
> Signed-off-by: Ramalingam C
> cc: Daniel Vetter
> cc: Matthew Auld
> ---
> Documentation/gpu/rfc/i915_dg2.rst | 47
On Mon, Oct 11, 2021 at 09:41:41PM +0530, Ramalingam C wrote:
> This series introduces the enabling patches for new flat ccs feature and
> 64k page support for i915 local memory, along with documentation on the
> uAPI impact.
>
> 64k page support
>
>
> On discrete platforms, star
On Wed, Oct 13, 2021 at 07:05:34PM +0530, Arunpravin wrote:
> Port Intel buddy manager to drm root folder
One patch to move it 1:1, then follow-up patches to change it. Not
everything in one.
Also i915 needs to be adopted to use this too, or this just doesn't make
sense.
I'm also wondering wheth
On Wed, Oct 13, 2021 at 02:32:03PM +0200, Maarten Lankhorst wrote:
> No memory should be allocated when calling i915_gem_object_wait,
> because it may be called to idle a BO when evicting memory.
>
> Fix this by using dma_resv_iter helpers to call
> i915_gem_object_wait_fence() on each fence, whic
On Tue, Oct 05, 2021 at 01:37:17PM +0200, Christian König wrote:
> Just exercising a very minor subset of the functionality, but already
> proven useful.
>
> v2: add missing locking
> v3: some more cleanup and consolidation, add unlocked test as well
>
> Signed-off-by: Christian König
Yeah this
On Tue, Oct 05, 2021 at 01:37:25PM +0200, Christian König wrote:
> Simplifying the code a bit.
>
> Signed-off-by: Christian König
Reviewed-by: Daniel Vetter
Yeah these iterators rock :-)
-Daniel
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 44
> 1 file changed,
On Tue, Oct 05, 2021 at 01:37:26PM +0200, Christian König wrote:
> Simplifying the code a bit.
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 14 --
> 1 file changed, 4 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/a
On Tue, Oct 05, 2021 at 01:37:27PM +0200, Christian König wrote:
> No need to actually allocate an array of fences here.
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 26 +-
> 1 file changed, 5 insertions(+), 21 deletions(-)
>
> diff
On 13/10/2021 14:38, Daniel Vetter wrote:
On Mon, Oct 11, 2021 at 09:41:44PM +0530, Ramalingam C wrote:
From: Matthew Auld
For local-memory objects we need to align the GTT addresses to 64K, both
for the ppgtt and ggtt.
Signed-off-by: Matthew Auld
Signed-off-by: Stuart Summers
Signed-off-by
On Tue, Oct 05, 2021 at 01:37:28PM +0200, Christian König wrote:
> Simplifying the code a bit. Also drop the RCU read side lock since the
> object is locked anyway.
>
> Untested since I can't get the driver to compile on !ARM.
Cross-compiler install is pretty easy and you should have that for pus
On Tue, Oct 05, 2021 at 01:37:29PM +0200, Christian König wrote:
> Simplifying the code a bit.
>
> Signed-off-by: Christian König
Reviewed-by: Daniel Vetter
> ---
> drivers/gpu/drm/radeon/radeon_sync.c | 22 +++---
> 1 file changed, 3 insertions(+), 19 deletions(-)
>
> diff -
On Tue, Oct 05, 2021 at 02:44:50PM +0200, Christian König wrote:
> Am 05.10.21 um 14:40 schrieb Tvrtko Ursulin:
> >
> > On 05/10/2021 12:37, Christian König wrote:
> > > This makes the function much simpler since the complex
> > > retry logic is now handled else where.
> > >
> > > Signed-off-by:
On Tue, Oct 05, 2021 at 01:37:37PM +0200, Christian König wrote:
> Simplifying the code a bit.
>
> v2: add missing rcu_read_lock()/unlock()
> v3: switch to locked version
>
> Signed-off-by: Christian König
> Reviewed-by: Tvrtko Ursulin
Please make sure you also apply this to the new copy of th
On Wed, 2021-10-13 at 14:43 +0200, Daniel Vetter wrote:
> On Fri, Oct 08, 2021 at 03:35:28PM +0200, Thomas Hellström wrote:
> > The TTM managers and, possibly, the gtt address space managers will
> > need to be able to order fences for async operation.
> > Using dma_fence_is_later() for this will r
On Tue, Oct 05, 2021 at 01:37:38PM +0200, Christian König wrote:
> Makes the handling a bit more complex, but avoids the use of
> dma_resv_get_excl_unlocked().
>
> v2: improve coding and documentation
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/drm_gem_atomic_helper.c | 13 ++
On Tue, Oct 05, 2021 at 01:37:39PM +0200, Christian König wrote:
> Simplifying the code a bit.
>
> Signed-off-by: Christian König
A bit a trick conversion since the previous code was clever with the ret
handling in the loop, but looks correct.
Please mention in the commit message that this code
On Tue, Oct 05, 2021 at 01:37:40PM +0200, Christian König wrote:
> Makes the handling a bit more complex, but avoids the use of
> dma_resv_get_excl_unlocked().
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/nouveau/dispnv50/wndw.c | 10 +-
> 1 file changed, 9 insertions(+), 1
On Tue, Oct 05, 2021 at 01:37:41PM +0200, Christian König wrote:
> Instead of hand rolling the logic.
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/etnaviv/etnaviv_gem.c | 31 ++-
> 1 file changed, 11 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/g
On Tue, Oct 05, 2021 at 01:37:42PM +0200, Christian König wrote:
> We certainly hold the reservation lock here, no need for the RCU dance.
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --g
On Wed, Oct 13, 2021 at 04:21:43PM +0200, Thomas Hellström wrote:
> On Wed, 2021-10-13 at 14:43 +0200, Daniel Vetter wrote:
> > On Fri, Oct 08, 2021 at 03:35:28PM +0200, Thomas Hellström wrote:
> > > The TTM managers and, possibly, the gtt address space managers will
> > > need to be able to order
On 10/13/21 16:33, Daniel Vetter wrote:
On Wed, Oct 13, 2021 at 04:21:43PM +0200, Thomas Hellström wrote:
On Wed, 2021-10-13 at 14:43 +0200, Daniel Vetter wrote:
On Fri, Oct 08, 2021 at 03:35:28PM +0200, Thomas Hellström wrote:
The TTM managers and, possibly, the gtt address space managers w
On Fri, Oct 08, 2021 at 03:35:26PM +0200, Thomas Hellström wrote:
> As we start to introduce asynchronous failsafe object migration,
> where we update the object state and then submit asynchronous
> commands we need to record what memory resources are actually used
> by various part of the command
On 10/13/21 16:41, Daniel Vetter wrote:
On Fri, Oct 08, 2021 at 03:35:26PM +0200, Thomas Hellström wrote:
As we start to introduce asynchronous failsafe object migration,
where we update the object state and then submit asynchronous
commands we need to record what memory resources are actually
== Series Details ==
Series: mmotm 2021-10-05-19-53 uploaded (drivers/gpu/drm/msm/hdmi/hdmi_phy.o)
(rev2)
URL : https://patchwork.freedesktop.org/series/95495/
State : failure
== Summary ==
Applying: mmotm 2021-10-05-19-53 uploaded (drivers/gpu/drm/msm/hdmi/hdmi_phy.o)
error: patch failed: dr
== Series Details ==
Series: drm/i915: Use dma_resv_iter for waiting in
i915_gem_object_wait_reservation. (rev3)
URL : https://patchwork.freedesktop.org/series/95765/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
C
On Thu, Oct 07, 2021 at 01:19:25PM +0530, Nautiyal, Ankit K wrote:
>
> On 10/5/2021 9:01 PM, Imre Deak wrote:
> > On Tue, Oct 05, 2021 at 01:34:21PM +0300, Jani Nikula wrote:
> > > Cc: Imre, I think you were involved in adding the checks.
> > About ADL-S the spec says:
> >
> > Bspec 53597:
> > Co
On Wed, 13 Oct 2021, Imre Deak wrote:
> On Thu, Oct 07, 2021 at 01:19:25PM +0530, Nautiyal, Ankit K wrote:
>>
>> On 10/5/2021 9:01 PM, Imre Deak wrote:
>> > On Tue, Oct 05, 2021 at 01:34:21PM +0300, Jani Nikula wrote:
>> > > Cc: Imre, I think you were involved in adding the checks.
>> > About ADL
On 13/10/2021 15:00, Daniel Vetter wrote:
On Wed, Oct 13, 2021 at 02:32:03PM +0200, Maarten Lankhorst wrote:
No memory should be allocated when calling i915_gem_object_wait,
because it may be called to idle a BO when evicting memory.
Fix this by using dma_resv_iter helpers to call
i915_gem_ob
On Wed, Oct 13, 2021 at 01:47:09PM +0300, Jani Nikula wrote:
On Wed, 13 Oct 2021, Ville Syrjälä wrote:
On Wed, Oct 13, 2021 at 01:11:58PM +0300, Jani Nikula wrote:
Three main ideas here:
- vlv sideband only has the name "sideband" in common with the rest of
intel_sideband.[ch]
I wouldn't
On 13/10/2021 13:01, Daniel Vetter wrote:
On Wed, Oct 06, 2021 at 10:12:29AM -0700, Matthew Brost wrote:
On Mon, Oct 04, 2021 at 03:36:48PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Code added in 71ed60112d5d ("drm/i915: Add kick_backend function to
i915_sched_engine") and ee242ca70
On Wed, Oct 13, 2021 at 01:11:59PM +0300, Jani Nikula wrote:
The VLV/CHV sideband code is pretty distinct from the rest of the
sideband code. Split it out to new vlv_sideband.[ch].
Pure code movement with relevant #include changes, and a tiny checkpatch
fix on top.
Cc: Lucas De Marchi
Cc: Vill
On 13/10/2021 13:06, Daniel Vetter wrote:
On Tue, Oct 05, 2021 at 03:05:25PM +0200, Thomas Hellström wrote:
Hi, Tvrtko,
On 10/5/21 13:31, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
In short this makes i915 work for hybrid setups (DRI_PRIME=1 with Mesa)
when rendering is done on Intel dgfx
On 13/10/2021 01:56, Umesh Nerlige Ramappa wrote:
With GuC handling scheduling, i915 is not aware of the time that a
context is scheduled in and out of the engine. Since i915 pmu relies on
this info to provide engine busyness to the user, GuC shares this info
with i915 for all engines using sha
On 2021-10-12 at 11:28:45 +0300, Stanislav Lisovskiy wrote:
> TileF(Tile4 in bspec) format is 4K tile organized into
> 64B subtiles with same basic shape as for legacy TileY
> which will be supported by Display13.
>
> v2: - Fixed wrong case condition(Jani Nikula)
> - Increased I915_FORMAT_MOD_
On Wed, Oct 13, 2021 at 04:37:03PM +0100, Tvrtko Ursulin wrote:
>
> On 13/10/2021 15:00, Daniel Vetter wrote:
> > On Wed, Oct 13, 2021 at 02:32:03PM +0200, Maarten Lankhorst wrote:
> > > No memory should be allocated when calling i915_gem_object_wait,
> > > because it may be called to idle a BO wh
In current code, the devres group for aggregate master is left open
after call to component_master_add_*(). This leads to problems when the
master does further managed allocations on its own. When any
participating driver calls component_del(), this leads to immediate
release of resources.
This ca
On Wed, Oct 13, 2021 at 05:06:26PM +0100, Tvrtko Ursulin wrote:
On 13/10/2021 01:56, Umesh Nerlige Ramappa wrote:
With GuC handling scheduling, i915 is not aware of the time that a
context is scheduled in and out of the engine. Since i915 pmu relies on
this info to provide engine busyness to th
Op 13-10-2021 om 17:37 schreef Tvrtko Ursulin:
>
> On 13/10/2021 15:00, Daniel Vetter wrote:
>> On Wed, Oct 13, 2021 at 02:32:03PM +0200, Maarten Lankhorst wrote:
>>> No memory should be allocated when calling i915_gem_object_wait,
>>> because it may be called to idle a BO when evicting memory.
>>>
== Series Details ==
Series: component: do not leave master devres group open after bind (rev3)
URL : https://patchwork.freedesktop.org/series/94889/
State : failure
== Summary ==
Applying: component: do not leave master devres group open after bind
Using index info to reconstruct a base tree.
On 2021-10-13 14:57:34 [+0200], Daniel Vetter wrote:
> Hm there's a pile of commits there, and nothing immediately jumps to
> light. The thing is, 18 is likely way too much, since if e.g. we have a
> single new property on a plane and that pushes over the limit on all of
> them, you get iirc 3x4 al
Add drm buddy allocator support for vram memory management
Signed-off-by: Arunpravin
---
.../gpu/drm/amd/amdgpu/amdgpu_res_cursor.h| 97 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 4 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 251 ++
3 files changed, 2
Port Intel buddy manager to drm root folder
Implemented range allocation support for the provided order
Implemented TOP-DOWN support
Implemented freeing up unused pages on contiguous allocation
Moved range allocation and freelist pickup into a single function
Signed-off-by: Arunpravin
---
driver
Move vram related defines and inline functions into
a separate header file
Signed-off-by: Arunpravin
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h | 72
1 file changed, 72 insertions(+)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h
diff --git a/drivers
On Tue, Oct 12, 2021 at 03:08:05PM -0700, John Harrison wrote:
> On 10/4/2021 15:06, Matthew Brost wrote:
> > If an object in the excl or shared slot is a composite fence from a
> > parallel submit and the current request in the conflict tracking is from
> > the same parallel context there is no ne
On Fri, Oct 08, 2021 at 09:40:43AM -0700, John Harrison wrote:
> On 10/7/2021 18:21, Matthew Brost wrote:
> > On Thu, Oct 07, 2021 at 03:03:04PM -0700, John Harrison wrote:
> > > On 10/4/2021 15:06, Matthew Brost wrote:
> > > > Assign contexts in parent-child relationship consecutive guc_ids. This
From: Mark Yacoub
[Why]
1. drm_atomic_helper_check doesn't check for the LUT sizes of either Gamma
or Degamma props in the new CRTC state, allowing any invalid size to
be passed on.
2. Each driver has its own LUT size, which could also be different for
legacy users.
[How]
1. Create |degamma_lut_
From: Mark Yacoub
[Why]
drm_atomic_helper_check_crtc now verifies both legacy and non-legacy LUT
sizes. There is no need to check it within amdgpu_dm_atomic_check.
[How]
Remove the local call to verify LUT sizes and use DRM Core function
instead.
Tested on ChromeOS Zork.
v1:
Remove amdgpu_dm_v
On Fri, Oct 08, 2021 at 10:20:24AM -0700, John Harrison wrote:
> On 10/4/2021 15:06, Matthew Brost wrote:
> > Implement multi-lrc submission via a single workqueue entry and single
> > H2G. The workqueue entry contains an updated tail value for each
> > request, of all the contexts in the multi-lrc
Looks good to me.
Reviewed-by: Caz Yokoyama
-caz
On Tue, 2021-10-12 at 15:12 -0700, Matt Roper wrote:
> The I915_TILING_* values in our uapi header are intended solely for
> use
> with the old get_tiling/set_tiling ioctls that operate on hardware
> de-tiling fences; all other uapi communication a
== Series Details ==
Series: series starting with [v2,1/4] dri: do not check for NULL debugfs dentry
URL : https://patchwork.freedesktop.org/series/95794/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
bb1c720488a1 dri: do not check for NULL debugfs dentry
-:93: CHECK:LINE_SPACI
== Series Details ==
Series: series starting with [v2,1/4] dri: do not check for NULL debugfs dentry
URL : https://patchwork.freedesktop.org/series/95794/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separa
On 10/13/2021 11:03, Matthew Brost wrote:
On Fri, Oct 08, 2021 at 09:40:43AM -0700, John Harrison wrote:
On 10/7/2021 18:21, Matthew Brost wrote:
On Thu, Oct 07, 2021 at 03:03:04PM -0700, John Harrison wrote:
On 10/4/2021 15:06, Matthew Brost wrote:
Assign contexts in parent-child relationshi
On Wed, 2021-10-13 at 12:32 +0300, Ville Syrjälä wrote:
> On Tue, Oct 12, 2021 at 06:00:46PM -0700, José Roberto de Souza wrote:
> > This memory frequency calculated is only used to check if it is zero,
> > what is not useful as it will never actually be zero.
> >
> > Also the calculation is wrong
On 10/12/2021 17:15, Matthew Brost wrote:
On Tue, Oct 12, 2021 at 03:15:00PM -0700, John Harrison wrote:
On 10/4/2021 15:21, Patchwork wrote:
== Series Details ==
Series: Parallel submission aka multi-bb execbuf (rev4)
URL : https://patchwork.freedesktop.org/series/92789/
State : warning
==
On 10/13/2021 10:51, Matthew Brost wrote:
On Tue, Oct 12, 2021 at 03:08:05PM -0700, John Harrison wrote:
On 10/4/2021 15:06, Matthew Brost wrote:
If an object in the excl or shared slot is a composite fence from a
parallel submit and the current request in the conflict tracking is from
the same
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