On 09/10/2021 00:33, Matt Roper wrote:
From: Tvrtko Ursulin
Check how many extra GT tiles are available on the system and setup
register access for all of them. We can detect how may GT tiles are
available by reading a register on the root tile. The same register
returns the tile ID on all ti
== Series Details ==
Series: dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after
conversion (rev4)
URL : https://patchwork.freedesktop.org/series/95605/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2ef0df1434bf dma-resv: Fix dma_resv_get_fences and dma_resv_copy_
== Series Details ==
Series: dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after
conversion (rev4)
URL : https://patchwork.freedesktop.org/series/95605/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10712 -> Patchwork_21303
===
On 07/10/2021 23:55, Umesh Nerlige Ramappa wrote:
With GuC handling scheduling, i915 is not aware of the time that a
context is scheduled in and out of the engine. Since i915 pmu relies on
this info to provide engine busyness to the user, GuC shares this info
with i915 for all engines using sha
== Series Details ==
Series: dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after
conversion (rev4)
URL : https://patchwork.freedesktop.org/series/95605/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10712_full -> Patchwork_21303_full
=
On 08/10/2021 13:19, Christian König wrote:
Am 08.10.21 um 12:49 schrieb Tvrtko Ursulin:
On 08/10/2021 11:21, Christian König wrote:
Am 08.10.21 um 11:50 schrieb Tvrtko Ursulin:
From: Tvrtko Ursulin
Cache the count of shared fences in the iterator to avoid dereferencing
the dma_resv_objec
Hi,
On Sun, Oct 03, 2021 at 12:42:58PM +0200, Len Baker wrote:
> As noted in the "Deprecated Interfaces, Language Features, Attributes,
> and Conventions" documentation [1], size calculations (especially
> multiplication) should not be performed in memory allocator (or similar)
> function argument
Am 11.10.21 um 14:32 schrieb Tvrtko Ursulin:
On 08/10/2021 13:19, Christian König wrote:
Am 08.10.21 um 12:49 schrieb Tvrtko Ursulin:
On 08/10/2021 11:21, Christian König wrote:
Am 08.10.21 um 11:50 schrieb Tvrtko Ursulin:
From: Tvrtko Ursulin
Cache the count of shared fences in the itera
The comment here is no longer accurate, since the current shrinker code
requires a full ref before touching any objects. Also unset_pages()
should already do the required make_unshrinkable() for us, if needed,
which is also nicely balanced with set_pages().
Signed-off-by: Matthew Auld
Cc: Thomas
We already do this when mapping the pages.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 1 -
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 1 -
2 files changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt
From: Thomas Hellström
Break out some shmem backend utils for future reuse by the TTM backend:
shmem_alloc_st(), shmem_free_st() and __shmem_writeback() which we can
use to provide a shmem-backed TTM page pool for cached-only TTM
buffer objects.
Main functional change here is that we now compute
Attempt to document shrink_pin and the other relevant interfaces that
interact with it, before we start messing with it.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Reviewed-by: Thomas Hellström
---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 24 +-
drivers/gpu/drm/i915/ge
For cached objects we can allocate our pages directly in shmem. This
should make it possible(in a later patch) to utilise the existing
i915-gem shrinker code for such objects. For now this is still disabled.
v2(Thomas):
- Add optional try_to_writeback hook for objects. Importantly we need
to
We currently just evict lmem objects to system memory when under memory
pressure. For this case we might lack the usual object mm.pages, which
effectively hides the pages from the i915-gem shrinker, until we
actually "attach" the TT to the object, or in the case of lmem-only
objects it just gets mi
This should let us do an accelerated copy directly to the shmem pages
when temporarily moving lmem-only objects, where the i915-gem shrinker
can later kick in to swap out the pages, if needed.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i9
Turn on the shmem tt backend, and enable shrinking.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/driver
Replace DRM_ERROR with i915_probe_error to report early HuC failures.
Signed-off-by: Thanneeru Srinivasulu
---
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel
Injecting probe errors -ENXIO for MMIO send.
Signed-off-by: Thanneeru Srinivasulu
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 8f8182bf7c11..490d66712afc 1
Inject probe errors -ENXIO, -EBUSY for CT send.
Signed-off-by: Thanneeru Srinivasulu
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 83764db0fd6d
Replace DRM_ERROR with CT_PROBE_ERROR to report early CTB failures.
Signed-off-by: Thanneeru Srinivasulu
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
b/drivers/gpu/drm/i915/gt/uc/i
Injecting probe errors for MMIO send, CT send to make
probe flow more robust.
Use i915_probe_error to report probe injection errors.
Thanneeru Srinivasulu (4):
drm/i915/huc: Use i915_probe_error to report early CTB failures
drm/i915/huc: Use i915_probe_error to report early HuC failures
drm
== Series Details ==
Series: series starting with [v8,1/8] drm/i915/gem: Break out some shmem
backend utils
URL : https://patchwork.freedesktop.org/series/95677/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
099555c40683 drm/i915/gem: Break out some shmem backend utils
671a8c8
== Series Details ==
Series: series starting with [v8,1/8] drm/i915/gem: Break out some shmem
backend utils
URL : https://patchwork.freedesktop.org/series/95677/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checke
From: Stuart Summers
Add a new platform flag, has_64k_pages, for platforms supporting
base page sizes of 64k.
Signed-off-by: Stuart Summers
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 2 ++
drivers/gpu/drm/i915/in
This series introduces the enabling patches for new flat ccs feature and
64k page support for i915 local memory, along with documentation on the
uAPI impact.
64k page support
On discrete platforms, starting from DG2, we have to contend with GTT
page size restrictions when dealing
From: Matthew Auld
LMEM should be allocated at 64K granularity, since 4K page support will
eventually be dropped for LMEM when using the PPGTT.
Signed-off-by: Matthew Auld
Signed-off-by: Stuart Summers
Signed-off-by: Ramalingam C
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i91
From: Matthew Auld
For local-memory objects we need to align the GTT addresses to 64K, both
for the ppgtt and ggtt.
Signed-off-by: Matthew Auld
Signed-off-by: Stuart Summers
Signed-off-by: Ramalingam C
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_vma.c | 9 +++--
From: Matthew Auld
If the device needs 64K minimum GTT pages for device local-memory,
like on XEHPSDV, then we need to fail the allocation if we can't
meet it, instead of falling back to 4K pages, otherwise we can't
safely support the insertion of device local-memory pages for
this vm, since the
From: Matthew Auld
On some platforms the hw has dropped support for 4K GTT pages when
dealing with LMEM, and due to the design of 64K GTT pages in the hw, we
can only mark the *entire* page-table as operating in 64K GTT mode,
since the enable bit is still on the pde, and not the pte. And since we
From: Matthew Auld
XEHPSDV optimises 64K GTT pages for local-memory, since everything
should be allocated at 64K granularity. We say goodbye to sparse
entries, and instead get a compact 256B page-table for 64K pages,
which should be more cache friendly. 4K pages for local-memory
are no longer sup
From: Bommu Krishnaiah
Replace the hard coded 4K alignment value with vm->min_alignment.
Cc: Wilson Chris P
Signed-off-by: Bommu Krishnaiah
Signed-off-by: Ramalingam C
---
.../i915/gem/selftests/i915_gem_client_blt.c | 23 ---
drivers/gpu/drm/i915/gt/intel_gtt.c |
From: Matthew Auld
We need to support vm->min_alignment > 4K, depending
on the vm itself and the type of object we are inserting.
With this in mind update the GTT selftests to take this
into account.
Signed-off-by: Matthew Auld
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/selftests/i9
From: Matthew Auld
The basic idea is that each 2M block(page-table) has a color, depending
on if the page-table is occupied by LMEM objects(64K) or SMEM
objects(4K), where our goal is to prevent mixing 64K and 4K GTT pages in
the page-table, which is not supported by the HW.
Signed-off-by: Matth
From: CQ Tang
Gen12+ devices support 3D surface (buffer) compression and various
compression formats. This is accomplished by an additional compression
control state (CCS) stored for each surface.
Gen 12 devices(TGL family and DG1) stores compression states in a separate
region of memory. It is
From: Abdiel Janulgue
A portion of device memory is reserved for Flat CCS so usable
device memory will be reduced by size of Flat CCS. Size of
Flat CCS is specified in “XEHPSDV_FLAT_CCS_BASE_ADDR”.
So to get effective device memory we need to subtract
total device memory by Flat CCS memory size.
From: Matthew Auld
On discrete platforms like DG2, we need to support a minimum page size
of 64K when dealing with device local-memory. This is quite tricky for
various reasons, so try to document the new implicit uapi for this.
Signed-off-by: Matthew Auld
Signed-off-by: Ramalingam C
---
incl
From: Ayaz A Siddiqui
Gen12.5+ devices support Flat CCS which reserved a portion of the device
memory to store compression metadata, during the clearing of device memory
buffer object we also need to clear the associated CCS buffer.
Flat CCS memory can not be directly accessed by S/W.
Address of
Details of the new features getting added as part of DG2 enabling and their
implicit impact on the uAPI.
Signed-off-by: Ramalingam C
cc: Daniel Vetter
cc: Matthew Auld
---
Documentation/gpu/rfc/i915_dg2.rst | 47 ++
Documentation/gpu/rfc/index.rst| 3 ++
2 file
== Series Details ==
Series: series starting with [v8,1/8] drm/i915/gem: Break out some shmem
backend utils
URL : https://patchwork.freedesktop.org/series/95677/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10716 -> Patchwork_21304
===
== Series Details ==
Series: drm/i915/guc: Inject probe errors for MMIO send, CT send
URL : https://patchwork.freedesktop.org/series/95683/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10716 -> Patchwork_21305
Summary
On 10/7/21 13:01, Marco Elver wrote:
> On Thu, Oct 07, 2021 at 11:58AM +0200, Vlastimil Babka wrote:
> [...]
>> - Add a CONFIG_STACKDEPOT_ALWAYS_INIT flag to keep using the current
>> well-defined point of allocation as part of mem_init(). Make CONFIG_KASAN
>> select this flag.
>> - Other user
> -Original Message-
> From: C, Ramalingam
> Sent: Monday, October 11, 2021 9:12 AM
> To: dri-devel ; intel-gfx g...@lists.freedesktop.org>
> Cc: Daniel Vetter ; Auld, Matthew
> ; Tang, CQ ; Hellstrom,
> Thomas ; C, Ramalingam
> ; Daniel Vetter
> Subject: [PATCH 14/14] Doc/gpu/rfc/i91
perf_parallel_engines is micro benchmark to test i915 request
scheduling. The test creates a thread per physical engine and submits
NOP requests and waits the requests to complete in a loop. In execlists
mode this works perfectly fine as powerful CPU has enough cores to feed
each engine and process
== Series Details ==
Series: drm/i915/dg2: Enabling 64k page size and flat ccs
URL : https://patchwork.freedesktop.org/series/95686/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5bf9ba0e1d7d drm/i915: Add has_64k_pages flag
70d612d1a872 drm/i915/xehpsdv: set min page-size to 6
On Mon, Oct 11, 2021 at 08:51:06PM +0530, Thanneeru Srinivasulu wrote:
> Inject probe errors -ENXIO, -EBUSY for CT send.
>
> Signed-off-by: Thanneeru Srinivasulu
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i9
== Series Details ==
Series: drm/i915/dg2: Enabling 64k page size and flat ccs
URL : https://patchwork.freedesktop.org/series/95686/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/d
On Mon, Oct 11, 2021 at 08:51:05PM +0530, Thanneeru Srinivasulu wrote:
> Injecting probe errors -ENXIO for MMIO send.
>
> Signed-off-by: Thanneeru Srinivasulu
Reviewed-by: Matthew Brost
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git
On Mon, Oct 11, 2021 at 08:51:03PM +0530, Thanneeru Srinivasulu wrote:
> Replace DRM_ERROR with CT_PROBE_ERROR to report early CTB failures.
>
> Signed-off-by: Thanneeru Srinivasulu
Reviewed-by: Matthew Brost
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 4 ++--
> 1 file changed, 2 inse
On Mon, Oct 11, 2021 at 08:51:04PM +0530, Thanneeru Srinivasulu wrote:
> Replace DRM_ERROR with i915_probe_error to report early HuC failures.
>
> Signed-off-by: Thanneeru Srinivasulu
Reviewed-by: Matthew Brost
> ---
> drivers/gpu/drm/i915/gt/uc/intel_huc.c | 4 ++--
> 1 file changed, 2 inser
The 128b/132b channel coding link training uses more straightforward TX
FFE preset values. Reuse voltage tries and max vswing for retry logic.
The delays for 128b/132b are still all wrong, but this is regardless a
step forward.
v2: Fix UHBR rate checks, use intel_dp_is_uhbr() helper
v3:
- Rebase
Add per-lane abstraction for max vswing reached to make follow-up
cleaner, as this one reverses the conditions.
v2: both conditions need to be true, reverse (Ville)
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
.../drm/i915/display/intel_dp_link_training.c | 42 +++
1 file c
== Series Details ==
Series: drm/i915/dg2: Enabling 64k page size and flat ccs
URL : https://patchwork.freedesktop.org/series/95686/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10717 -> Patchwork_21306
Summary
---
ok - CI on this failed like, multiple times last week - each time with
something slightly different and pretty clearly not related, so I'm going to
give this one last shot at retesting now that some time has passed - otherwise
I'll just file some bugs.
On Sat, 2021-10-09 at 01:58 +, Patchwork
== Series Details ==
Series: drm/i915/selftests: Increase timeout in requests perf selftest
URL : https://patchwork.freedesktop.org/series/95688/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10717 -> Patchwork_21307
Summar
== Series Details ==
Series: series starting with [1/2] drm/i915/dp: abstract
intel_dp_lane_max_vswing_reached()
URL : https://patchwork.freedesktop.org/series/95689/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
89b690d2e4c1 drm/i915/dp: abstract intel_dp_lane_max_vswing_reac
== Series Details ==
Series: series starting with [1/2] drm/i915/dp: abstract
intel_dp_lane_max_vswing_reached()
URL : https://patchwork.freedesktop.org/series/95689/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10717 -> Patchwork_21308
==
The hangcheck selftest blows on DG1 CI and aborts the BAT run.
Investigation is underway to root cause the failure but in the meantime
disable to this test on DG1 to unblock CI.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 8
1 file changed, 8 insertio
== Series Details ==
Series: series starting with [v8,1/8] drm/i915/gem: Break out some shmem
backend utils
URL : https://patchwork.freedesktop.org/series/95677/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10716_full -> Patchwork_21304_full
=
== Series Details ==
Series: Fixup header includes (rev3)
URL : https://patchwork.freedesktop.org/series/95587/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_engi
On Mon, Oct 11, 2021 at 12:41:19PM +0100, Tvrtko Ursulin wrote:
On 07/10/2021 23:55, Umesh Nerlige Ramappa wrote:
With GuC handling scheduling, i915 is not aware of the time that a
context is scheduled in and out of the engine. Since i915 pmu relies on
this info to provide engine busyness to th
== Series Details ==
Series: Fixup header includes (rev3)
URL : https://patchwork.freedesktop.org/series/95587/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10717 -> Patchwork_21309
Summary
---
**SUCCESS**
No reg
On Mon, Oct 11, 2021 at 09:06:07PM +0200, Nirmoy Das wrote:
> Debugfs APIs returns encoded error on failure so use
> debugfs_lookup() instead of checking for NULL.
[...]
> --- a/drivers/gpu/vga/vga_switcheroo.c
> +++ b/drivers/gpu/vga/vga_switcheroo.c
> @@ -914,7 +914,7 @@ static void vga_switchero
== Series Details ==
Series: drm/i915/guc: Inject probe errors for MMIO send, CT send
URL : https://patchwork.freedesktop.org/series/95683/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10716_full -> Patchwork_21305_full
Su
On Thu, 2021-10-07 at 12:31 +0300, Gwan-gyeong Mun wrote:
>
> On 10/6/21 11:04 PM, Souza, Jose wrote:
> > On Wed, 2021-10-06 at 11:50 +0300, Gwan-gyeong Mun wrote:
> > >
> > > On 10/6/21 2:18 AM, José Roberto de Souza wrote:
> > > > Alderlake-P was getting 'max time under evasion' messages when P
== Series Details ==
Series: drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers
(rev9)
URL : https://patchwork.freedesktop.org/series/95127/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked
== Series Details ==
Series: drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers
(rev9)
URL : https://patchwork.freedesktop.org/series/95127/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10719 -> Patchwork_21310
=
== Series Details ==
Series: series starting with [1/4] dri: do not check for NULL debugfs dentry
URL : https://patchwork.freedesktop.org/series/95691/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separatel
On 10/4/2021 15:06, Matthew Brost wrote:
Introduce 'set parallel submit' extension to connect UAPI to GuC
multi-lrc interface. Kernel doc in new uAPI should explain it all.
IGT: https://patchwork.freedesktop.org/patch/447008/?series=93071&rev=1
media UMD: https://github.com/intel/media-driver/pu
On 10/4/2021 3:06 PM, Matthew Brost wrote:
Parallel submission create composite fences (dma_fence_array) for excl /
shared slots in objects. The I915_GEM_BUSY IOCTL checks these slots to
determine the busyness of the object. Prior to patch it only check if
the fence in the slot was a i915_reque
== Series Details ==
Series: series starting with [1/4] dri: do not check for NULL debugfs dentry
URL : https://patchwork.freedesktop.org/series/95691/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10719 -> Patchwork_21311
== Series Details ==
Series: series starting with [1/2] drm/i915/dp: abstract
intel_dp_lane_max_vswing_reached()
URL : https://patchwork.freedesktop.org/series/95689/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10717_full -> Patchwork_21308_full
On Mon, Oct 11, 2021 at 03:09:43PM -0700, John Harrison wrote:
> On 10/4/2021 15:06, Matthew Brost wrote:
> > Introduce 'set parallel submit' extension to connect UAPI to GuC
> > multi-lrc interface. Kernel doc in new uAPI should explain it all.
> >
> > IGT: https://patchwork.freedesktop.org/patch
Debugfs APIs returns encoded error on failure so use
debugfs_lookup() instead of checking for NULL.
CC: Lukas Wunner
CC: David Airlie
CC: Daniel Vetter
CC: Maarten Lankhorst
CC: Maxime Ripard
CC: Thomas Zimmermann
Signed-off-by: Nirmoy Das
---
drivers/gpu/vga/vga_switcheroo.c | 2 +-
1 fi
Do not check for NULL value as drm.primary->debugfs_root
will either contain a valid pointer or an encoded error
instead of NULL.
CC: Jani Nikula
CC: Joonas Lahtinen
CC: Rodrigo Vivi
CC: David Airlie
CC: Daniel Vetter
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/debugfs_gt.c | 3 -
Debugfs APIs returns encoded error on failure instead of NULL
and for drm primary/minor debugfs directories, we save the
returned value in the dentry pointer and pass it on to drm
drivers to further create debugfs files/directories. Error
conditions are handled by debugfs APIs, so no need to check
For debugfs directory, it is recommended to save the result
and pass over to next debugfs API for creating debugfs
files/directories. Error conditions are handled by debugfs APIs.
CC: Christian Koenig
CC: Huang Rui
CC: David Airlie
CC: Daniel Vetter
Signed-off-by: Nirmoy Das
---
drivers/gpu
== Series Details ==
Series: drm/i915/selftests: Skip hangcheck selftest on DG1
URL : https://patchwork.freedesktop.org/series/95693/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10719 -> Patchwork_21312
Summary
---
On 10/4/2021 15:06, Matthew Brost wrote:
For some users of multi-lrc, e.g. split frame, it isn't safe to preempt
mid BB. To safely enable preemption at the BB boundary, a handshake
between to parent and child is needed. This is implemented via custom
between to parent -> between parent
emit_bb_
== Series Details ==
Series: Fixup header includes (rev3)
URL : https://patchwork.freedesktop.org/series/95587/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10717_full -> Patchwork_21309_full
Summary
---
**FAILURE**
The hangcheck selftest blocks per engine resets by setting magic bits in
the reset flags. This is incorrect for GuC submission because if the GuC
fails to reset an engine we would like to do a full GT reset. Do no set
these magic bits when using GuC submission.
Side note this lockless algorithm wi
== Series Details ==
Series: drm/i915/selftests: Allow engine reset failure to do a GT reset in
hangcheck selftest
URL : https://patchwork.freedesktop.org/series/95702/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10719 -> Patchwork_21313
'inst' [-Werror=unused-variable]
491 | u32 inst, aper;
| ^~~~
cc1: all warnings being treated as errors
Caused by commit
404046cf4805 ("drm/nouveau/mmu/gp100-: drop unneeded assignment in the if
condition.")
I have used the drm-misc tree from next-20211011 for t
== Series Details ==
Series: drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers
(rev9)
URL : https://patchwork.freedesktop.org/series/95127/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10719_full -> Patchwork_21310_full
===
== Series Details ==
Series: drm/i915/selftests: Skip hangcheck selftest on DG1
URL : https://patchwork.freedesktop.org/series/95693/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10719_full -> Patchwork_21312_full
Summary
On Thu, 7 Oct 2021 at 21:09, Ville Syrjälä
wrote:
>
> On Thu, Oct 07, 2021 at 01:52:42PM +0300, Jani Nikula wrote:
> > On Thu, 07 Oct 2021, Dave Airlie wrote:
> > > This is another series in the refactor intel_display.c into more
> > > manageable
> > > places.
> > >
> > > This moves the initial
This is another series in the refactor intel_display.c into more manageable
places.
This moves the initial plane config and all the fb pin/unpin code out.
It also refactors both a little to make the interfaces cleaner.
v2: just address the minor comments from Jani.
Jani, I think Ville doesn't m
From: Dave Airlie
Start to refactor more stuff out of intel_display.c. These fit
better in this file.
This moves the rps boosting code as well as this is the only user of it.
Signed-off-by: Dave Airlie
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 208 ++
drivers/gpu/drm
From: Dave Airlie
This just pulls this out into a function so it can be moved to
another file easier.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 44 +++-
1 file changed, 25 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/disp
From: Dave Airlie
I want to refactor some stuff using this so make it shared.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i9
From: Dave Airlie
This moves this functionality out of intel_display.c to separate
self-contained file.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 279 +
drivers/gpu/drm/i915/display/inte
From: Dave Airlie
This just moves this code out of the i915_display.c into a new
standalone file.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/Makefile | 1 +
.../gpu/drm/i915/display/intel_atomic_plane.c | 1 +
drivers/gpu/drm/i915/display/intel_cursor.c | 2 +-
From: Dave Airlie
This just cleans up the calls a bit.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_fbdev.c | 64 +-
1 file changed, 38 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c
b/drivers/gpu/drm/i915/displ
From: Dave Airlie
This moves the fbdev pin code over and moves the internal
interfaces to static.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_fb_pin.c | 34 +++--
drivers/gpu/drm/i915/display/intel_fb_pin.h | 15 -
drivers/gpu/drm/i915/display/inte
From: Dave Airlie
The uses_fence isn't used.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_fb_pin.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c
b/drivers/gpu/drm/i915/display/intel_fb_pin.c
index 7233a2d
== Series Details ==
Series: drm/i915/selftests: Allow engine reset failure to do a GT reset in
hangcheck selftest
URL : https://patchwork.freedesktop.org/series/95702/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10719_full -> Patchwork_21313_full
==
== Series Details ==
Series: drm/i915/display: refactor plane config + pin out (rev2)
URL : https://patchwork.freedesktop.org/series/95541/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
569a494f9314 drm/i915/display: move plane prepare/cleanup to
intel_atomic_plane.c
-:38: WAR
== Series Details ==
Series: drm/i915/display: refactor plane config + pin out (rev2)
URL : https://patchwork.freedesktop.org/series/95541/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+driver
== Series Details ==
Series: drm/i915/display: refactor plane config + pin out (rev2)
URL : https://patchwork.freedesktop.org/series/95541/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10720 -> Patchwork_21314
Summary
On Mon, Oct 11, 2021 at 9:10 AM Ramalingam C wrote:
>
> Details of the new features getting added as part of DG2 enabling and their
> implicit impact on the uAPI.
>
> Signed-off-by: Ramalingam C
> cc: Daniel Vetter
> cc: Matthew Auld
> ---
> Documentation/gpu/rfc/i915_dg2.rst | 47
The formulae has been updated to include more variables. Make
sure the code carries the same.
Bspec: 64631
v2: Make GEN11 follow the default route and fix calculation of
maxdebw(RK)
v3: Fix div by zero on default case
Correct indent for fallthrough(Jani)
v4: Fix div by zero on gen11.
v5:
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