[Intel-gfx] [RFC PATCH 00/25] refactor display struct

This is a reworked version of the complete series into a _display pointed to by display for now. There is a fair few places the abstraction leaks around container_of, these need to be resolved to move the code into cleaner separation. I might also have been over-zealous moving stuff, or not zealo

[Intel-gfx] [PATCH 01/25] drm/i915: move display funcs into a display struct. (v3)

From: Dave Airlie This is the first step in an idea to refactor the display code into a bit more of a corner. v2: move display to being a pointer. v3: add missing pointer setup line Signed-off-by: Dave Airlie --- drivers/gpu/drm/i915/display/intel_audio.c| 24 +-- drivers/gpu/drm/i915/di

[Intel-gfx] [PATCH 04/25] drm/i915/display: move gmbus into display struct

From: Dave Airlie Signed-off-by: Dave Airlie --- drivers/gpu/drm/i915/display/intel_cdclk.c | 6 +-- drivers/gpu/drm/i915/display/intel_dp_aux.c | 2 +- drivers/gpu/drm/i915/display/intel_gmbus.c | 42 ++--- drivers/gpu/drm/i915/i915_drv.h | 27 +++-- dri

[Intel-gfx] [PATCH 03/25] drm/i915: move more pll/clocks into display struct.

From: Dave Airlie Signed-off-by: Dave Airlie --- drivers/gpu/drm/i915/display/intel_cdclk.c | 24 ++-- drivers/gpu/drm/i915/display/intel_crt.c | 2 +- drivers/gpu/drm/i915/display/intel_display.c | 14 ++-- drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--

[Intel-gfx] [PATCH 05/25] drm/i915/display: move intel_dmc into display struct

From: Dave Airlie Signed-off-by: Dave Airlie --- .../drm/i915/display/intel_display_debugfs.c | 2 +- .../drm/i915/display/intel_display_power.c| 38 +++ drivers/gpu/drm/i915/display/intel_dmc.c | 46 +-- drivers/gpu/drm/i915/display/intel_psr.c | 2

[Intel-gfx] [PATCH 06/25] drm/i915/display: move mipi_mmio_base to display struct

From: Dave Airlie Signed-off-by: Dave Airlie --- drivers/gpu/drm/i915/display/vlv_dsi.c | 4 +- drivers/gpu/drm/i915/i915_drv.h| 6 +- drivers/gpu/drm/i915/i915_reg.h| 188 - 3 files changed, 99 insertions(+), 99 deletions(-) diff --git a/drivers/gpu

[Intel-gfx] [PATCH 07/25] drm/i915/display: move pps_mmio_base to display struct

From: Dave Airlie Signed-off-by: Dave Airlie --- drivers/gpu/drm/i915/display/intel_pps.c | 6 +++--- drivers/gpu/drm/i915/i915_drv.h | 4 ++-- drivers/gpu/drm/i915/i915_reg.h | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i

[Intel-gfx] [PATCH 09/25] drm/i915/display: move drrs into display struct

From: Dave Airlie Signed-off-by: Dave Airlie --- .../drm/i915/display/intel_display_debugfs.c | 2 +- drivers/gpu/drm/i915/display/intel_drrs.c | 32 +-- drivers/gpu/drm/i915/display/intel_psr.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 2 +- 4 files c

[Intel-gfx] [PATCH 10/25] drm/i915/display: move fbc into display struct

From: Dave Airlie Signed-off-by: Dave Airlie --- drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +- .../drm/i915/display/intel_display_debugfs.c | 10 +- drivers/gpu/drm/i915/display/intel_fbc.c | 98 +-- .../drm/i915/display/skl_universal_plane.c| 2 +- drivers/g

[Intel-gfx] [PATCH 02/25] drm/i915/display: move cdclk info into display

From: Dave Airlie Signed-off-by: Dave Airlie --- drivers/gpu/drm/i915/display/intel_audio.c| 4 +- .../gpu/drm/i915/display/intel_backlight.c| 4 +- drivers/gpu/drm/i915/display/intel_cdclk.c| 196 +- drivers/gpu/drm/i915/display/intel_cdclk.h| 4 +- driver

[Intel-gfx] [PATCH 11/25] drm/i915/display: move pipe/plane mappings to display struct

From: Dave Airlie Signed-off-by: Dave Airlie --- drivers/gpu/drm/i915/display/intel_crtc.c | 12 ++-- drivers/gpu/drm/i915/display/intel_display_types.h | 8 drivers/gpu/drm/i915/i915_drv.h| 6 +++--- 3 files changed, 13 insertions(+), 13 deletion

[Intel-gfx] [PATCH 08/25] drm/i915/drrs: just use some local vars to simplify drrs code

From: Dave Airlie this makes it easier to move this struct later. Signed-off-by: Dave Airlie --- drivers/gpu/drm/i915/display/intel_drrs.c | 90 --- 1 file changed, 49 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/

[Intel-gfx] [PATCH 12/25] drm/i915/display: move properties into display struct

From: Dave Airlie Signed-off-by: Dave Airlie --- drivers/gpu/drm/i915/display/intel_atomic.c| 8 drivers/gpu/drm/i915/display/intel_connector.c | 8 drivers/gpu/drm/i915/i915_drv.h| 6 +++--- 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/

[Intel-gfx] [PATCH 14/25] drm/i915/display: move HDCP related items into display struct

From: Dave Airlie Signed-off-by: Dave Airlie --- drivers/gpu/drm/i915/display/intel_hdcp.c | 134 +++--- drivers/gpu/drm/i915/i915_drv.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 12 +- 3 files changed, 74 insertions(+), 74 deletions(-) diff --git a/drive

[Intel-gfx] [PATCH 17/25] drm/i915/display: move fbdev info to display struct

From: Dave Airlie Signed-off-by: Dave Airlie --- .../drm/i915/display/intel_display_debugfs.c | 4 +-- drivers/gpu/drm/i915/display/intel_fbdev.c| 26 +-- drivers/gpu/drm/i915/i915_drv.h | 8 +++--- 3 files changed, 19 insertions(+), 19 deletions(-) diff --

[Intel-gfx] [PATCH 15/25] drm/i915/display: move hotplug struct to display struct

From: Dave Airlie I've left some _display around the workqueue stuff, since that will need reworking maybe if we split display out, so best to fail early. Signed-off-by: Dave Airlie --- drivers/gpu/drm/i915/display/g4x_dp.c | 4 +- drivers/gpu/drm/i915/display/intel_ddi.c | 6

[Intel-gfx] [PATCH 18/25] drm/i915/display: move fb_tracking to display struct

From: Dave Airlie the spinlock init in gem code seems wildly out of place Signed-off-by: Dave Airlie --- .../drm/i915/display/intel_display_debugfs.c | 4 +- .../gpu/drm/i915/display/intel_frontbuffer.c | 54 +-- drivers/gpu/drm/i915/i915_drv.h | 4 +- drivers/

[Intel-gfx] [PATCH 13/25] drm/i915/display: move audio related members into display struct

From: Dave Airlie Signed-off-by: Dave Airlie --- drivers/gpu/drm/i915/display/intel_audio.c| 72 +-- .../gpu/drm/i915/display/intel_lpe_audio.c| 42 +-- drivers/gpu/drm/i915/i915_drv.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 38

[Intel-gfx] [PATCH 16/25] drm/i915/display: move overlay into display struct

From: Dave Airlie Signed-off-by: Dave Airlie --- drivers/gpu/drm/i915/display/intel_overlay.c | 12 ++-- drivers/gpu/drm/i915/i915_drv.h | 6 +++--- drivers/gpu/drm/i915/i915_getparam.c | 2 +- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drive

[Intel-gfx] [PATCH 20/25] drm/intel/display: move atomic related things to display

From: Dave Airlie Signed-off-by: Dave Airlie --- drivers/gpu/drm/i915/display/intel_display.c | 28 ++-- drivers/gpu/drm/i915/i915_drv.h | 16 +-- 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c

[Intel-gfx] [PATCH 22/25] drm/i915/display: move dpll struct into display

From: Dave Airlie Signed-off-by: Dave Airlie --- drivers/gpu/drm/i915/display/icl_dsi.c| 12 +- drivers/gpu/drm/i915/display/intel_ddi.c | 24 ++-- drivers/gpu/drm/i915/display/intel_display.c | 10 +- .../drm/i915/display/intel_display_debugfs.c | 8 +- drivers/gpu/drm/i915

[Intel-gfx] [PATCH 24/25] drm/i915/display: move workqueues to display struct

From: Dave Airlie Signed-off-by: Dave Airlie --- drivers/gpu/drm/i915/display/intel_display.c | 18 +- drivers/gpu/drm/i915/i915_drv.h | 10 +- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/d

[Intel-gfx] [PATCH 25/25] drm/i915/display: move pps/backlight mutexes into display

From: Dave Airlie Signed-off-by: Dave Airlie --- .../gpu/drm/i915/display/intel_backlight.c| 28 +++--- drivers/gpu/drm/i915/display/intel_pps.c | 38 +-- drivers/gpu/drm/i915/i915_drv.c | 4 +- drivers/gpu/drm/i915/i915_drv.h | 12 +

[Intel-gfx] [PATCH 23/25] drm/i915/display: move fdi_rx_config into display struct

From: Dave Airlie Signed-off-by: Dave Airlie --- drivers/gpu/drm/i915/display/intel_crt.c | 2 +- drivers/gpu/drm/i915/display/intel_fdi.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel

[Intel-gfx] [PATCH 21/25] drm/i915/display: move a bunch of platform misc regs to display

From: Dave Airlie Signed-off-by: Dave Airlie --- drivers/gpu/drm/i915/display/intel_ddi.c | 4 +- drivers/gpu/drm/i915/display/intel_display.c | 4 +- .../drm/i915/display/intel_display_power.c| 76 +-- drivers/gpu/drm/i915/display/intel_dpio_phy.c | 6 +- drivers/g

[Intel-gfx] [PATCH 19/25] drm/i915/display: move delay and pch values to display struct

From: Dave Airlie Signed-off-by: Dave Airlie --- drivers/gpu/drm/i915/display/intel_display.c | 34 +-- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 4 +-- drivers/gpu/drm/i915/display/intel_vrr.c | 6 ++-- drivers/gpu/drm/i915/i915_drv.h | 14

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for refactor display struct

== Series Details == Series: refactor display struct URL : https://patchwork.freedesktop.org/series/94413/ State : warning == Summary == $ dim checkpatch origin/drm-tip 191aa552f294 drm/i915: move display funcs into a display struct. (v3) 675cb420d0d5 drm/i915/display: move cdclk info into dis

Re: [Intel-gfx] [PATCH v2 0/7] drm/i915/bios: remove vbt ddi_port_info caching

On Fri, 03 Sep 2021, "Souza, Jose" wrote: > On Fri, 2021-09-03 at 14:04 +0300, Jani Nikula wrote: >> José, I'd like to get an ack from you on this before applying. I know >> it's bound conflict with your in flight series. Thoughts? > > If you are okay in adding more data at the end of intel_bios_e

Re: [Intel-gfx] [PATCH 4/7] drm/i915/bios: use alternate aux channel directly from child data

On Thu, 26 Aug 2021, "Nautiyal, Ankit K" wrote: > On 8/24/2021 7:04 PM, Jani Nikula wrote: >> Avoid extra caching of the data. >> >> Cc: José Roberto de Souza >> Signed-off-by: Jani Nikula >> --- >> drivers/gpu/drm/i915/display/intel_bios.c | 26 +++ >> drivers/gpu/drm/i91

Re: [Intel-gfx] [PATCH 01/10] drm/i915: move display funcs into a display struct.

On Mon, Sep 6, 2021 at 9:45 PM Dave Airlie wrote: > On Mon, 6 Sept 2021 at 18:18, Jani Nikula wrote: > > On Mon, 06 Sep 2021, Dave Airlie wrote: > > > From: Dave Airlie > > > > > > This is the first step in an idea to refactor the display code > > > into a bit more of a corner. > > > > So, do w

[Intel-gfx] ✓ Fi.CI.BAT: success for refactor display struct

== Series Details == Series: refactor display struct URL : https://patchwork.freedesktop.org/series/94413/ State : success == Summary == CI Bug Log - changes from CI_DRM_10555 -> Patchwork_20972 Summary --- **SUCCESS** No regressi

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Use Transparent Hugepages when IOMMU is enabled

On Fri, Sep 03, 2021 at 01:47:52PM +0100, Tvrtko Ursulin wrote: > > On 29/07/2021 15:06, Daniel Vetter wrote: > > On Thu, Jul 29, 2021 at 3:34 PM Tvrtko Ursulin > > wrote: > > > > > > From: Tvrtko Ursulin > > > > > > Usage of Transparent Hugepages was disabled in 9987da4b5dcf > > > ("drm/i915:

Re: [Intel-gfx] [PATCH v2 1/6] drm/i915/ttm: Implement a function to copy the contents of two TTM-base objects

On 06/09/2021 17:55, Thomas Hellström wrote: When backing up or restoring contents of pinned objects at suspend / resume time we need to allocate a new object as the backup. Add a function to facilitate copies between the two. Some data needs to be copied before the migration context is ready for

Re: [Intel-gfx] [PATCH v2 2/6] drm/i915/gem: Implement a function to process all gem objects of a region

On 06/09/2021 17:55, Thomas Hellström wrote: An upcoming common pattern is to traverse the region object list and perform certain actions on all objects in a region. It's a little tricky to get the list locking right, in particular since a gem object may change region unless it's pinned or the ob

Re: [Intel-gfx] [PATCH v2 0/7] drm: add per-connector hotplug events

Ping, anyone up for a review?

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Use Transparent Hugepages when IOMMU is enabled

On 07/09/2021 09:42, Daniel Vetter wrote: On Fri, Sep 03, 2021 at 01:47:52PM +0100, Tvrtko Ursulin wrote: On 29/07/2021 15:06, Daniel Vetter wrote: On Thu, Jul 29, 2021 at 3:34 PM Tvrtko Ursulin wrote: From: Tvrtko Ursulin Usage of Transparent Hugepages was disabled in 9987da4b5dcf ("dr

Re: [Intel-gfx] [PATCH 01/10] drm/i915: move display funcs into a display struct.

On Tue, 7 Sept 2021 at 18:15, Daniel Vetter wrote: > > On Mon, Sep 6, 2021 at 9:45 PM Dave Airlie wrote: > > On Mon, 6 Sept 2021 at 18:18, Jani Nikula > > wrote: > > > On Mon, 06 Sep 2021, Dave Airlie wrote: > > > > From: Dave Airlie > > > > > > > > This is the first step in an idea to refact

[Intel-gfx] ✗ Fi.CI.IGT: failure for refactor display struct

== Series Details == Series: refactor display struct URL : https://patchwork.freedesktop.org/series/94413/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10555_full -> Patchwork_20972_full Summary --- **FAILURE** S

[Intel-gfx] [PATCH v4] drm/i915: Use Transparent Hugepages when IOMMU is enabled

From: Tvrtko Ursulin Usage of Transparent Hugepages was disabled in 9987da4b5dcf ("drm/i915: Disable THP until we have a GPU read BW W/A"), but since it appears majority of performance regressions reported with an enabled IOMMU can be almost eliminated by turning them on, lets just do that. To e

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/adlp: Add support for remapping CCS FBs (rev3)

Hi Lakshmi, Tomi, could you check the failure below, looks like a storage device issue. On Tue, Sep 07, 2021 at 05:25:30AM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/adlp: Add support for remapping CCS FBs (rev3) > URL : https://patchwork.freedesktop.org/series/94108/

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/adlp: Add support for remapping CCS FBs (rev3)

This looks very much like SATA drive issue. I'll replace the drive for shard-iclb3 and we'll see if this happens again. Tomi > -Original Message- > From: Deak, Imre > Subject: Re: ✗ Fi.CI.IGT: failure for drm/i915/adlp: Add support for > remapping CCS FBs (rev3) > > Hi Lakshmi, Tomi, >

Re: [Intel-gfx] [PATCH v4] drm/i915: Use Transparent Hugepages when IOMMU is enabled

Hi, For completeness sake, it might be worth mentioning specifically what (synthetic) test-cases regress with THP patch. * Skylake GT4e: 20-25% SynMark TexMem* (whereas all MemBW GPU tests either improve or are not affected) * Broxton J4205: 7% MemBW GPU texture 2-3% SynMark TexMem*

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Use Transparent Hugepages when IOMMU is enabled (rev2)

== Series Details == Series: drm/i915: Use Transparent Hugepages when IOMMU is enabled (rev2) URL : https://patchwork.freedesktop.org/series/93122/ State : warning == Summary == $ dim checkpatch origin/drm-tip 2f994050d821 drm/i915: Use Transparent Hugepages when IOMMU is enabled -:6: ERROR:GI

[Intel-gfx] [PATCH] drm/i915/display: Add HDR mode helper function

Add helper function with returns if HDR mode in on Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/display/intel_display.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_displa

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Use Transparent Hugepages when IOMMU is enabled (rev2)

== Series Details == Series: drm/i915: Use Transparent Hugepages when IOMMU is enabled (rev2) URL : https://patchwork.freedesktop.org/series/93122/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10557 -> Patchwork_20973 Summ

[Intel-gfx] [PATCH] drm/i915: Free the returned object of acpi_evaluate_dsm()

As per the comment on top of acpi_evaluate_dsm(): | * Evaluate device's _DSM method with specified GUID, revision id and | * function number. Caller needs to free the returned object. We should free the returned object of acpi_evaluate_dsm() to avoid memory leakage. Otherwise the kmemleak splat w

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Add HDR mode helper function

== Series Details == Series: drm/i915/display: Add HDR mode helper function URL : https://patchwork.freedesktop.org/series/94428/ State : success == Summary == CI Bug Log - changes from CI_DRM_10557 -> Patchwork_20974 Summary --- **S

[Intel-gfx] [PATCH] kernel/locking: Add context to ww_mutex_trylock.

i915 will soon gain an eviction path that trylock a whole lot of locks for eviction, getting dmesg failures like below: BUG: MAX_LOCK_DEPTH too low! turning off the locking correctness validator. depth: 48 max: 48! 48 locks held by i915_selftest/5776: #0: 888101a79240 (&dev->mutex){}-{3:

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Free the returned object of acpi_evaluate_dsm()

== Series Details == Series: drm/i915: Free the returned object of acpi_evaluate_dsm() URL : https://patchwork.freedesktop.org/series/94433/ State : success == Summary == CI Bug Log - changes from CI_DRM_10557 -> Patchwork_20975 Summary ---

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for kernel/locking: Add context to ww_mutex_trylock.

== Series Details == Series: kernel/locking: Add context to ww_mutex_trylock. URL : https://patchwork.freedesktop.org/series/94437/ State : warning == Summary == $ dim checkpatch origin/drm-tip 9eed33b42bf0 kernel/locking: Add context to ww_mutex_trylock. -:166: CHECK:MACRO_ARG_REUSE: Macro ar

[Intel-gfx] ✓ Fi.CI.BAT: success for kernel/locking: Add context to ww_mutex_trylock.

== Series Details == Series: kernel/locking: Add context to ww_mutex_trylock. URL : https://patchwork.freedesktop.org/series/94437/ State : success == Summary == CI Bug Log - changes from CI_DRM_10557 -> Patchwork_20976 Summary --- *

Re: [Intel-gfx] [PATCH 05/11] drm/i915: Rename i915_gem_context_get_vm_rcu to i915_gem_context_get_eb_vm

On 06/09/2021 09:51, Daniel Vetter wrote: On Fri, Sep 03, 2021 at 09:05:00AM +0100, Tvrtko Ursulin wrote: On 02/09/2021 15:20, Daniel Vetter wrote: The important part isn't so much that this does an rcu lookup - that's more an implementation detail, which will also be removed. The thing tha

Re: [Intel-gfx] [PATCH] kernel/locking: Add context to ww_mutex_trylock.

Hi Maarten, I love your patch! Perhaps something to improve: [auto build test WARNING on regulator/for-next] [also build test WARNING on tegra-drm/drm/tegra/for-next v5.14] [cannot apply to tip/locking/core linus/master next-20210907] [If your patch is applied to the wrong git tree, kindly drop

Re: [Intel-gfx] [PATCH v7 3/8] i915/gvt: use DEFINE_DYNAMIC_DEBUG_CATEGORIES to create "gvt:core:" etc categories

On 06/09/2021 18:41, jim.cro...@gmail.com wrote: On Mon, Sep 6, 2021 at 6:26 AM Tvrtko Ursulin mailto:tvrtko.ursu...@linux.intel.com>> wrote: > > > On 03/09/2021 20:22, jim.cro...@gmail.com wrote: > > On Fri, Sep 3, 2021 at 5:07 AM Tvrtko Ursulin > >

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/display: Add HDR mode helper function

== Series Details == Series: drm/i915/display: Add HDR mode helper function URL : https://patchwork.freedesktop.org/series/94428/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10557_full -> Patchwork_20974_full Summary

Re: [Intel-gfx] [PATCH V4] drm/i915/gen11: Disable cursor clock gating in HDR mode

Hi Ville, I have posted single patch for HDR mode here https://patchwork.freedesktop.org/series/94428/#rev1 . Please review and ack. I will post " drm/i915/gen11: Disable cursor clock gating in HDR mode " on top of that patch. Thanks, Tejas > -Original Message- > From: Surendrakumar U

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add MOCS tables for XeHP SDV and DG2 (rev3)

== Series Details == Series: drm/i915: Add MOCS tables for XeHP SDV and DG2 (rev3) URL : https://patchwork.freedesktop.org/series/94344/ State : success == Summary == CI Bug Log - changes from CI_DRM_10557 -> Patchwork_20977 Summary ---

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Free the returned object of acpi_evaluate_dsm()

== Series Details == Series: drm/i915: Free the returned object of acpi_evaluate_dsm() URL : https://patchwork.freedesktop.org/series/94433/ State : success == Summary == CI Bug Log - changes from CI_DRM_10557_full -> Patchwork_20975_full S

[Intel-gfx] [PATCH 0/8] i915: Introduce Xe_HP compute engines

The Xe_HP architecture introduces compute engines as a new engine class. These compute command streamers (CCS) are similar to the render engine, except that they're intended for GPGPU usage and lack support for the 3D pipeline. The definition of I915_ENGINE_CLASS_COMPUTE is new ABI; see below for

[Intel-gfx] [PATCH 3/8] drm/i915/xehp: Add Compute CS IRQ handlers

Add execlists and GuC interrupts for compute CS into existing IRQ handlers. All compute command streamers belong to the same compute class, so the only change needed to enable their interrupts is to program their GT engine interrupt mask registers. CCS0 shares the register with CCS1, while CCS2 a

[Intel-gfx] [PATCH 1/8] drm/i915/xehp: Define compute class and engine

Introduce a Compute Command Streamer (CCS), which has access to the media and GPGPU pipelines (but not the 3D pipeline). To begin with, define the compute class/engine common functions, based on the existing render ones. Bspec: 46167, 45544 Original-patch-by: Michel Thierry Cc: Daniele Ceraolo Sp

[Intel-gfx] [PATCH 2/8] drm/i915/xehp: CCS shares the render reset domain

The reset domain is shared between render and all compute engines, so resetting one will affect the others. Note: Before performing a reset on an RCS or CCS engine, the GuC will attempt to preempt-to-idle the other non-hung RCS/CCS engines to avoid impacting other clients (since some shared modul

[Intel-gfx] [PATCH 6/8] drm/i915/xehp: Define context scheduling attributes in lrc descriptor

In Dual Context mode the EUs are shared between render and compute command streamers. The hardware provides a field in the lrc descriptor to indicate the prioritization of the thread dispatch associated to the corresponding context. The context priority is set to 'low' at creation time and relies

[Intel-gfx] [PATCH 8/8] drm/i915/xehp: Extend uninterruptible OpenCL workloads to CCS

From: John Harrison Now that OpenCL workloads can run on the compute engine, we need to set preempt_timeout_ms = 0 on the CCS engines too. Signed-off-by: John Harrison Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 9 + 1 file changed, 5 insertions(+), 4 del

[Intel-gfx] [PATCH 7/8] drm/i915/xehp: Enable ccs/dual-ctx in RCU_MODE

We have to specify in the Render Control Unit Mode register when CCS is enabled. Bspec: 46034 Original-patch-by: Michel Thierry Cc: Daniele Ceraolo Spurio Cc: Tvrtko Ursulin Cc: Vinay Belgaumkar Signed-off-by: Daniele Ceraolo Spurio Signed-off-by: Aravind Iddamsetty Signed-off-by: Matt Roper

[Intel-gfx] [PATCH 4/8] drm/i915/xehp: CCS should use RCS setup functions

The compute engine handles the same commands the render engine can (except 3D pipeline), so it makes sense that CCS is more similar to RCS than non-render engines. The CCS context state (lrc) is also similar to the render one, so reuse it. Note that the compute engine has its own CTX_R_PWR_CLK_STA

[Intel-gfx] [PATCH 5/8] drm/i915/xehp: compute engine pipe_control

From: Daniele Ceraolo Spurio CCS re-uses the RCS functions for breadcrumb and flush emission. However, CCS pipe_control has additional programming restrictions: - Command Streamer Stall Enable must be always set - Post Sync Operations must not be set to Write PS Depth Count - 3D-related bits mus

[Intel-gfx] [PATCH] drm/i915/gt: Add separate MOCS table for Gen12 devices other than TGL/RKL

MOCS table of TGL/RKL has MOCS[1] set to L3_UC. While for other gen12 devices we need to set MOCS[1] as L3_WB, So adding a new MOCS table for other gen 12 devices eg. ADL. Fixes: cfbe5291a189 ("drm/i915/gt: Initialize unused MOCS entries with device specific values") Cc: Matt Roper Signed-off-by

Re: [Intel-gfx] [PATCH v7 3/8] i915/gvt: use DEFINE_DYNAMIC_DEBUG_CATEGORIES to create "gvt:core:" etc categories

On Tue, Sep 7, 2021 at 9:14 AM Tvrtko Ursulin wrote: > > > On 06/09/2021 18:41, jim.cro...@gmail.com wrote: > > On Mon, Sep 6, 2021 at 6:26 AM Tvrtko Ursulin > > mailto:tvrtko.ursu...@linux.intel.com>> > > wrote: > > > > > > > > > On 03/09/2021 20:22, jim.cro...@gmail.com > >

Re: [Intel-gfx] [PATCH] drm/i915/gt: Add separate MOCS table for Gen12 devices other than TGL/RKL

On Tue, Sep 07, 2021 at 10:46:39PM +0530, Ayaz A Siddiqui wrote: > MOCS table of TGL/RKL has MOCS[1] set to L3_UC. > While for other gen12 devices we need to set MOCS[1] as L3_WB, > So adding a new MOCS table for other gen 12 devices eg. ADL. > > Fixes: cfbe5291a189 ("drm/i915/gt: Initialize unuse

[Intel-gfx] ✓ Fi.CI.IGT: success for kernel/locking: Add context to ww_mutex_trylock.

== Series Details == Series: kernel/locking: Add context to ww_mutex_trylock. URL : https://patchwork.freedesktop.org/series/94437/ State : success == Summary == CI Bug Log - changes from CI_DRM_10557_full -> Patchwork_20976_full Summary --

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Add HDR mode helper function (rev2)

== Series Details == Series: drm/i915/display: Add HDR mode helper function (rev2) URL : https://patchwork.freedesktop.org/series/94428/ State : success == Summary == CI Bug Log - changes from CI_DRM_10557 -> Patchwork_20978 Summary ---

Re: [Intel-gfx] [PATCH v2 3/6] drm/i915 Implement LMEM backup and restore for suspend / resume

On 06/09/2021 17:55, Thomas Hellström wrote: Just evict unpinned objects to system. For pinned LMEM objects, make a backup system object and blit the contents to that. Backup is performed in three steps, 1: Opportunistically evict evictable objects using the gpu blitter. 2: After gt idle, evict

Re: [Intel-gfx] [PATCH] drm/i915/gt: Add separate MOCS table for Gen12 devices other than TGL/RKL

On Tue, Sep 07, 2021 at 10:27:28AM -0700, Matt Roper wrote: > On Tue, Sep 07, 2021 at 10:46:39PM +0530, Ayaz A Siddiqui wrote: > > MOCS table of TGL/RKL has MOCS[1] set to L3_UC. > > While for other gen12 devices we need to set MOCS[1] as L3_WB, > > So adding a new MOCS table for other gen 12 devic

Re: [Intel-gfx] [PATCH 01/10] drm/i915: move display funcs into a display struct.

On Tue, Sep 07, 2021 at 07:52:17PM +1000, Dave Airlie wrote: > On Tue, 7 Sept 2021 at 18:15, Daniel Vetter wrote: > > > > On Mon, Sep 6, 2021 at 9:45 PM Dave Airlie wrote: > > > On Mon, 6 Sept 2021 at 18:18, Jani Nikula > > > wrote: > > > > On Mon, 06 Sep 2021, Dave Airlie wrote: > > > > > Fro

Re: [Intel-gfx] [PATCH] drm/i915/gt: Add separate MOCS table for Gen12 devices other than TGL/RKL

On Tue, Sep 07, 2021 at 08:41:06PM +0300, Ville Syrjälä wrote: > On Tue, Sep 07, 2021 at 10:27:28AM -0700, Matt Roper wrote: > > On Tue, Sep 07, 2021 at 10:46:39PM +0530, Ayaz A Siddiqui wrote: > > > MOCS table of TGL/RKL has MOCS[1] set to L3_UC. > > > While for other gen12 devices we need to set

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Add MOCS tables for XeHP SDV and DG2 (rev3)

== Series Details == Series: drm/i915: Add MOCS tables for XeHP SDV and DG2 (rev3) URL : https://patchwork.freedesktop.org/series/94344/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10557_full -> Patchwork_20977_full Summa

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,1/3] drm/i915/display: Some code improvements and code style fixes for DRRS (rev3)

== Series Details == Series: series starting with [v3,1/3] drm/i915/display: Some code improvements and code style fixes for DRRS (rev3) URL : https://patchwork.freedesktop.org/series/94342/ State : success == Summary == CI Bug Log - changes from CI_DRM_10558 -> Patchwork_20979 ==

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Add MOCS tables for XeHP SDV and DG2 (rev3)

On Tue, Sep 07, 2021 at 07:05:51PM +, Patchwork wrote: > == Series Details == > > Series: drm/i915: Add MOCS tables for XeHP SDV and DG2 (rev3) > URL : https://patchwork.freedesktop.org/series/94344/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_10557_full -> Pat

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gtt: add some flushing for the 64K GTT path (rev2)

== Series Details == Series: drm/i915/gtt: add some flushing for the 64K GTT path (rev2) URL : https://patchwork.freedesktop.org/series/94332/ State : success == Summary == CI Bug Log - changes from CI_DRM_10558 -> Patchwork_20980 Summary -

Re: [Intel-gfx] [PATCH v10 0/4] drm: update locking for modesetting

On 31/8/21 3:24 am, Desmond Cheong Zhi Xi wrote: Sorry for the noise, rebasing on top of drm-misc-next. Please ignore the v9 series. Hi, I updated the patch set with some suggestions by Daniel Vetter, and dropped the patches after patch 4 so that we can stick the landing for avoiding races with

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/display: Add HDR mode helper function (rev2)

== Series Details == Series: drm/i915/display: Add HDR mode helper function (rev2) URL : https://patchwork.freedesktop.org/series/94428/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10557_full -> Patchwork_20978_full Summa

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Introduce Xe_HP compute engines

== Series Details == Series: i915: Introduce Xe_HP compute engines URL : https://patchwork.freedesktop.org/series/94450/ State : warning == Summary == $ dim checkpatch origin/drm-tip f33a9b39f861 drm/i915/xehp: Define compute class and engine -:13: WARNING:BAD_SIGN_OFF: Non-standard signature:

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915: Introduce Xe_HP compute engines

== Series Details == Series: i915: Introduce Xe_HP compute engines URL : https://patchwork.freedesktop.org/series/94450/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/i

[Intel-gfx] ✓ Fi.CI.BAT: success for i915: Introduce Xe_HP compute engines

== Series Details == Series: i915: Introduce Xe_HP compute engines URL : https://patchwork.freedesktop.org/series/94450/ State : success == Summary == CI Bug Log - changes from CI_DRM_10558 -> Patchwork_20981 Summary --- **SUCCESS**

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Add separate MOCS table for Gen12 devices other than TGL/RKL

== Series Details == Series: drm/i915/gt: Add separate MOCS table for Gen12 devices other than TGL/RKL URL : https://patchwork.freedesktop.org/series/94451/ State : warning == Summary == $ dim checkpatch origin/drm-tip 95b55732351d drm/i915/gt: Add separate MOCS table for Gen12 devices other

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Add separate MOCS table for Gen12 devices other than TGL/RKL

== Series Details == Series: drm/i915/gt: Add separate MOCS table for Gen12 devices other than TGL/RKL URL : https://patchwork.freedesktop.org/series/94451/ State : success == Summary == CI Bug Log - changes from CI_DRM_10558 -> Patchwork_20982

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v3,1/3] drm/i915/display: Some code improvements and code style fixes for DRRS (rev3)

== Series Details == Series: series starting with [v3,1/3] drm/i915/display: Some code improvements and code style fixes for DRRS (rev3) URL : https://patchwork.freedesktop.org/series/94342/ State : success == Summary == CI Bug Log - changes from CI_DRM_10558_full -> Patchwork_20979_full

[Intel-gfx] [PATCH] drm/i915: deduplicate frequency dump on debugfs

Although commit 9dd4b065446a ("drm/i915/gt: Move pm debug files into a gt aware debugfs") says it was moving debug files to gt/, the i915_frequency_info file was left behind and its implementation copied into drivers/gpu/drm/i915/gt/debugfs_gt_pm.c. Over time we had several patches having to change

Re: [Intel-gfx] [PATCH 3/3] drm/i915: remove some debug-only registers from MCHBAR

On Tue, Jul 06, 2021 at 04:44:30PM -0700, Lucas De Marchi wrote: On Thu, Nov 05, 2020 at 10:02:27AM +0200, Joonas Lahtinen wrote: Quoting Lucas De Marchi (2020-11-05 03:04:22) On Wed, Nov 04, 2020 at 11:55:15AM +0200, Joonas Lahtinen wrote: Quoting Lucas De Marchi (2020-10-27 06:46:18) GT_PER

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v3,1/3] drm/i915/display: Some code improvements and code style fixes for DRRS (rev2)

On Sat, 2021-09-04 at 00:11 +, Patchwork wrote: Patch Details Series: series starting with [v3,1/3] drm/i915/display: Some code improvements and code style fixes for DRRS (rev2) URL:https://patchwork.freedesktop.org/series/94342/ State: failure Details: https://intel-gfx-ci.01.org

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gtt: add some flushing for the 64K GTT path (rev2)

== Series Details == Series: drm/i915/gtt: add some flushing for the 64K GTT path (rev2) URL : https://patchwork.freedesktop.org/series/94332/ State : success == Summary == CI Bug Log - changes from CI_DRM_10558_full -> Patchwork_20980_full

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: deduplicate frequency dump on debugfs

== Series Details == Series: drm/i915: deduplicate frequency dump on debugfs URL : https://patchwork.freedesktop.org/series/94455/ State : warning == Summary == $ dim checkpatch origin/drm-tip 7c0de9fb0c56 drm/i915: deduplicate frequency dump on debugfs -:11: WARNING:COMMIT_LOG_LONG_LINE: Poss

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: deduplicate frequency dump on debugfs

== Series Details == Series: drm/i915: deduplicate frequency dump on debugfs URL : https://patchwork.freedesktop.org/series/94455/ State : success == Summary == CI Bug Log - changes from CI_DRM_10559 -> Patchwork_20983 Summary --- **

[Intel-gfx] [PATCH] drm/i915: Get PM ref before accessing HW register

Seeing these errors when GT is likely in suspend state- "RPM wakelock ref not held during HW access" Ensure GT is awake before trying to access HW registers. Avoid reading the register if that is not the case. Signed-off-by: Vinay Belgaumkar --- drivers/gpu/drm/i915/gt/intel_rps.c | 8 +++-

[Intel-gfx] ✓ Fi.CI.IGT: success for i915: Introduce Xe_HP compute engines

== Series Details == Series: i915: Introduce Xe_HP compute engines URL : https://patchwork.freedesktop.org/series/94450/ State : success == Summary == CI Bug Log - changes from CI_DRM_10558_full -> Patchwork_20981_full Summary --- **

[Intel-gfx] [PATCH 00/21] i915/display: split and constify vtable

This is orthogonal to my display ptr refactoring and should probably be applied first. The display funcs vtable was a bit of mess, lots of intermixing of internal display functionality and interfaces to watermarks/irqs. It's also considered not great security practice to leave writeable function

[Intel-gfx] [PATCH 01/21] drm/i915/pm: drop get_fifo_size vfunc.

From: Dave Airlie The i845_update_wm code was always calling the i845 variant, and the i9xx_update_wm had only a choice between i830 and i9xx paths, hardly worth the vfunc overhead. Signed-off-by: Dave Airlie --- drivers/gpu/drm/i915/i915_drv.h | 2 -- drivers/gpu/drm/i915/intel_pm.c | 20 +++

[Intel-gfx] [PATCH 02/21] drm/i915: make update_wm take a dev_priv.

From: Dave Airlie The crtc was never being used here. --- drivers/gpu/drm/i915/display/intel_display.c | 10 +- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/intel_pm.c | 18 ++ drivers/gpu/drm/i915/intel_pm.h | 2 +-

[Intel-gfx] [PATCH 03/21] drm/i915/wm: move the update watermark wrapper to display side.

From: Dave Airlie A vague goal is to have the vfunc table be the api between wm and display, not having direction function calls cross the boundary. This aligns the legacy update_wm with the newer vfuncs. The comment probably needs to live somewhere else, it seems like it should live in the pm

  1   2   >