[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [01/11] drm/i915: Release i915_gem_context from a worker (rev3)

== Series Details == Series: series starting with [01/11] drm/i915: Release i915_gem_context from a worker (rev3) URL : https://patchwork.freedesktop.org/series/94285/ State : success == Summary == CI Bug Log - changes from CI_DRM_10548_full -> Patchwork_20949_full ===

Re: [Intel-gfx] [PATCH 05/11] drm/i915: Rename i915_gem_context_get_vm_rcu to i915_gem_context_get_eb_vm

On 02/09/2021 15:20, Daniel Vetter wrote: The important part isn't so much that this does an rcu lookup - that's more an implementation detail, which will also be removed. The thing that makes this different from other functions is that it's gettting you the vm that batchbuffers will run in fo

Re: [Intel-gfx] [PATCH v2 1/7] drm/i915/bios: use hdmi level shift directly from child data

LGTM. Reviewed-by: Ankit Nautiyal On 9/1/2021 9:39 PM, Jani Nikula wrote: Avoid extra caching of the data. Cc: José Roberto de Souza Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_bios.c | 26 +-- drivers/gpu/drm/i915/i915_drv.h | 4

Re: [Intel-gfx] [PATCH v2 2/7] drm/i915/bios: use max tmds clock directly from child data

LGTM. Reviewed-by: Ankit Nautiyal On 9/1/2021 9:40 PM, Jani Nikula wrote: Avoid extra caching of the data. Cc: José Roberto de Souza Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_bios.c | 52 +++ drivers/gpu/drm/i915/i915_drv.h | 2 - 2

Re: [Intel-gfx] [PATCH v2 3/7] drm/i915/bios: use dp max link rate directly from child data

A small nitpick below: Otherwise the patch looks good to me. Reviewed-by: Ankit Nautiyal On 9/1/2021 9:40 PM, Jani Nikula wrote: Avoid extra caching of the data. Cc: José Roberto de Souza Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_bios.c | 28 ++

Re: [Intel-gfx] [PATCH v2 4/7] drm/i915/bios: use alternate aux channel directly from child data

LGTM. Reviewed-by: Ankit Nautiyal On 9/1/2021 9:40 PM, Jani Nikula wrote: Avoid extra caching of the data. v2: Check for !info->devdata in intel_bios_port_aux_ch() (Ankit) Cc: José Roberto de Souza Cc: Ankit Nautiyal Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_bios

[Intel-gfx] [PATCH V5 0/5] drm/i915/gt: Initialize unused MOCS entries to L3_WB

Gen >= 12 onwards MOCS table doesn't have a setting for PTE so I915_MOCS_PTE is not a valid index and it will have different MOCS values are based on the platform. To detect these kinds of misprogramming, all the unspecified and reserved MOCS indexes are set to WB_L3. TGL/RKL unspecified MOCS inde

[Intel-gfx] [PATCH V5 1/5] drm/i915/gt: Add support of mocs propagation

Now there are lots of Command and registers that require mocs index programming. So propagating mocs_index from mocs to gt so that it can be used directly without having platform-specific checks. V2: Changed 'i915_mocs_index_gt' to anonymous structure. Cc: CQ Tang Reviewed-by: Matt Roper Signed-

[Intel-gfx] [PATCH V5 2/5] drm/i915/gt: Set CMD_CCTL to UC for Gen12 Onward

Cache-control registers for Command Stream(CMD_CCTL) are used to set catchability for memory writes and reads outputted by Command Streamers on Gen12 onward platforms. These registers need to point un-cached(UC) MOCS index. Reviewed-by: Matt Roper Signed-off-by: Ayaz A Siddiqui --- drivers/gpu

[Intel-gfx] [PATCH V5 3/5] drm/i915/gt: Set BLIT_CCTL reg to un-cached

Blitter commands which do not have MOCS fields rely on cacheability of BlitterCacheControlRegister which was mapped to index 0 by default.Once we changed the MOCS value of index 0 to L3 WB, tests like gem_linear_blits started failing due to a change in cacheability from UC to WB. Program and place

[Intel-gfx] [PATCH V5 4/5] drm/i915/gt: Initialize unused MOCS entries with device specific values

Historically we've initialized all undefined/reserved entries in a platform's MOCS table to the contents of table entry #1 (i.e., I915_MOCS_PTE). Going forward, we can't assume that table entry #1 will always contain suitable values to use for undefined/reserved table indices. We'll allow a platfor

[Intel-gfx] [PATCH V5 5/5] drm/i915/gt: Initialize L3CC table in mocs init

From: Sreedhar Telukuntla Initialize the L3CC table as part of mocs initialization to program LNCFCMOCSx registers so that the mocs settings are available for selection for subsequent memory transactions in the driver load path. We need to keep L3CC initialization in intel_mocs_init_engine() als

Re: [Intel-gfx] [PATCH 07/19] drm/i915: vma is always backed by an object.

Op 31-08-2021 om 12:29 schreef Tvrtko Ursulin: > > On 31/08/2021 10:34, Maarten Lankhorst wrote: >> Op 31-08-2021 om 11:18 schreef Tvrtko Ursulin: >>> >>> On 30/08/2021 13:09, Maarten Lankhorst wrote: vma->obj and vma->resv are now never NULL, and some checks can be removed. >>> >>> Is the dir

Re: [Intel-gfx] [PATCH 14/19] drm/i915: Add i915_vma_unbind_unlocked, and take obj lock for i915_vma_unbind

Op 30-08-2021 om 14:10 schreef Maarten Lankhorst: > We want to remove more members of i915_vma, which requires the locking to be > held more often. > > Start requiring gem object lock for i915_vma_unbind, as it's one of the > callers that may unpin pages. > > Some special care is needed when evicti

[Intel-gfx] [PULL] drm-misc-next-fixes

drm-misc-next-fixes-2021-09-03: drm-misc-next-fixes for v5.15: - Fix ttm_bo_move_memcpy() when ttm_resource is subclassed. - Small fixes to panfrost, mgag200, vc4. - Small ttm compilation fixes. The following changes since commit 2819cf0e7dbe45a2bccf2f6c60fe6a27b299cc3e: Merge tag 'drm-misc-next

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/gt: Initialize unused MOCS entries to L3_WB

== Series Details == Series: drm/i915/gt: Initialize unused MOCS entries to L3_WB URL : https://patchwork.freedesktop.org/series/94315/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gp

Re: [Intel-gfx] [PATCH v2 5/7] drm/i915/bios: move ddc pin mapping code next to ddc pin sanitize

LGTM. Reviewed-by: Ankit Nautiyal On 9/1/2021 9:40 PM, Jani Nikula wrote: Move code around to avoid a forward declaration in the future. Cc: José Roberto de Souza Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_bios.c | 154 +++--- 1 file changed, 77 ins

Re: [Intel-gfx] [PATCH v2 6/7] drm/i915/bios: use ddc pin directly from child data

LGTM. Reviewed-by: Ankit Nautiyal On 9/1/2021 9:40 PM, Jani Nikula wrote: Avoid extra caching of the data. This is slightly more subtle than one would think. For one thing, we explicitly ignore 0 value in child device ddc pin; this is specified as N/A and does not warrant a warning. For anothe

Re: [Intel-gfx] [PATCH v2 7/7] drm/i915/bios: get rid of vbt ddi_port_info

LGTM. Reviewed-by: Ankit Nautiyal On 9/1/2021 9:40 PM, Jani Nikula wrote: We can finally remove the extra caching in ddi_port_info. Good riddance. v2: Rebased Cc: José Roberto de Souza Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_bios.c | 63 +--

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Initialize unused MOCS entries to L3_WB

== Series Details == Series: drm/i915/gt: Initialize unused MOCS entries to L3_WB URL : https://patchwork.freedesktop.org/series/94315/ State : success == Summary == CI Bug Log - changes from CI_DRM_10549 -> Patchwork_20950 Summary ---

Re: [Intel-gfx] [PATCH 01/11] drm/i915: Release i915_gem_context from a worker

On 02/09/2021 21:02, Daniel Vetter wrote: On Thu, Sep 2, 2021 at 6:20 PM Tvrtko Ursulin wrote: On 02/09/2021 16:05, Daniel Vetter wrote: On Thu, Sep 2, 2021 at 2:42 PM Tvrtko Ursulin wrote: On 13/08/2021 21:30, Daniel Vetter wrote: The only reason for this really is the i915_gem_engines

Re: [Intel-gfx] [PATCH 07/19] drm/i915: vma is always backed by an object.

On 03/09/2021 10:31, Maarten Lankhorst wrote: Op 31-08-2021 om 12:29 schreef Tvrtko Ursulin: On 31/08/2021 10:34, Maarten Lankhorst wrote: Op 31-08-2021 om 11:18 schreef Tvrtko Ursulin: On 30/08/2021 13:09, Maarten Lankhorst wrote: vma->obj and vma->resv are now never NULL, and some check

Re: [Intel-gfx] [PATCH v2 0/7] drm/i915/bios: remove vbt ddi_port_info caching

On Wed, 01 Sep 2021, Jani Nikula wrote: > v2 of https://patchwork.freedesktop.org/series/93957/ with the CI issues > fixed (fingers crossed!). José, I'd like to get an ack from you on this before applying. I know it's bound conflict with your in flight series. Thoughts? BR, Jani. > > BR, > Jani

Re: [Intel-gfx] [PATCH v7 3/8] i915/gvt: use DEFINE_DYNAMIC_DEBUG_CATEGORIES to create "gvt:core:" etc categories

On 31/08/2021 21:21, Jim Cromie wrote: The gvt component of this driver has ~120 pr_debugs, in 9 categories quite similar to those in DRM. Following the interface model of drm.debug, add a parameter to map bits to these categorizations. DEFINE_DYNAMIC_DEBUG_CATEGORIES(debug_gvt, __gvt_debug,

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable TPS3/4 on all platforms that support them

On Mon, 22 Mar 2021, Ville Syrjälä wrote: > On Fri, Mar 19, 2021 at 07:08:40PM -, Patchwork wrote: >> == Series Details == >> >> Series: drm/i915: Enable TPS3/4 on all platforms that support them >> URL : https://patchwork.freedesktop.org/series/88186/ >> State : success >> >> == Summary =

Re: [Intel-gfx] [PATCH v7 5/8] drm_print: add choice to use dynamic debug in drm-debug

On 31/08/2021 21:21, Jim Cromie wrote: drm's debug system writes 10 distinct categories of messages to syslog using a small API[1]: drm_dbg*(10 names), DRM_DEV_DEBUG*(3 names), DRM_DEBUG*(8 names). There are thousands of these callsites, each categorized in this systematized way. These callsi

[Intel-gfx] [PATCH] drm/i915/request: fix early tracepoints

Currently we blow up in trace_dma_fence_init, when calling into get_driver_name or get_timeline_name, since both the engine and context might be NULL(or contain some garbage address) in the case of newly allocated slab objects via the request ctor. Note that we also use SLAB_TYPESAFE_BY_RCU here, w

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for use DYNAMIC_DEBUG to implement DRM.debug (rev2)

On 03/09/2021 01:31, jim.cro...@gmail.com wrote: On Tue, Aug 31, 2021 at 5:38 PM Patchwork > wrote: __ *Patch Details* *Series:* use DYNAMIC_DEBUG to implement DRM.debug (rev2) *URL:* https://patchwork.freedesktop.org/series/9

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gt: Initialize unused MOCS entries to L3_WB

== Series Details == Series: drm/i915/gt: Initialize unused MOCS entries to L3_WB URL : https://patchwork.freedesktop.org/series/94315/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10549_full -> Patchwork_20950_full Summar

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/request: fix early tracepoints

== Series Details == Series: drm/i915/request: fix early tracepoints URL : https://patchwork.freedesktop.org/series/94317/ State : warning == Summary == $ dim checkpatch origin/drm-tip c82cbcd35cf9 drm/i915/request: fix early tracepoints -:40: ERROR:GIT_COMMIT_ID: Please use git commit descrip

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/request: fix early tracepoints

== Series Details == Series: drm/i915/request: fix early tracepoints URL : https://patchwork.freedesktop.org/series/94317/ State : success == Summary == CI Bug Log - changes from CI_DRM_10549 -> Patchwork_20951 Summary --- **SUCCESS*

[Intel-gfx] i915 with Dell XPS 9310

Hello all, I've been following recent kernels on this dell laptop for almost a year now to work through some issues with the ath11k module. I've been experiencing random occasional video artifacts for most of that time. These artifacts would cause the i915 module to report some kind of underr

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Use Transparent Hugepages when IOMMU is enabled

On 29/07/2021 15:06, Daniel Vetter wrote: On Thu, Jul 29, 2021 at 3:34 PM Tvrtko Ursulin wrote: From: Tvrtko Ursulin Usage of Transparent Hugepages was disabled in 9987da4b5dcf ("drm/i915: Disable THP until we have a GPU read BW W/A"), but since it appears majority of performance regressio

Re: [Intel-gfx] i915 with Dell XPS 9310

Hi, Please report actual bug using instructions: https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs ? Br, Jani Saarinen Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo > -Original Message- > From: Intel-gfx On Behalf Of wi nk > Sent: perjantai 3. s

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for use DYNAMIC_DEBUG to implement DRM.debug (rev2)

On Fri, Sep 03, 2021 at 12:29:51PM +0100, Tvrtko Ursulin wrote: > > On 03/09/2021 01:31, jim.cro...@gmail.com wrote: > > > > > > On Tue, Aug 31, 2021 at 5:38 PM Patchwork > > > > wrote: > > > > __ > > *Patch Details* > > *Series:* use

Re: [Intel-gfx] [PATCH V5 0/5] drm/i915/gt: Initialize unused MOCS entries to L3_WB

Hi, I see a failure reported on IGT-CI for this series for SKL, igt@gem_ctx_isolation@preservation-s3@rcs0: shard-skl: PASS -> DMESG-WARN Changes set in this series are applicable for gen12 onward platforms except TGL/RKL. So above failure look like a false alarm to me. Regards -Ayaz >

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/request: fix early tracepoints

== Series Details == Series: drm/i915/request: fix early tracepoints URL : https://patchwork.freedesktop.org/series/94317/ State : success == Summary == CI Bug Log - changes from CI_DRM_10549_full -> Patchwork_20951_full Summary ---

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Initialize unused MOCS entries to L3_WB

== Series Details == Series: drm/i915/gt: Initialize unused MOCS entries to L3_WB URL : https://patchwork.freedesktop.org/series/94315/ State : success == Summary == CI Bug Log - changes from CI_DRM_10549_full -> Patchwork_20950_full Summar

Re: [Intel-gfx] [PATCH V5 0/5] drm/i915/gt: Initialize unused MOCS entries to L3_WB

Hi Ayaz, Re-reported Patch : https://patchwork.freedesktop.org/series/94315/ Regards, Jaswanth Kattamanchi -Original Message- From: Siddiqui, Ayaz A Sent: Friday, September 3, 2021 6:29 PM To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana ; Illipilli, TejasreeX ; Kattamanc

[Intel-gfx] [PATCH RESEND] drm/i915: Flush buffer pools on driver remove

In preparation for clean driver release, attempts to drain work queues and release freed objects are taken at driver remove time. However, GT buffer pools are now not flushed before the driver release phase. Since unused objects may stay there for up to one second, some may survive until driver re

[Intel-gfx] [PATCH RESEND] drm/i915: Mark GPU wedging on driver unregister unrecoverable

GPU wedged flag now set on driver unregister to prevent from further using the GPU can be then cleared unintentionally when calling __intel_gt_unset_wedged() still before the flag is finally marked unrecoverable. We need to have it marked unrecoverable earlier. Implement that by replacing a call t

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable TPS3/4 on all platforms that support them

On Fri, Sep 03, 2021 at 02:10:17PM +0300, Jani Nikula wrote: > On Mon, 22 Mar 2021, Ville Syrjälä wrote: > > On Fri, Mar 19, 2021 at 07:08:40PM -, Patchwork wrote: > >> == Series Details == > >> > >> Series: drm/i915: Enable TPS3/4 on all platforms that support them > >> URL : https://patch

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Flush buffer pools on driver remove (rev3)

== Series Details == Series: drm/i915: Flush buffer pools on driver remove (rev3) URL : https://patchwork.freedesktop.org/series/91177/ State : success == Summary == CI Bug Log - changes from CI_DRM_10549 -> Patchwork_20952 Summary ---

Re: [Intel-gfx] [PATCH V5 0/5] drm/i915/gt: Initialize unused MOCS entries to L3_WB

Thanks Ayaz for the patches and all the review efforts. Merged the patches. -Ram On 2021-09-03 at 19:11:24 +0530, Kattamanchi, JaswanthX wrote: > Hi Ayaz, > > Re-reported > > Patch : https://patchwork.freedesktop.org/series/94315/ > > Regards, > Jaswanth Kattamanchi > > -Original Message-

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable TPS3/4 on all platforms that support them

On Fri, Sep 03, 2021 at 06:03:30PM +0300, Ville Syrjälä wrote: > On Fri, Sep 03, 2021 at 02:10:17PM +0300, Jani Nikula wrote: > > On Mon, 22 Mar 2021, Ville Syrjälä wrote: > > > On Fri, Mar 19, 2021 at 07:08:40PM -, Patchwork wrote: > > >> == Series Details == > > >> > > >> Series: drm/i915:

[Intel-gfx] [PATCH] drm/i915/gtt: add some flushing for the 64K GTT path

If we need to mark the PDE as operating in 64K GTT mode, we should be paranoid and flush the extra writes, like we already do for the PTEs. On some platforms the clflush can apparently add the just the right amount of magical delay to force the GPU to see the updated entry. Signed-off-by: Matthew

Re: [Intel-gfx] [PATCH] drm/i915/gtt: add some flushing for the 64K GTT path

Matthew Auld writes: > If we need to mark the PDE as operating in 64K GTT mode, we should be > paranoid and flush the extra writes, like we already do for the PTEs. On > some platforms the clflush can apparently add the just the right amount > of magical delay to force the GPU to see the updated

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Flush buffer pools on driver remove (rev3)

== Series Details == Series: drm/i915: Flush buffer pools on driver remove (rev3) URL : https://patchwork.freedesktop.org/series/91177/ State : success == Summary == CI Bug Log - changes from CI_DRM_10549_full -> Patchwork_20952_full Summar

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Mark GPU wedging on driver unregister unrecoverable (rev2)

== Series Details == Series: drm/i915: Mark GPU wedging on driver unregister unrecoverable (rev2) URL : https://patchwork.freedesktop.org/series/94247/ State : success == Summary == CI Bug Log - changes from CI_DRM_10550 -> Patchwork_20953

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable TPS3/4 on all platforms that support them

On Fri, Sep 03, 2021 at 06:39:14PM +0300, Imre Deak wrote: > On Fri, Sep 03, 2021 at 06:03:30PM +0300, Ville Syrjälä wrote: > > On Fri, Sep 03, 2021 at 02:10:17PM +0300, Jani Nikula wrote: > > > On Mon, 22 Mar 2021, Ville Syrjälä wrote: > > > > On Fri, Mar 19, 2021 at 07:08:40PM -, Patchwork w

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gtt: add some flushing for the 64K GTT path

== Series Details == Series: drm/i915/gtt: add some flushing for the 64K GTT path URL : https://patchwork.freedesktop.org/series/94332/ State : success == Summary == CI Bug Log - changes from CI_DRM_10550 -> Patchwork_20954 Summary ---

[Intel-gfx] [PATCH] drm/i915/adl_s: Remove require_force_probe protection

From: ravitejax Removing force probe protection from ADLS platform. Did not observe warnings, errors, flickering or any visual defects while doing ordinary tasks like browsing and editing documents in a two monitor setup. For more info drm-tip idle run results : https://intel-gfx-ci.01.org/tree/

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Mark GPU wedging on driver unregister unrecoverable (rev2)

== Series Details == Series: drm/i915: Mark GPU wedging on driver unregister unrecoverable (rev2) URL : https://patchwork.freedesktop.org/series/94247/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10550_full -> Patchwork_20953_full

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/adl_s: Remove require_force_probe protection

== Series Details == Series: drm/i915/adl_s: Remove require_force_probe protection URL : https://patchwork.freedesktop.org/series/94338/ State : success == Summary == CI Bug Log - changes from CI_DRM_10550 -> Patchwork_20955 Summary ---

Re: [Intel-gfx] [PATCH v7 3/8] i915/gvt: use DEFINE_DYNAMIC_DEBUG_CATEGORIES to create "gvt:core:" etc categories

On Fri, Sep 3, 2021 at 5:07 AM Tvrtko Ursulin wrote: > > > On 31/08/2021 21:21, Jim Cromie wrote: > > The gvt component of this driver has ~120 pr_debugs, in 9 categories > > quite similar to those in DRM. Following the interface model of > > drm.debug, add a parameter to map bits to these catego

[Intel-gfx] [PATCH v5 25/25] drm/i915/guc: Add GuC kernel doc

From: Matthew Brost Add GuC kernel doc for all structures added thus far for GuC submission and update the main GuC submission section with the new interface details. v2: - Drop guc_active.lock DOC v3: - Fixup a few kernel doc comments (Daniele) v4 (Daniele): - Implement doc suggestions from

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Clean up GuC CI failures, simplify locking, and kernel DOC (rev9)

== Series Details == Series: Clean up GuC CI failures, simplify locking, and kernel DOC (rev9) URL : https://patchwork.freedesktop.org/series/93704/ State : warning == Summary == $ dim checkpatch origin/drm-tip 6d1bb5d22544 drm/i915/guc: Fix blocked context accounting 6398818fa78a drm/i915/guc

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Clean up GuC CI failures, simplify locking, and kernel DOC (rev9)

== Series Details == Series: Clean up GuC CI failures, simplify locking, and kernel DOC (rev9) URL : https://patchwork.freedesktop.org/series/93704/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

Re: [Intel-gfx] [PATCH v2 0/7] drm/i915/bios: remove vbt ddi_port_info caching

On Fri, 2021-09-03 at 14:04 +0300, Jani Nikula wrote: > On Wed, 01 Sep 2021, Jani Nikula wrote: > > v2 of https://patchwork.freedesktop.org/series/93957/ with the CI issues > > fixed (fingers crossed!). > > José, I'd like to get an ack from you on this before applying. I know > it's bound conflic

Re: [Intel-gfx] [PATCH v2 4/8] drm/i915/display: Some code improvements and code style fixes for DRRS

On Thu, 2021-09-02 at 18:15 +0300, Gwan-gyeong Mun wrote: > > On 8/25/21 3:58 AM, José Roberto de Souza wrote: > > It started as a code style fix for the lines above 100 col but it > > turned out to simplifications to intel_drrs_set_state(). > > Now it receives the desired refresh rate type, high

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gtt: add some flushing for the 64K GTT path

== Series Details == Series: drm/i915/gtt: add some flushing for the 64K GTT path URL : https://patchwork.freedesktop.org/series/94332/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10550_full -> Patchwork_20954_full Summar

[Intel-gfx] ✗ Fi.CI.BAT: failure for Clean up GuC CI failures, simplify locking, and kernel DOC (rev9)

== Series Details == Series: Clean up GuC CI failures, simplify locking, and kernel DOC (rev9) URL : https://patchwork.freedesktop.org/series/93704/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10550 -> Patchwork_20956 Sum

Re: [Intel-gfx] [PATCH v2 5/8] drm/i915/display: Share code between intel_drrs_flush and intel_drrs_invalidate

On Thu, 2021-09-02 at 18:57 +0300, Gwan-gyeong Mun wrote: > > On 8/25/21 3:58 AM, José Roberto de Souza wrote: > > Both functions are pretty much equal, with minor changes that can be > > handled by a single parameter. > > > > Signed-off-by: José Roberto de Souza > > --- > > drivers/gpu/drm/i9

Re: [Intel-gfx] [PATCH v7 5/8] drm_print: add choice to use dynamic debug in drm-debug

On Fri, Sep 3, 2021 at 5:15 AM Tvrtko Ursulin wrote: > > > On 31/08/2021 21:21, Jim Cromie wrote: > > drm's debug system writes 10 distinct categories of messages to syslog > > using a small API[1]: drm_dbg*(10 names), DRM_DEV_DEBUG*(3 names), > > DRM_DEBUG*(8 names). There are thousands of these

[Intel-gfx] [PATCH v3 1/3] drm/i915/display: Some code improvements and code style fixes for DRRS

It started as a code style fix for the lines above 100 col but it turned out to simplifications to intel_drrs_set_state(). Now it receives the desired refresh rate type, high or low. v3: - Fixed the mode refesh rate debug message Cc: Gwan-gyeong Mun Signed-off-by: José Roberto de Souza --- dri

[Intel-gfx] [PATCH v3 3/3] drm/i915/display: Prepare DRRS for frontbuffer rendering drop

Frontbuffer rendering will be dropped for modern platforms but before that we to prepare DRRS for it. intel_drrs_flush and intel_drrs_invalidate will not be called for platforms that will not support frontbuffer rendering so DRRS needs another way to be notified about to page flips so it can chang

[Intel-gfx] [PATCH v3 2/3] drm/i915/display: Share code between intel_drrs_flush and intel_drrs_invalidate

Both functions are pretty much equal, with minor changes that can be handled by a single parameter. v3: - not scheduling work from invalidate operations Cc: Gwan-gyeong Mun Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_drrs.c | 82 +-- 1 file c

Re: [Intel-gfx] [PATCH v2 7/8] drm/i915/display/skl+: Drop frontbuffer rendering support

On Thu, 2021-09-02 at 21:42 +0300, Gwan-gyeong Mun wrote: > > On 8/25/21 3:58 AM, José Roberto de Souza wrote: > > By now all the userspace applications should have migrated to atomic > > or at least be calling DRM_IOCTL_MODE_DIRTYFB. > > > > With that we can kill frontbuffer rendering support in

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/adl_s: Remove require_force_probe protection

== Series Details == Series: drm/i915/adl_s: Remove require_force_probe protection URL : https://patchwork.freedesktop.org/series/94338/ State : success == Summary == CI Bug Log - changes from CI_DRM_10550_full -> Patchwork_20955_full Summa

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v3,1/3] drm/i915/display: Some code improvements and code style fixes for DRRS

== Series Details == Series: series starting with [v3,1/3] drm/i915/display: Some code improvements and code style fixes for DRRS URL : https://patchwork.freedesktop.org/series/94342/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10550 -> Patchwork_20957 =

[Intel-gfx] [PATCH v5 07/25] Revert "drm/i915/gt: Propagate change in error status to children on unhold"

From: Matthew Brost Propagating errors to dependent fences is broken and can lead to errors from one client ending up in another. In commit 3761baae908a ("Revert "drm/i915: Propagate errors on awaiting already signaled fences""), we attempted to get rid of fence error propagation but missed the c

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v3,1/3] drm/i915/display: Some code improvements and code style fixes for DRRS (rev2)

== Series Details == Series: series starting with [v3,1/3] drm/i915/display: Some code improvements and code style fixes for DRRS (rev2) URL : https://patchwork.freedesktop.org/series/94342/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10550 -> Patchwork_20958 ==

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Clean up GuC CI failures, simplify locking, and kernel DOC (rev10)

== Series Details == Series: Clean up GuC CI failures, simplify locking, and kernel DOC (rev10) URL : https://patchwork.freedesktop.org/series/93704/ State : warning == Summary == $ dim checkpatch origin/drm-tip 7a92435f3439 drm/i915/guc: Fix blocked context accounting 4cbb7ec8d2a5 drm/i915/gu

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Clean up GuC CI failures, simplify locking, and kernel DOC (rev10)

== Series Details == Series: Clean up GuC CI failures, simplify locking, and kernel DOC (rev10) URL : https://patchwork.freedesktop.org/series/93704/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

Re: [Intel-gfx] [PATCH v2 7/8] drm/i915/display/skl+: Drop frontbuffer rendering support

On Fri, 2021-09-03 at 22:09 +, Souza, Jose wrote: > On Thu, 2021-09-02 at 21:42 +0300, Gwan-gyeong Mun wrote: > > > > On 8/25/21 3:58 AM, José Roberto de Souza wrote: > > > By now all the userspace applications should have migrated to atomic > > > or at least be calling DRM_IOCTL_MODE_DIRTYFB.

[Intel-gfx] [PATCH 0/2] drm/i915: Add MOCS tables for XeHP SDV and DG2

Now that Ayaz's MOCS initialization series has landed on drm-intel-gt-next, we can add the new MOCS tables for XeHP SDV and DG2. [1] https://patchwork.freedesktop.org/series/94315/ Lucas De Marchi (1): drm/i915/xehpsdv: Define MOCS table for XeHP SDV Matt Roper (1): drm/i915/dg2: Define MOCS

[Intel-gfx] [PATCH 2/2] drm/i915/dg2: Define MOCS table for DG2

Bspec: 45101, 45427 Cc: Ramalingam C Signed-off-by: Matt Roper Reviewed-by: Matt Atwood --- drivers/gpu/drm/i915/gt/intel_mocs.c | 37 +++- 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel

[Intel-gfx] [PATCH 1/2] drm/i915/xehpsdv: Define MOCS table for XeHP SDV

From: Lucas De Marchi Like DG1, XeHP SDV doesn't have LLC/eDRAM control values due to being a dgfx card. XeHP SDV adds 2 more bits: L3_GLBGO to "push the Go point to memory for L3 destined transaction" and L3_LKP to "enable Lookup for uncacheable accesses". Bspec: 45101 Cc: Daniele Ceraolo Spuri

[Intel-gfx] ✗ Fi.CI.BAT: failure for Clean up GuC CI failures, simplify locking, and kernel DOC (rev10)

== Series Details == Series: Clean up GuC CI failures, simplify locking, and kernel DOC (rev10) URL : https://patchwork.freedesktop.org/series/93704/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10550 -> Patchwork_20959 Su

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Add MOCS tables for XeHP SDV and DG2

== Series Details == Series: drm/i915: Add MOCS tables for XeHP SDV and DG2 URL : https://patchwork.freedesktop.org/series/94344/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10550 -> Patchwork_20960 Summary --- **F

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Add MOCS tables for XeHP SDV and DG2 (rev2)

== Series Details == Series: drm/i915: Add MOCS tables for XeHP SDV and DG2 (rev2) URL : https://patchwork.freedesktop.org/series/94344/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10550 -> Patchwork_20961 Summary ---