On 02/08/2021 21:10, Matthew Brost wrote:
On Mon, Aug 02, 2021 at 09:59:01AM +0100, Tvrtko Ursulin wrote:
On 30/07/2021 19:06, Matthew Brost wrote:
On Fri, Jul 30, 2021 at 10:58:38AM +0100, Tvrtko Ursulin wrote:
On 27/07/2021 19:20, Matthew Brost wrote:
With GuC submission contexts can g
Greetings,
Original proposal:
https://www.mail-archive.com/amd-gfx@lists.freedesktop.org/msg62387.html
Abstract: Add "preferred color format", "active color format", "active bpc",
and "active Broadcast RGB" drm properties,
to control color information send to the monitor.
It seems that the "pr
On 2021.07.21 17:53:35 +0200, Christoph Hellwig wrote:
> Remove the separately included Makefile and just use the relative
> reference from the main i915 Makefile as for source files in other
> subdirectories.
>
We agreed to make gvt mostly self-contained in its own directory
before. Although I do
On 2021.07.29 09:20:22 +0200, Christoph Hellwig wrote:
> On Wed, Jul 28, 2021 at 02:59:25PM -0300, Jason Gunthorpe wrote:
> > On Wed, Jul 28, 2021 at 01:38:58PM +, Wang, Zhi A wrote:
> >
> > > I guess those APIs you were talking about are KVM-only. For other
> > > hypervisors, e.g. Xen, ARCN c
On 7/31/21 3:10 AM, José Roberto de Souza wrote:
Only to execute tests with PSR2 selective fetch enabled and check what
is broken.
IGT tests know to fail with this:
- kms_cursor_legacy: all tests that checks if evasion happend, I have
fix for it making cursor_slowpath() returns true for displ
On 7/31/21 3:10 AM, José Roberto de Souza wrote:
There is no users of it, so no need to keep handling for it.
Cc: Gwan-gyeong Mun
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_fbc.c | 10 +-
drivers/gpu/drm/i915/display/intel_frontbuffer.h |
== Series Details ==
Series: drm/i915: Apply CMTG clock disabling WA while DPLL0 is enabled
URL : https://patchwork.freedesktop.org/series/93318/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10440_full -> Patchwork_20762_full
==
On Tue, Aug 3, 2021 at 6:53 AM Matthew Brost wrote:
>
> Minimum set of patches to enable GuC submission on DG1 and enable it by
> default.
>
> A little difficult to test as IGTs do not work with DG1 due to a bunch
> of uAPI features being disabled (e.g. relocations, caching memory
> options, etc..
== Series Details ==
Series: remove rcu support from i915_address_space (rev2)
URL : https://patchwork.freedesktop.org/series/93314/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
21c76a470088 drm/i915: Drop code to handle set-vm races from execbuf
-:17: WARNING:COMMIT_LOG_LONG_
== Series Details ==
Series: remove rcu support from i915_address_space (rev2)
URL : https://patchwork.freedesktop.org/series/93314/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-drivers/gpu/drm
Media userspace was the last userspace to still use them, and they
converted now too:
https://github.com/intel/media-driver/commit/144020c37770083974bedf59902b70b8f444c799
This means no reason anymore to make relocations faster than they've
been for the first 9 years of gem. This code was added i
It's already removed, this just garbage collects it all.
v2: Rebase over s/GEN/GRAPHICS_VER/
v3: Also ditch eb.reloc_pool and eb.reloc_context (Maarten)
Signed-off-by: Daniel Vetter
Cc: Jon Bloomfield
Cc: Chris Wilson
Cc: Maarten Lankhorst
Cc: Daniel Vetter
Cc: Joonas Lahtinen
Cc: "Thomas
== Series Details ==
Series: remove rcu support from i915_address_space (rev2)
URL : https://patchwork.freedesktop.org/series/93314/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10440 -> Patchwork_20764
Summary
---
On Tue, Aug 03, 2021 at 12:08:05PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Apply CMTG clock disabling WA while DPLL0 is enabled
> URL : https://patchwork.freedesktop.org/series/93318/
> State : failure
Pushed to -din, thanks for the review. The DPLL0 dependecy was c
== Series Details ==
Series: drm/i915: Apply CMTG clock disabling WA while DPLL0 is enabled
URL : https://patchwork.freedesktop.org/series/93318/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10440 -> Patchwork_20762
Summar
On Wed, Jul 28, 2021 at 4:22 PM Matthew Auld
wrote:
>
> On Mon, 26 Jul 2021 at 17:10, Tvrtko Ursulin
> wrote:
> >
> >
> > On 26/07/2021 16:14, Jason Ekstrand wrote:
> > > On Mon, Jul 26, 2021 at 3:31 AM Maarten Lankhorst
> > > wrote:
> > >>
> > >> Op 23-07-2021 om 13:34 schreef Matthew Auld:
> >
== Series Details ==
Series: series starting with [1/2] drm/i915: Disable gpu relocations
URL : https://patchwork.freedesktop.org/series/93340/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
42973b3c2f93 drm/i915: Disable gpu relocations
-:12: WARNING:COMMIT_LOG_LONG_LINE: Possi
Hi Rajat,
The merge proposals are now in place after discussing a bit more with upstream:
- https://gitlab.gnome.org/GNOME/gsettings-desktop-schemas/-/merge_requests/49
- https://gitlab.gnome.org/GNOME/mutter/-/merge_requests/1952
- https://gitlab.gnome.org/GNOME/gnome-control-center/-/merge_r
== Series Details ==
Series: drm/i915: Apply CMTG clock disabling WA while DPLL0 is enabled
URL : https://patchwork.freedesktop.org/series/93318/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10440_full -> Patchwork_20762_full
==
== Series Details ==
Series: series starting with [1/2] drm/i915: Disable gpu relocations
URL : https://patchwork.freedesktop.org/series/93340/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10442 -> Patchwork_20765
Summary
On Tue, Aug 3, 2021 at 10:09 AM Daniel Vetter wrote:
> On Wed, Jul 28, 2021 at 4:22 PM Matthew Auld
> wrote:
> >
> > On Mon, 26 Jul 2021 at 17:10, Tvrtko Ursulin
> > wrote:
> > >
> > >
> > > On 26/07/2021 16:14, Jason Ekstrand wrote:
> > > > On Mon, Jul 26, 2021 at 3:31 AM Maarten Lankhorst
> >
Both are
Reviewed-by: Jason Ekstrand
On Tue, Aug 3, 2021 at 7:49 AM Daniel Vetter wrote:
>
> It's already removed, this just garbage collects it all.
>
> v2: Rebase over s/GEN/GRAPHICS_VER/
>
> v3: Also ditch eb.reloc_pool and eb.reloc_context (Maarten)
>
> Signed-off-by: Daniel Vetter
> Cc: J
Op 2021-08-03 om 17:45 schreef Jason Ekstrand:
> On Tue, Aug 3, 2021 at 10:09 AM Daniel Vetter wrote:
>> On Wed, Jul 28, 2021 at 4:22 PM Matthew Auld
>> wrote:
>>> On Mon, 26 Jul 2021 at 17:10, Tvrtko Ursulin
>>> wrote:
On 26/07/2021 16:14, Jason Ekstrand wrote:
> On Mon, Jul 26, 2
== Series Details ==
Series: Enable GuC submission by default on DG1
URL : https://patchwork.freedesktop.org/series/93325/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10440_full -> Patchwork_20763_full
Summary
---
On Wed, 28 Jul 2021 21:49:18 -0300
Jason Gunthorpe wrote:
> Keep track of all the vfio_devices that have been added to the device set
> and use this list in vfio_pci_try_bus_reset() instead of trying to work
> backwards from the pci_device.
>
> The dev_set->lock directly prevents devices from jo
On Tue, 3 Aug 2021 13:41:52 -0300
Jason Gunthorpe wrote:
> On Tue, Aug 03, 2021 at 10:34:06AM -0600, Alex Williamson wrote:
> > I think the vfio_pci_find_reset_target() function needs to be re-worked
> > to just tell us true/false that it's ok to reset the provided device,
> > not to anoint an arb
On Tue, 2021-08-03 at 14:17 +0300, Gwan-gyeong Mun wrote:
>
> On 7/31/21 3:10 AM, José Roberto de Souza wrote:
> > Only to execute tests with PSR2 selective fetch enabled and check what
> > is broken.
> >
> > IGT tests know to fail with this:
> > - kms_cursor_legacy: all tests that checks if evas
On Tue, 2021-08-03 at 14:20 +0300, Gwan-gyeong Mun wrote:
>
> On 7/31/21 3:10 AM, José Roberto de Souza wrote:
> > There is no users of it, so no need to keep handling for it.
> >
> > Cc: Gwan-gyeong Mun
> > Signed-off-by: José Roberto de Souza
> > ---
> > drivers/gpu/drm/i915/display/intel_f
On Tue, Aug 03, 2021 at 02:15:13PM +0200, Daniel Vetter wrote:
> On Tue, Aug 3, 2021 at 6:53 AM Matthew Brost wrote:
> >
> > Minimum set of patches to enable GuC submission on DG1 and enable it by
> > default.
> >
> > A little difficult to test as IGTs do not work with DG1 due to a bunch
> > of uA
On Tue, Aug 03, 2021 at 05:43:15PM +0800, Zhenyu Wang wrote:
> Acked-by: Zhenyu Wang
>
> Thanks a lot for this effort!
Great, do we have a submission plan for this? how much does it clash
with my open_device/etc patch? ie does the whole thing have to go
through the vfio tree?
Thanks,
Jason
From: Chris Wilson
Switch the search and grow code of the _wa_add to use _wa_index and
_wa_list_grow.
Signed-off-by: Chris Wilson
Reviewed-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 124 +++-
1 file changed, 71 insertions(+), 53 deletions(-)
d
From: Chris Wilson
Strip the encoded bits from the register offset so that we only use the
address for looking up the RING_NONPRIV entry.
Signed-off-by: Chris Wilson
Reviewed-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 66 +
1 file changed,
Refactor intel_engine_apply_whitelist into locked and unlocked versions
so that a caller who already has the lock can apply whitelist.
v2: Fix sparse warning
v3: (Chris)
- Drop prefix and suffix for static function
- Use longest to shortest line ordering for variable declaration
Signed-off-by: Um
OA reports can be triggered into the OA buffer by writing into the
OAREPORTTRIG registers. Whitelist the registers to allow non-privileged
user to trigger reports.
Whitelist registers only if perf_stream_paranoid is set to 0. In
i915_perf_open_ioctl, this setting is checked and the whitelist is
en
It is useful to have markers in the OA reports to identify triggered
reports. Whitelist some OA counters that can be used as markers.
A triggered report can be found faster if we can sample the HW tail and
head registers when the report was triggered. Whitelist OA buffer
specific registers.
v2:
-
This is a revival of the patch series to support triggered perf query reports
from here - https://patchwork.freedesktop.org/series/83831/
The patches were not pushed earlier because corresponding UMD changes were
missing. This revival addresses UMD changes in GPUvis for this series. GPUvis
uses th
From: Chris Wilson
The OA subsystem would like to enable its privileged clients access to
the OA registers from execbuf. This requires temporarily removing the
HW validation from those registers for the duration of the OA client,
for which we need to allow OA to dynamically adjust the set of
RING
From: Piotr Maciejewski
A clock gating switch can control if the performance monitoring and
observation logic is enaled or not. Ensure that we enable the clocks.
v2: Separate code from other patches (Lionel)
v3: Reset PMON enable when disabling perf to save power (Lionel)
v4: Use intel_uncore_rm
i915 used to support time based sampling mode which is good for overall
system monitoring, but is not enough for query mode used to measure a
single draw call or dispatch. Gen9-Gen11 are using current i915 perf
implementation for query, but Gen12+ requires a new approach for query
based on triggere
+ Joonas
On Tue, Aug 03, 2021 at 01:13:41PM -0700, Umesh Nerlige Ramappa wrote:
This is a revival of the patch series to support triggered perf query reports
from here - https://patchwork.freedesktop.org/series/83831/
The patches were not pushed earlier because corresponding UMD changes were
mi
On Fri, 2021-07-09 at 22:41 -0700, Matt Roper wrote:
> On Thu, Jul 08, 2021 at 02:18:26PM -0700, José Roberto de Souza wrote:
> > Alderlake-P have different values for MBUS DBOX A credits depending
> > if MBUS join is enabled or not.
> >
> > BSpec: 50343
> > BSpec: 54369
> > Cc: Matt Atwood
> > S
On Tue, Aug 03, 2021 at 01:18:38PM -0700, Umesh Nerlige Ramappa wrote:
+ Joonas
On Tue, Aug 03, 2021 at 01:13:41PM -0700, Umesh Nerlige Ramappa wrote:
This is a revival of the patch series to support triggered perf query reports
from here - https://patchwork.freedesktop.org/series/83831/
The p
On Tue, Aug 03, 2021 at 10:34:06AM -0600, Alex Williamson wrote:
> On Wed, 28 Jul 2021 21:49:18 -0300
> Jason Gunthorpe wrote:
>
> > Keep track of all the vfio_devices that have been added to the device set
> > and use this list in vfio_pci_try_bus_reset() instead of trying to work
> > backwards
== Series Details ==
Series: Enable triggered perf query for Xe_HP
URL : https://patchwork.freedesktop.org/series/93357/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./include/uapi/drm/i915_drm.h:2408: warning: This comment starts with '/**',
but isn't a kernel-d
== Series Details ==
Series: Enable triggered perf query for Xe_HP
URL : https://patchwork.freedesktop.org/series/93357/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10442 -> Patchwork_20766
Summary
---
**FAILURE**
Taking a PM reference to prevent intel_gt_wait_for_idle from short
circuiting while a deregister context H2G is in flight.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_engine_pm.h | 5 +
drivers/gpu/drm/i915/gt/intel_gt_pm.h | 13 +++
drivers/gpu/drm/i915/gt/uc/int
Dynamically allocate space for lrc descriptor registration with the GuC
rather than using a large static buffer indexed by the guc_id. If no
space is available to register a context, fall back to tasklet flow
control mechanism. Only allow 1/2 of the space to be allocated outside
the tasklet to prev
As discussed in [1] we are introducing a new parallel submission uAPI
for the i915 which allows more than 1 BB to be submitted in an execbuf
IOCTL. This is the implemenation for both GuC and execlists.
In addition to selftests in the series, an IGT is available implemented
in the first 4 patches [
Check return of __xa_store when registering a context as this can fail
in a rare case if not memory can not be allocated. If this occurs fall
back on the tasklet flow control and try again in the future.
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c| 16 +
Add a heuristic which checks if over half of the available guc_ids are
currently consumed by requests not ready to be submitted. If this
heuristic is true at request creation time (normal guc_id allocation
location) force all submissions + guc_ids allocations to tasklet.
Signed-off-by: Matthew Bro
Calling switch_to_kernel_context isn't needed if the engine PM reference
is taken while all contexts are pinned. By not calling
switch_to_kernel_context we save on issuing a request to the engine.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 4
1 file changed
For testing purposes it may make sense to reduce the number of guc_ids
available to be allocated. Add debugfs support for setting the number of
guc_ids.
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gt/uc/intel_guc_debugfs.c| 31 +++
.../gpu/drm/i915/gt/uc/intel_guc_submi
Number of available GuC contexts ids might be limited.
Stop referring in code to macro and use variable instead.
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h | 2 ++
.../gpu/drm/i915/gt/uc/intel_guc_submission.c| 16 +
Move fields related to controlling the GuC submission state machine to a
unique object (guc_submit_engine) rather than the global GuC state
(intel_guc). This encapsulation allows multiple instances of submission
objects to operate in parallel and a single instance can block if needed
while another
Introduce context parent-child relationship. Once this relationship is
created all pinning / unpinning operations are directed to the parent
context. The parent context is responsible for pinning all of its'
children and itself.
This is a precursor to the full GuC multi-lrc implementation but alig
Rather than returning -EAGAIN to the user when no guc_ids are available,
implement a fair sharing algorithm in the kernel which blocks submissons
until guc_ids become available. Submissions are released one at a time,
based on priority, until the guc_id pressure is released to ensure fair
sharing o
Implement GuC parent-child context pin / unpin functions in which in any
contexts in the relationship are pinned all the contexts are pinned. The
parent owns most of the pinning / unpinning process and the children
direct any pins / unpins to the parent.
Patch implements a number of unused functio
Sometimes it is desirable to queue work up for later if the GT PM isn't
held and run that work on next GT PM unpark.
Implemented with a list in the GT of all pending work, workqueues in
the list, a callback to add a workqueue to the list, and finally a
wakeref post_get callback that iterates / dra
Goal is to remove all input sanity checks from the core submission.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 35 +++
1 file changed, 21 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i91
Add logical engine mapping. This is required for split-frame, as
workloads need to be placed on engines in a logically contiguous manner.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 60 ---
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
The GuC must receive requests in the order submitted for contexts in a
parent-child relationship to function correctly. To ensure this, insert
a submit fence between the current request and last request submitted
for requests / contexts in a parent child relationship. This is
conceptually similar t
Implement multi-lrc submission via a single workqueue entry and single
H2G. The workqueue entry contains an updated tail value for each
request, of all the contexts in the multi-lrc submission, and updates
these values simultaneously. As such, the tasklet and bypass path have
been updated to coales
Add 5 selftests for hard (from user space) to recreate flow conditions.
Test listed below:
1. A test to verify that the number of guc_ids can be exhausted and all
submissions still complete.
2. A test to verify that the flow control state machine can recover from
a full GPU reset.
3. A teset to
Taking a PM reference to prevent intel_gt_wait_for_idle from short
circuiting while a scheduling of user context could be enabled.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/Makefile | 1 +
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 36 +--
2 file
In GuC parent-child contexts the parent context controls the scheduling,
ensure only the parent does the scheduling operations.
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 52 +++
1 file changed, 41 insertions(+), 11 deletions(-)
diff --git a
Since child contexts do not own the guc_ids or GuC context registration,
child contexts can simply be freed on destroy. Add
guc_child_context_destroy context operation to do this.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 7 +++
1 file changed, 7 in
Move the job of creating an input/exec fences (from a file descriptor)
out of i915_gem_do_execbuffer.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 75 +++
1 file changed, 43 insertions(+), 32 deletions(-)
diff --
For some users of multi-lrc, e.g. split frame, it isn't safe to preempt
mid BB. To safely enable preemption at the BB boundary, a handshake
between to parent and child is needed. This is implemented via custom
emit_bb_start & emit_fini_breadcrumb functions and enabled via by
default if a context is
Display the workqueue status in debugfs for GuC contexts that are in
parent-child relationship.
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 56 +--
1 file changed, 39 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/inte
Update context and full GPU reset to work with multi-lrc. The idea is
parent context tracks all the active requests inflight for itself and
its' children. The parent context owns the reset replaying / canceling
requests as needed.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_co
Prove multi-lrc and single-lrc are independent.
Prove multi-lrc guc_ids flow control works.
Prove multi-lrc hanging the tastlet can recover from a GPU reset.
Cc: John Harrison
Signed-off-by: Matthew Brost
---
.../i915/gt/uc/selftest_guc_flow_control.c| 299 ++
.../drm/i915/g
Move the job of creating a new file descriptor and passing it back to
userspace to i915_gem_execbuffer2.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 45 ++-
1 file changed, 25 insertions(+), 20 deletions(-)
diff
Assign contexts in parent-child relationship consecutive guc_ids. This
is accomplished by partitioning guc_id space between ones that need to
be consecutive (1/16 available guc_ids) and ones that do not (15/16 of
available guc_ids). The consecutive search is implemented via the bitmap
API.
This is
Add multi-lrc context registration H2G. In addition a workqueue and
process descriptor are setup during multi-lrc context registration as
these data structures are needed for multi-lrc submission.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_context_types.h | 6 +
drivers/gpu
Move the job of creating a new sync fence and installing it onto a file
descriptor to i915_gem_execbuffer2.
Suggested-by: Tvrtko Ursulin
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 39 +--
1 file changed, 19 insertions(+), 20 deletions(-)
di
Update parallel submit doc to point to i915_drm.h
Signed-off-by: Matthew Brost
---
Documentation/gpu/rfc/i915_parallel_execbuf.h | 122 --
Documentation/gpu/rfc/i915_scheduler.rst | 4 +-
2 files changed, 2 insertions(+), 124 deletions(-)
delete mode 100644 Documentation/
Allow specifying the batch directly over what is inferred from passed in
execbuf flags.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem
Some workloads use lots of contexts that continually pin / unpin
contexts. With GuC submission an unpin translates to a schedule disable
H2G which puts pressure on both the i915 and GuC. A schedule disable can
also block future requests from being submitted until the operation
completes. None of th
Only track object dependencies on the first request generated from the
execbuf, this help with the upcoming multi-bb execbuf extension.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/
Expose logical engine instance to user via query engine info IOCTL. This
is required for split-frame workloads as these needs to be placed on
engines in a logically contiguous order. The logical mapping can change
based on fusing. Rather than having user have knowledge of the fusing we
simply just
Introduce 'set parallel submit' extension to connect UAPI to GuC
multi-lrc interface. Kernel doc in new uAPI should explain it all.
Cc: Tvrtko Ursulin
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 157 +-
.../gpu/drm/i915/gem/i915_gem_context_t
Certain VMA functions in the execbuf IOCTL only need to be called on
first or last BB of a multi-BB submission. eb_relocate() on the first
and eb_release_vmas() on the last. Doing so will save CPU / GPU cycles.
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 127
In case of multiple batches all batches will be at the beginning in the
exex objects array or at the end based on the existing execbuffer2 flag.
Batches not executed in the current execbuf call will not be processed
for relocations or but will be pinned in same manner as the current
batch.
This w
Enable multi-bb execbuf by enabling the set_parallel extension.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 2b0d
This will help with upcoming extensions where more than 1 batch can be
submitted in a single execbuf IOCTL.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 19 +--
1 file changed, 9 insertions(+), 10 deletions(-)
di
Hold all parallel requests, via a submit fence, until the last request
is generated. If an error occurs in the middle of generating the
requests, skip the requests signal the backend of the error via a
request flag.
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c|
A weak implementation of parallel submission (multi-bb execbuf IOCTL) for
execlists. Basically doing as little as possible to support this
interface for execlists - basically just passing submit fences between
each request generated and virtual engines are not allowed. This is on
par with what is t
Submitting to a subset of hardware contexts is not allowed, so use the
copy engine for GPU relocations when using a parallel context.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/
The heartbeat uses a single instance of a GuC submit engine (GSE) to do
the hang check. As such if a different GSE's state machine hangs, the
heartbeat cannot detect this hang. Add timer to each GSE which in turn
can disable all submissions if it is hung.
Cc: John Harrison
Signed-off-by: Matthew
Add very basic (single submission) multi-lrc selftest.
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 1 +
.../drm/i915/gt/uc/selftest_guc_multi_lrc.c | 168 ++
.../drm/i915/selftests/i915_live_selftests.h | 1 +
3 files changed, 170 inser
If an error occurs in the front end when multi-lrc requests are getting
generated we need to skip these in the backend but we still need to
emit the breadcrumbs seqno. An issues arrises because with multi-lrc
breadcrumbs there is a handshake between the parent and children to make
forwad progress.
For contexts with width set to two or more, we add a mode to execbuf2
which implies there are N batch buffers in the buffer list, each of
which will be sent to one of the engines from the engine map array
(I915_CONTEXT_PARAM_ENGINES, I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT).
Those N batches can e
tree: git://anongit.freedesktop.org/drm-intel for-linux-next-fixes
head: 1354d830cb8f9be966cc07fc61368af27ffb7c4a
commit: 1354d830cb8f9be966cc07fc61368af27ffb7c4a [2/2] drm/i915: Call
i915_globals_exit() if pci_register_device() fails
config: i386-allyesconfig (attached as .config)
compiler: g
On Tue, Aug 03, 2021 at 01:19:12PM -0700, Souza, Jose wrote:
> On Fri, 2021-07-09 at 22:41 -0700, Matt Roper wrote:
> > On Thu, Jul 08, 2021 at 02:18:26PM -0700, José Roberto de Souza wrote:
> > > Alderlake-P have different values for MBUS DBOX A credits depending
> > > if MBUS join is enabled or n
== Series Details ==
Series: Parallel submission aka multi-bb execbuf (rev2)
URL : https://patchwork.freedesktop.org/series/92789/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5e27ca906d33 drm/i915/guc: Allow flexible number of context ids
27bc3be5a17a drm/i915/guc: Connect th
== Series Details ==
Series: Parallel submission aka multi-bb execbuf (rev2)
URL : https://patchwork.freedesktop.org/series/92789/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i
== Series Details ==
Series: Parallel submission aka multi-bb execbuf (rev2)
URL : https://patchwork.freedesktop.org/series/92789/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
/home/cidrm/kernel/Documentation/gpu/i915:525:
./drivers/gpu/drm/i915/gt/uc/intel_guc_s
== Series Details ==
Series: Parallel submission aka multi-bb execbuf (rev2)
URL : https://patchwork.freedesktop.org/series/92789/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10442 -> Patchwork_20767
Summary
---
**
tree: git://anongit.freedesktop.org/drm-intel for-linux-next-fixes
head: 1354d830cb8f9be966cc07fc61368af27ffb7c4a
commit: 1354d830cb8f9be966cc07fc61368af27ffb7c4a [2/2] drm/i915: Call
i915_globals_exit() if pci_register_device() fails
config: x86_64-randconfig-a011-20210803 (attached as
On Thu, 2021-07-29 at 09:59 -0700, Matt Roper wrote:
> The DG2 forcewake table is very similar to the one used by XeHP SDV (and
> both platforms are even presented as a single table in the bspec). For
> the most part DG2 starts using a few additional ranges that were
> 'reserved' on XeHP SDV and s
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