== Series Details ==
Series: drm/i915/guc/slpc: Enable GuC based power management features
URL : https://patchwork.freedesktop.org/series/93026/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+dri
== Series Details ==
Series: drm/i915/guc/slpc: Enable GuC based power management features
URL : https://patchwork.freedesktop.org/series/93026/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10396 -> Patchwork_20707
Summary
> -Original Message-
> From: Intel-gfx On Behalf Of José
> Roberto de Souza
> Sent: Friday, July 16, 2021 6:12 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 2/4] drm/i915/display/psr2: Mark as updated all
> planes that intersect with pipe_clip
>
> Without this p
> -Original Message-
> From: Intel-gfx On Behalf Of José
> Roberto de Souza
> Sent: Friday, July 16, 2021 6:12 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 3/4] drm/i915/display/psr2: Fix cursor updates
> using legacy apis
>
> The fast path only updates cursor
On Wed, Jul 21, 2021 at 10:43:29PM -0700, José Roberto de Souza wrote:
> Allow MIPI DSI ports to be parsed like any other DDI port.
> This will be helpful to integrate into just one function the parse of
> information about integrated panels(eDP and DSI).
>
> Allow MIPI DSI ports to be parsed to b
> -Original Message-
> From: Intel-gfx On Behalf Of José
> Roberto de Souza
> Sent: Friday, July 16, 2021 6:12 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 4/4] drm/i915/display/psr2: Force a PSR exit in
> the frontbuffer modification flushes
>
> The CURSURFLIV
On Wed, Jul 21, 2021 at 10:43:30PM -0700, José Roberto de Souza wrote:
> VBT has support for up two integrated panels but i915 only supports one.
>
> So here stating to add the basic support for two integrated panels
> and moving the DRRS to ddi_vbt_port_info instead of keeping a global
> one.
> O
On Wed, Jul 21, 2021 at 10:43:31PM -0700, José Roberto de Souza wrote:
> Continuing the conversion from single integrated VBT data to two.
>
> Cc: Ville Syrjälä
> Cc: Jani Nikula
> Signed-off-by: José Roberto de Souza
Review-by: Matt Atwood
> ---
> drivers/gpu/drm/i915/display/intel_bios.c
On Wed, Jul 21, 2021 at 10:43:32PM -0700, José Roberto de Souza wrote:
> Continuing the conversion from single integrated VBT data to two, now
> handling backlight data.
>
> Cc: Ville Syrjälä
> Cc: Jani Nikula
> Signed-off-by: José Roberto de Souza
Reviewed-by: Matt Atwood
> ---
> drivers/gpu
On Wed, Jul 21, 2021 at 10:43:29PM -0700, José Roberto de Souza wrote:
> Allow MIPI DSI ports to be parsed like any other DDI port.
> This will be helpful to integrate into just one function the parse of
> information about integrated panels(eDP and DSI).
>
> Allow MIPI DSI ports to be parsed to b
On Thu, Jul 22, 2021 at 01:46:08PM +0100, Tvrtko Ursulin wrote:
>
> On 16/07/2021 21:16, Matthew Brost wrote:
> > With GuC virtual engines the physical engine which a request executes
> > and completes on isn't known to the i915. Therefore we can't attach a
> > request to a physical engines breadc
== Series Details ==
Series: drm/i915/display: Disable audio, DRRS and PSR before planes
URL : https://patchwork.freedesktop.org/series/93024/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10396_full -> Patchwork_20705_full
On Thu, Jul 15, 2021 at 10:36:51AM +0100, Tvrtko Ursulin wrote:
>
> On 24/06/2021 08:05, Matthew Brost wrote:
> > Reset implementation for new GuC interface. This is the legacy reset
> > implementation which is called when the i915 owns the engine hang check.
> > Future patches will offload the en
On 7/22/2021 16:54, Matthew Brost wrote:
Reset implementation for new GuC interface. This is the legacy reset
implementation which is called when the i915 owns the engine hang check.
Future patches will offload the engine hang check to GuC but we will
continue to maintain this legacy path as a fa
On Sat, 2021-07-17 at 12:48 +, Patchwork wrote:
Patch Details
Series: series starting with [1/4] drm/i915/display: Disable FBC when PSR2 is
enabled for xelpd platforms
URL:https://patchwork.freedesktop.org/series/92667/
State: failure
Details:
https://intel-gfx-ci.01.org/tree/drm-
On Fri, Jul 23, 2021 at 05:11:07PM -0700, Lucas De Marchi wrote:
> CNL is the only platform with GRAPHICS_VER == 10. With its removal we
> don't need to handle that version anymore.
>
> Also we can now reduce the max number of slices: the call to
> intel_sseu_set_info() with the highest number of
On Fri, Jul 23, 2021 at 05:10:54PM -0700, Lucas De Marchi wrote:
> Remove DMC firmware for CNL.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_dmc.c | 9 -
> 1 file changed, 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/di
== Series Details ==
Series: drm/i915/guc/slpc: Enable GuC based power management features
URL : https://patchwork.freedesktop.org/series/93026/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10396_full -> Patchwork_20707_full
===
The remaining patches for basic GuC submission [1]. Need 1 more RB and
CI results to get this merged.
v2:
(Checkpatch)
- Fix checkpatch warning (1 remaining overrulled)
(Daniele)
- Use an outer lock in guc_context_block / unblock
Signed-off-by: Matthew Brost
[1] https://patchwork.freedesk
Reset implementation for new GuC interface. This is the legacy reset
implementation which is called when the i915 owns the engine hang check.
Future patches will offload the engine hang check to GuC but we will
continue to maintain this legacy path as a fallback and this code path
is also required
With GuC virtual engines the physical engine which a request executes
and completes on isn't known to the i915. Therefore we can't attach a
request to a physical engines breadcrumbs. To work around this we create
a single breadcrumbs per engine class when using GuC submission and
direct all physica
The new GuC interface introduces an MMIO H2G command,
INTEL_GUC_ACTION_RESET_CLIENT, which is used to implement suspend. This
MMIO tears down any active contexts generating a context reset G2H CTB
for each. Once that step completes the GuC tears down the CTB
channels. It is safe to suspend once thi
From: John Harrison
The serial number tracking of engines happens at the backend of
request submission and was expecting to only be given physical
engines. However, in GuC submission mode, the decomposition of virtual
to physical engines does not happen in i915. Instead, requests are
submitted to
Add disable GuC interrupts to intel_guc_sanitize(). Part of this
requires moving the guc_*_interrupt wrapper function into header file
intel_guc.h.
Signed-off-by: Matthew Brost
Cc: Daniele Ceraolo Spurio
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h | 16 +++
This is required to allow backend specific cleanup
v2:
(John H)
- Rework commit message
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/i915_scheduler.c | 3 ++-
drivers/gpu/drm/i915/i915_scheduler.h | 4 +---
drivers/gpu/drm/i915/i915_scheduler_
Hold a reference to the intel_context over life of an i915_request.
Without this an i915_request can exist after the context has been
destroyed (e.g. request retired, context closed, but user space holds a
reference to the request from an out fence). In the case of GuC
submission + virtual engine,
From: John Harrison
The driver must provide GuC with a list of mmio registers
that should be saved/restored during a GuC-based engine reset.
Unfortunately, the list must be dynamically allocated as its size is
variable. That means the driver must generate the list twice - once to
work out the siz
Update the bonding extension to return -ENODEV when using GuC submission
as this extension fundamentally will not work with the GuC submission
interface.
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 +
1 file changed, 5 insertio
Implement GuC virtual engines. Rather simple implementation, basically
just allocate an engine, setup context enter / exit function to virtual
engine specific functions, set all other variables / functions to guc
versions, and set the engine mask to that of all the siblings.
v2: Update to work wit
From: John Harrison
Added the scheduling policy parameters to the 'guc_info' debugfs state
dump.
Signed-off-by: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 14 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_a
From: John Harrison
Use the official driver default scheduling policies for configuring
the GuC scheduler rather than a bunch of hardcoded values.
v2:
(Matthew Brost)
- Move I915_ENGINE_WANT_FORCED_PREEMPTION to later patch
Signed-off-by: John Harrison
Signed-off-by: Matthew Brost
Reviewed
When using GuC submission, if a context gets banned disable scheduling
and mark all inflight requests as complete.
Cc: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/gt/intel_context.h
GuC will issue a reset on detecting an engine hang and will notify
the driver via a G2H message. The driver will service the notification
by resetting the guilty context to a simple state or banning it
completely.
v2:
(John Harrison)
- Move msg[0] lookup after length check
v3:
(John Harrison)
Move active request tracking to a backend vfunc rather than assuming all
backends want to do this in the manner. In the of case execlists /
ring submission the tracking is on the physical engine while with GuC
submission it is on the context.
Signed-off-by: Matthew Brost
Reviewed-by: John Harriso
If submission is disabled by the backend for any reason, reset the GPU
immediately in the heartbeat code as the backend can't be reenabled
until the GPU is reset.
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 62 +++
The GuC can implement execution qunatums, detect hung contexts and
other such things but it requires the timer expired interrupt to do so.
Signed-off-by: Matthew Brost
CC: John Harrison
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/intel_rps.c | 4
1 file changed, 4 insertions(+)
From: John Harrison
There are many ways in which the hangcheck selftest can fail. Very few
of them actually printed an error message to say what happened. So,
fill in the missing messages.
Signed-off-by: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
Cc: Daniele Ceraolo
From: Rahul Kumar Singh
When GuC submission is enabled, the GuC controls engine resets. Rather
than explicitly triggering a reset, the driver must submit a hanging
context to GuC and wait for the reset to occur.
Signed-off-by: Rahul Kumar Singh
Signed-off-by: John Harrison
Signed-off-by: Matth
From: John Harrison
In the case of a full GPU reset (e.g. because GuC has died or because
GuC's hang detection has been disabled), the driver can't rely on GuC
reporting the guilty context. Instead, the driver needs to scan all
active contexts and find one that is currently executing, as per the
From: John Harrison
Clear the 'disable resets' flag to allow GuC to reset hung contexts
(detected via pre-emption timeout).
Signed-off-by: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 3 +--
1 file changed, 1 insertion
From: John Harrison
The media watchdog mechanism involves GuC doing a silent reset and
continue of the hung context. This requires the i915 driver provide a
golden context to GuC in the ADS.
v2:
(Matthew Brost):
- Fix memory corruption in shmem_read
(John H)
- Use locals rather than define
Implement a simple static mapping algorithm of the i915 priority levels
(int, -1k to 1k exposed to user) to the 4 GuC levels. Mapping is as
follows:
i915 level < 0 -> GuC low level (3)
i915 level == 0 -> GuC normal level (2)
i915 level < INT_MAX-> GuC high level(1)
i9
From: John Harrison
Changing the reset module parameter has no effect on a running GuC.
The corresponding entry in the ADS must be updated and then the GuC
informed via a Host2GuC message.
The new debugfs interface to module parameters allows this to happen.
However, connecting the parameter dat
From: John Harrison
It is impossible to seal all race conditions of resets occurring
concurrent to other operations. At least, not without introducing
excesive mutex locking. Instead, don't complain if it occurs. In
particular, don't complain if trying to send a H2G during a reset.
Whatever the H
Requests may take slightly longer with GuC submission, let's increase
the timeouts in live_requests.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/selftests/i915_request.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.
From: John Harrison
When GuC submission is enabled, the GuC controls engine resets. Rather
than explicitly triggering a reset, the driver must submit a hanging
context to GuC and wait for the reset to occur.
Conversely, one of the tests specifically sends hanging batches to the
engines but wants
From: John Harrison
Some testing environments and some heavier tests are slower than
previous limits allowed for. For example, it can take multiple seconds
for the 'context has been reset' notification handler to reach the
'kill the requests' code in the 'active' version of the 'reset
engines' te
From: Rahul Kumar Singh
When GuC submission is enabled, the GuC controls engine resets. Rather
than explicitly triggering a reset, the driver must submit a hanging
context to GuC and wait for the reset to occur.
Signed-off-by: Rahul Kumar Singh
Signed-off-by: John Harrison
Signed-off-by: Matth
GuC will notify the driver, via G2H, if it fails to
reset an engine. We recover by resorting to a full GPU
reset.
v2:
(John Harrison):
- s/drm_dbg/drm_err
Signed-off-by: Matthew Brost
Signed-off-by: Fernando Pacheco
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h
We receive notification of an engine reset from GuC at its
completion. Meaning GuC has potentially cleared any HW state
we may have been interested in capturing. GuC resumes scheduling
on the engine post-reset, as the resets are meant to be transparent,
further muddling our error state.
There is o
Hi Swati,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip v5.14-rc3 next-20210726]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use
This adds GuC backend support for i915_request_cancel(), which in turn
makes CONFIG_DRM_I915_REQUEST_TIMEOUT work.
This implementation makes use of fence while there are likely simplier
options. A fence was chosen because of another feature coming soon
which requires a user to block on a context u
From: Daniele Ceraolo Spurio
Unblock GuC submission on Gen11+ platforms.
v2:
(Martin Peres / John H)
- Delete debug message when GuC is disabled by default on certain
platforms
Signed-off-by: Michal Wajdeczko
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matthew Brost
Reviewed-
From: John Harrison
Various UMDs require hardware configuration information about the
current platform. A new interface has been added to the KMD to return
this information. So, add a test for the new interfaces.
Signed-off-by: John Harrison
Rodrigo Vivi (1):
tests/i915/query: Query, parse
From: Rodrigo Vivi
Newer platforms have an embedded table giving details about that
platform's hardware configuration. This table can be retrieved from
the KMD via the query API. So add a test for it as both an example of
how to fetch the table and to validate the contents as much as
possible.
S
== Series Details ==
Series: Remaining patches for basic GuC submission (rev2)
URL : https://patchwork.freedesktop.org/series/92912/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ac863c9f348a drm/i915/guc: GuC virtual engines
9b36b2e16d7c drm/i915/guc: Make hangcheck work with
== Series Details ==
Series: Remaining patches for basic GuC submission (rev2)
URL : https://patchwork.freedesktop.org/series/92912/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10399 -> Patchwork_20708
Summary
---
From: John Harrison
Implement support for fetching the hardware description table from the
GuC. The call is made twice - once without a destination buffer to
query the size and then a second time to fill in the buffer.
Note that the table is only available on ADL-P and later platforms.
Cc: Mich
From: Rodrigo Vivi
GuC contains a consolidated table with a bunch of information about the
current device.
Previously, this information was spread and hardcoded to all the components
including GuC, i915 and various UMDs. The goal here is to consolidate
the data into GuC in a way that all interes
From: John Harrison
Various UMDs require hardware configuration information about the
current platform. A bunch of static information is available in a
fixed table that can be retrieved from the GuC.
Test-with: 20210727002812.43469-2-john.c.harri...@intel.com
UMD: https://github.com/intel/comput
== Series Details ==
Series: Add support for querying hw info that UMDs need
URL : https://patchwork.freedesktop.org/series/93044/
State : failure
== Summary ==
Applying: drm/i915/guc: Add fetch of hwconfig table
error: sha1 information is lacking or useless (drivers/gpu/drm/i915/Makefile).
er
From: John Harrison
Implement support for fetching the hardware description table from the
GuC. The call is made twice - once without a destination buffer to
query the size and then a second time to fill in the buffer.
Note that the table is only available on ADL-P and later platforms.
Cc: Mich
From: John Harrison
Various UMDs require hardware configuration information about the
current platform. A bunch of static information is available in a
fixed table that can be retrieved from the GuC.
Test-with: 20210727002812.43469-2-john.c.harri...@intel.com
UMD: https://github.com/intel/comput
From: Rodrigo Vivi
GuC contains a consolidated table with a bunch of information about the
current device.
Previously, this information was spread and hardcoded to all the components
including GuC, i915 and various UMDs. The goal here is to consolidate
the data into GuC in a way that all interes
== Series Details ==
Series: Add support for querying hw info that UMDs need
URL : https://patchwork.freedesktop.org/series/93047/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
84f2c965ffe1 drm/i915/guc: Add fetch of hwconfig table
-:96: WARNING:FILE_PATH_CHANGES: added, moved
Like in the case of several other selftests, generating lots of requests
in a loop takes a bit longer with GuC submission. Increase a timeout in
i915_gem_contexts selftest to take this into account.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 2 +-
1
Patch says it all. Seeing a failure in CI [1] and locally on certain TGL
machines with GuC submission enabled. Let's fix this so we can enable CI
on TGL with GuC submission.
Signed-off-by: Matthew Brost
[1] https://patchwork.freedesktop.org/series/92984/#rev4
Matthew Brost (1):
drm/i915/selft
== Series Details ==
Series: Add support for querying hw info that UMDs need
URL : https://patchwork.freedesktop.org/series/93047/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10399 -> Patchwork_20710
Summary
---
**
== Series Details ==
Series: Increase timeout in i915_gem_contexts selftests
URL : https://patchwork.freedesktop.org/series/93049/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10399 -> Patchwork_20711
Summary
---
**
== Series Details ==
Series: Remaining patches for basic GuC submission (rev2)
URL : https://patchwork.freedesktop.org/series/92912/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10399_full -> Patchwork_20708_full
Summary
-
ADL_P requires that we disable underrun recovery when downscaling (or
using the scaler for YUV420 pipe output), using DSC, or using PSR2.
Otherwise we should be able to enable the underrun recovery.
On DG2 we need to keep underrun recovery disabled at all times, but the
chicken bit in PIPE_CHICKEN
On Sat, Jul 24, 2021 at 11:12:07AM -0700, Matt Roper wrote:
On Fri, Jul 23, 2021 at 05:10:48PM -0700, Lucas De Marchi wrote:
The only real platform with DISPLAY_VER == 10 is GLK, so we don't need
any checks and supporting code for CNL. Remove code and rename
functions/macros accordingly.
Signed
== Series Details ==
Series: drm/i915/adl_p: Allow underrun recovery when possible
URL : https://patchwork.freedesktop.org/series/93054/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10399 -> Patchwork_20712
Summary
---
On Mon, Jul 26, 2021 at 06:13:10AM -0400, Rodrigo Vivi wrote:
On Fri, Jul 23, 2021 at 05:11:14PM -0700, Lucas De Marchi wrote:
The numbers of scalers and sprites depend on the display version, so use
it instead of GRAPHICS_VER. We were mixing both, which let me confused
while removing CNL and GR
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