On Thu, 1 Jul 2021 21:28:06 +0200
Daniel Vetter wrote:
> On Thu, Jul 1, 2021 at 8:27 PM Martin Peres wrote:
> >
> > On 01/07/2021 11:14, Pekka Paalanen wrote:
> > > On Wed, 30 Jun 2021 11:58:25 -0700
> > > John Harrison wrote:
> > >
> > >> On 6/30/2021 01:22, Martin Peres wrote:
> > >>> O
== Series Details ==
Series: drm/i915: IRQ fixes (rev4)
URL : https://patchwork.freedesktop.org/series/92053/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10301_full -> Patchwork_20514_full
Summary
---
**FAILURE**
On Wed, 30 Jun 2021, Lucas De Marchi wrote:
> Typo: RUNTIME_INFO->stp
>
> On Wed, Jun 30, 2021 at 04:06:24PM -0700, Anusha Srivatsa wrote:
>>On the dmc side,we maintain a lookup table with different display
>>stepping-substepping combinations.
>>
>>Instead of adding new table for every new platfor
== Series Details ==
Series: drm: address potential UAF bugs with drm_master ptrs
URL : https://patchwork.freedesktop.org/series/92131/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10301_full -> Patchwork_20515_full
Summar
On Thu, 01 Jul 2021, Matt Roper wrote:
> From: Lucas De Marchi
>
> XeHP SDV is a Intel® dGPU without display. This is just the definition
> of some basic platform macros, by large a copy of current state of
> Tigerlake which does not reflect the end state of this platform.
>
> Bspec: 44467, 48077
On 02/07/2021 10:29, Pekka Paalanen wrote:
On Thu, 1 Jul 2021 21:28:06 +0200
Daniel Vetter wrote:
On Thu, Jul 1, 2021 at 8:27 PM Martin Peres wrote:
On 01/07/2021 11:14, Pekka Paalanen wrote:
On Wed, 30 Jun 2021 11:58:25 -0700
John Harrison wrote:
On 6/30/2021 01:22, Martin Peres wrot
On 01/07/2021 21:24, Martin Peres wrote:
[...]
+ i915->params.enable_guc = ENABLE_GUC_LOAD_HUC;
+ return;
+ }
+
+ /* Default: enable HuC authentication and GuC submission */
+ i915->params.enable_guc = ENABLE_GUC_LOAD_HUC |
ENABLE_GUC_SUBMISSION;
This seems to be in
On Thu, 01 Jul 2021, Matt Roper wrote:
> Vswing programming for SNPS PHYs is just a single step -- look up the
> value that corresponds to the voltage level from a table and program it
> into the SNPS_PHY_TX_EQ register.
I've got some patches to turn this to the same ddi buf trans mechanism
that
On Thu, 01 Jul 2021, Matt Roper wrote:
> DG2 has some changes to the expected modesetting sequences when compared
> to gen12. Adjust our driver logic accordingly. Although the DP
> sequence is pretty similar to TGL's, there are some steps that change,
> so let's split the handling for that out i
On Thu, 01 Jul 2021, Matt Roper wrote:
> From: Anusha Srivatsa
>
> DSC can be supported per DP connector. This patch creates
> a per connector debugfs node to expose the Input and
> Compressed BPP.
>
> The same node can be used from userspace to force
> DSC to a certain BPP.
>
> force_dsc_bpp is
tree: git://anongit.freedesktop.org/drm-intel drm-intel-gt-next
head: 5cd57f676bb946a00275408f0dd0d75dbc466d25
commit: cf586021642d8017cde111b7dd1ba86224e9da51 [8/14] drm/i915/gt: Pipelined
page migration
config: x86_64-randconfig-m001-20210630 (attached as .config)
compiler: gcc-9 (Debian 9.3
== Series Details ==
Series: Begin enabling Xe_HP SDV and DG2 platforms
URL : https://patchwork.freedesktop.org/series/92135/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10301_full -> Patchwork_20518_full
Summary
---
patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Anusha-Srivatsa/Stepping-substepping-reorg-for-DMC/20210702-033236
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: x86_64-randc
On 01/07/2021 23:24, Matt Roper wrote:
Xe_HPG adds some additional INSTDONE_GEOM debug registers; the Mesa team
has indicated that having these reported in the error state would be
useful for debugging GPU hangs. These registers are replicated per-DSS
with gslice steering.
Cc: Lionel Landwerlin
On Thu, Jul 1, 2021 at 10:26 PM Matt Roper wrote:
>
> From: Paulo Zanoni
>
> The current interrupt handler is getting increasingly complicated and
> Xe_HP changes will bring even more complexity. Let's split off a new
> interrupt handler starting with DG1 (i.e., when the master tile
> interrupt
From: Patnana Venkata Sai
DSC can be supported per DP connector. This patch creates
a per connector debugfs node to expose the Input and
Compressed BPP.
The same node can be used from userspace to force
DSC to a certain BPP.
force_dsc_bpp is written through this debugfs
node to force DSC BPP to
From: Patnana Venkata Sai
[What]:
This patch creates a per connector debugfs node to expose
the Input and Compressed BPP.
The same node can be used from userspace to force
DSC to a certain BPP(all accepted values).
[Why]:
Useful to verify all supported/requested compression bpp's
through IGT
v
From: Anusha Srivatsa
Set compress BPP in kernel while connector DP or eDP
Cc: Vandita Kulkarni
Cc: Navare Manasi D
Signed-off-by: Anusha Srivatsa
Signed-off-by: Patnana Venkata Sai
---
drivers/gpu/drm/i915/display/intel_dp.c | 23 ++-
1 file changed, 18 insertions(+), 5
tree: git://anongit.freedesktop.org/drm-intel drm-intel-gt-next
head: 13c2ceb6addb6b14468e09b75832c98909eed8e7
commit: d53ec322dc7de32a59bf1c2a56b93e90fc2f1c28 [7/8] drm/i915/ttm: switch
over to ttm_buddy_man
config: x86_64-randconfig-m001-20210630 (attached as .config)
compiler: gcc-9 (Debian
== Series Details ==
Series: drm/i915/display/dsc: Set BPP in the kernel (rev5)
URL : https://patchwork.freedesktop.org/series/91917/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
31d490bc229f drm/i915/display/dsc: Add Per connector debugfs node for DSC BPP
enable
-:64: CHECK:
== Series Details ==
Series: drm/i915/display/dsc: Set BPP in the kernel (rev5)
URL : https://patchwork.freedesktop.org/series/91917/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/
On Fri, 2 Jul 2021 at 09:45, Dan Carpenter wrote:
>
> tree: git://anongit.freedesktop.org/drm-intel drm-intel-gt-next
> head: 5cd57f676bb946a00275408f0dd0d75dbc466d25
> commit: cf586021642d8017cde111b7dd1ba86224e9da51 [8/14] drm/i915/gt:
> Pipelined page migration
> config: x86_64-randconfig-
== Series Details ==
Series: drm/i915/display/dsc: Set BPP in the kernel (rev5)
URL : https://patchwork.freedesktop.org/series/91917/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10302 -> Patchwork_20519
Summary
---
The block here can't be NULL, especially since we already dereferenced
it earlier, so remove the redundant check.
igt_check_blocks() warn: variable dereferenced before check 'block' (see line
126)
Reported-by: Dan Carpenter
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/selftests/i915_b
If mock_region_create fails then mem will be an error pointer. Instead
we just need to use the correct ordering for the onion unwind.
igt_mock_reserve() error: 'mem' dereferencing possible ERR_PTR()
Reported-by: kernel test robot
Reported-by: Dan Carpenter
Signed-off-by: Matthew Auld
---
driv
On Fri, Jul 02, 2021 at 11:32:45AM +0100, Matthew Auld wrote:
> On Fri, 2 Jul 2021 at 09:45, Dan Carpenter wrote:
> >
> > tree: git://anongit.freedesktop.org/drm-intel drm-intel-gt-next
> > head: 5cd57f676bb946a00275408f0dd0d75dbc466d25
> > commit: cf586021642d8017cde111b7dd1ba86224e9da51 [8/1
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: fix smatch warning in
igt_check_blocks
URL : https://patchwork.freedesktop.org/series/92150/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0da2bc133432 drm/i915/selftests: fix smatch warning in igt_che
On Fri, Jul 02, 2021 at 02:07:27PM +0300, Dan Carpenter wrote:
> On Fri, Jul 02, 2021 at 11:32:45AM +0100, Matthew Auld wrote:
> > On Fri, 2 Jul 2021 at 09:45, Dan Carpenter wrote:
> > > cf586021642d80 Chris Wilson 2021-06-17 84
> > > cf586021642d80 Chris Wilson 2021-06-17 85 err =
On Fri, 2 Jul 2021 at 12:07, Dan Carpenter wrote:
>
> On Fri, Jul 02, 2021 at 11:32:45AM +0100, Matthew Auld wrote:
> > On Fri, 2 Jul 2021 at 09:45, Dan Carpenter wrote:
> > >
> > > tree: git://anongit.freedesktop.org/drm-intel drm-intel-gt-next
> > > head: 5cd57f676bb946a00275408f0dd0d75dbc4
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: fix smatch warning in
igt_check_blocks
URL : https://patchwork.freedesktop.org/series/92150/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10302 -> Patchwork_20520
On Fri, 2 Jul 2021 at 12:14, Dan Carpenter wrote:
>
> On Fri, Jul 02, 2021 at 02:07:27PM +0300, Dan Carpenter wrote:
> > On Fri, Jul 02, 2021 at 11:32:45AM +0100, Matthew Auld wrote:
> > > On Fri, 2 Jul 2021 at 09:45, Dan Carpenter
> > > wrote:
> > > > cf586021642d80 Chris Wilson 2021-06-17 84
On 01/07/2021 21:23, Matt Roper wrote:
From: Venkata Sandeep Dhanalakota
In Gen12 there are various fuse combinations and in each configuration
vdbox engine may be connected to SFC depending on which engines are
available, so we need to set the SFC capability based on fuse value from
the hard
On Fri, Jul 02, 2021 at 12:34:33PM +0100, Matthew Auld wrote:
> > > > cf586021642d80 Chris Wilson 2021-06-17 85 err =
> > > > fn(migrate, &ww, src, dst, &rq);
> > > > cf586021642d80 Chris Wilson 2021-06-17 86 if (!err)
> > > > cf586021642d80 Chris Wilson 2021-06-17 87
On 01/07/2021 21:23, Matt Roper wrote:
From: John Harrison
Xe_HP can have a lot of extra media engines. This patch adds the basic
definitions for them.
Cc: Tvrtko Ursulin
Signed-off-by: John Harrison
Signed-off-by: Tomas Winkler
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/gen
On 01/07/2021 21:23, Matt Roper wrote:
From: Lucas De Marchi
Besides the arch version returned by GRAPHICS_VER(), new platforms
contain a "release id" to make clear the difference from one platform to
another. Although for the first ones we may use them as if they were a
What does "first on
On 01/07/2021 21:23, Matt Roper wrote:
From: John Harrison
Xe_HP can have a lot of extra media engines. This patch adds the
interrupt handler support for them.
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Signed-off-by: John Harrison
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/
On 02.07.2021 10:13, Martin Peres wrote:
> On 01/07/2021 21:24, Martin Peres wrote:
> [...]
>>>
> + i915->params.enable_guc = ENABLE_GUC_LOAD_HUC;
> + return;
> + }
> +
> + /* Default: enable HuC authentication and GuC submission */
> + i915->pa
On 02/07/2021 16:06, Michal Wajdeczko wrote:
On 02.07.2021 10:13, Martin Peres wrote:
On 01/07/2021 21:24, Martin Peres wrote:
[...]
+ i915->params.enable_guc = ENABLE_GUC_LOAD_HUC;
+ return;
+ }
+
+ /* Default: enable HuC authentication and GuC submission */
+ i915
On Thu, 1 Jul 2021 at 16:10, Matthew Auld wrote:
>
> The CPU domain should be static for discrete, and on DG1 we don't need
> any flushing since everything is already coherent, so really all this
> does is an object wait, for which we have an ioctl. Longer term the
> desired caching should be an i
== Series Details ==
Series: drm/i915/display/dsc: Set BPP in the kernel (rev5)
URL : https://patchwork.freedesktop.org/series/91917/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10302_full -> Patchwork_20519_full
Summary
On 7/2/21 6:18 AM, Will Deacon wrote:
On Fri, Jul 02, 2021 at 12:39:41PM +0100, Robin Murphy wrote:
On 2021-07-02 04:08, Guenter Roeck wrote:
On Thu, Jun 24, 2021 at 11:55:26PM +0800, Claire Chang wrote:
If a device is not behind an IOMMU, we look up the device node and set
up the restricted D
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: fix smatch warning in
igt_check_blocks
URL : https://patchwork.freedesktop.org/series/92150/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10302_full -> Patchwork_20520_full
==
On 02.07.2021 15:12, Martin Peres wrote:
> On 02/07/2021 16:06, Michal Wajdeczko wrote:
>>
>>
>> On 02.07.2021 10:13, Martin Peres wrote:
>>> On 01/07/2021 21:24, Martin Peres wrote:
>>> [...]
>
>>
>>> + i915->params.enable_guc = ENABLE_GUC_LOAD_HUC;
>>> + return;
>>
On 01/07/2021 16:10, Matthew Auld wrote:
The CPU domain should be static for discrete, and on DG1 we don't need
any flushing since everything is already coherent, so really all this
Knowledge of the write combine buffer is assumed to be had by anyone involved?
does is an object wait, for whi
On 02.07.2021 10:09, Martin Peres wrote:
> On 02/07/2021 10:29, Pekka Paalanen wrote:
>> On Thu, 1 Jul 2021 21:28:06 +0200
>> Daniel Vetter wrote:
>>
>>> On Thu, Jul 1, 2021 at 8:27 PM Martin Peres
>>> wrote:
On 01/07/2021 11:14, Pekka Paalanen wrote:
> On Wed, 30 Jun 2021 11:58:2
Hi Nathan,
On Thu, Jul 01, 2021 at 12:52:20AM -0700, Nathan Chancellor wrote:
> On 7/1/2021 12:40 AM, Will Deacon wrote:
> > On Wed, Jun 30, 2021 at 08:56:51AM -0700, Nathan Chancellor wrote:
> > > On Wed, Jun 30, 2021 at 12:43:48PM +0100, Will Deacon wrote:
> > > > On Wed, Jun 30, 2021 at 05:17:2
On Fri, Jul 02, 2021 at 12:39:41PM +0100, Robin Murphy wrote:
> On 2021-07-02 04:08, Guenter Roeck wrote:
> > On Thu, Jun 24, 2021 at 11:55:26PM +0800, Claire Chang wrote:
> > > If a device is not behind an IOMMU, we look up the device node and set
> > > up the restricted DMA when the restricted-dm
On 2021-07-02 04:08, Guenter Roeck wrote:
Hi,
On Thu, Jun 24, 2021 at 11:55:26PM +0800, Claire Chang wrote:
If a device is not behind an IOMMU, we look up the device node and set
up the restricted DMA when the restricted-dma-pool is presented.
Signed-off-by: Claire Chang
Tested-by: Stefano St
On 2021-07-02 14:58, Will Deacon wrote:
Hi Nathan,
On Thu, Jul 01, 2021 at 12:52:20AM -0700, Nathan Chancellor wrote:
On 7/1/2021 12:40 AM, Will Deacon wrote:
On Wed, Jun 30, 2021 at 08:56:51AM -0700, Nathan Chancellor wrote:
On Wed, Jun 30, 2021 at 12:43:48PM +0100, Will Deacon wrote:
On We
== Series Details ==
Series: Restricted DMA (rev2)
URL : https://patchwork.freedesktop.org/series/91883/
State : failure
== Summary ==
Applying: swiotlb: Refactor swiotlb init functions
Applying: swiotlb: Refactor swiotlb_create_debugfs
Applying: swiotlb: Set dev->dma_io_tlb_mem to the swiotlb
On Thu, Jul 1, 2021 at 4:24 PM Michael J. Ruhl wrote:
>
> From: Thomas Hellström
>
> If our exported dma-bufs are imported by another instance of our driver,
> that instance will typically have the imported dma-bufs locked during
> dma_buf_map_attachment(). But the exporter also locks the same re
On Fri, Jul 02, 2021 at 12:53:53AM +0800, Desmond Cheong Zhi Xi wrote:
> This patch series addresses potential use-after-free errors when
> dereferencing pointers to struct drm_master. These were identified after one
> such bug was caught by Syzbot in drm_getunique():
> https://syzkaller.appspot.
On Thu, Jul 01, 2021 at 10:58:31AM +0200, Thomas Zimmermann wrote:
> Fix a bug in the usage of IRQs and cleanup references to the DRM
> IRQ midlayer.
>
> Preferably this patchset would be merged through drm-misc-next.
>
> v4:
> * switch IRQ code to intel_synchronize_irq() (Daniel)
> v3:
>
On Thu, Jul 01, 2021 at 03:36:49PM +0100, Matthew Auld wrote:
> It's a noop on DG1, and in the future when need to support other devices
> which let us control the coherency, then it should be an immutable
> creation time property for the BO.
>
> Suggested-by: Daniel Vetter
> Signed-off-by: Matth
On Fri, Jul 02, 2021 at 03:31:08PM +0100, Tvrtko Ursulin wrote:
>
> On 01/07/2021 16:10, Matthew Auld wrote:
> > The CPU domain should be static for discrete, and on DG1 we don't need
> > any flushing since everything is already coherent, so really all this
>
> Knowledge of the write combine buff
On Thu, Jul 01, 2021 at 07:36:16PM +0200, Thomas Zimmermann wrote:
> Fix a bug in the usage of IRQs and cleanup references to the DRM
> IRQ midlayer.
>
> Preferably this patchset would be merged through drm-misc-next.
>
> v5:
> * go back to _hardirq() after CI tests reported atomic
>
We're not consistently recommending these for developers only.
I stumbled over this due to DRM_I915_LOW_LEVEL_TRACEPOINTS, which was
added in
commit 354d036fcf70654cff2e2cbdda54a835d219b9d2
Author: Tvrtko Ursulin
Date: Tue Feb 21 11:01:42 2017 +
drm/i915/tracepoints: Add request submi
From: Ville Syrjälä
Write the tiling check in a nicer form. No functional
changes due to Y-tile scanout being a gen9+ feature.
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff -
From: Ville Syrjälä
The way we calculate the CFB stride/size is kind of a mess, and
I'm not sure if we're even allocating enough stolen memory always.
Let's make it all more straightforward, and add some new related
workarounds as well.
Ville Syrjälä (8):
drm/i915/fbc: Rewrite the FBC tiling c
From: Ville Syrjälä
Pull the fbc enable vs. disable stuff into a small helper so
we don't have to have it pollute the higher level modeset code.
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +---
drivers/gpu/drm/i915/display/intel
From: Ville Syrjälä
On ILK+ we current do a nuke right after activating FBC. If my
memory isn't playing tricks on me this is actially required if
FBC didn't stay disabled for a full frame. In that case the
deactivate+reactivate may not invalidate the cfb. I'd have to
double chekc to be sure thoug
From: Ville Syrjälä
Polish the FBC stride override stuff:
- just call it override_cfb_stride since it'll be used on
more gens later
- Use REG_BIT() & co. for the registers and give everything
CHICKEN_ prefix since glk+ will have a different register
for this
- Use intel_de_rmw() for the RMW
From: Ville Syrjälä
The code to calculate the cfb stride/size is a bit of mess.
The cfb size is getting calculated based purely on the plane
stride and plane height. That doesn't account for extra
alignment we want for the cfb stride. The gen9 override
stride OTOH is just calculated based on the
From: Ville Syrjälä
Apply the same 512 byte FBC segment alignment to glk+ as we use
on skl+. The only real difference is that we now have a dedicated
register for the FBC override stride. Not 100% sure which
platforms really need the 512B alignment, but it's easieest
to just do it on everything.
From: Ville Syrjälä
There's some kind of weird corner cases in FBC which requires
FBC segments to be separated by at least one extra cacheline.
Make sure that is present.
TODO: the formula laid out in the spec seem to be semi-nonsense
so this is mostly my interpretation on what it is actually tr
From: Ville Syrjälä
On FBC1 we can specify an arbitrary cfb stride. The hw will
simply throw away any compressed line that would exceed the
specified limit and keep using the uncompressed data instead.
Thus we can allow arbitrary compression limits.
The one thing we have to keep in mind though i
== Series Details ==
Series: drm/i915: Improve debug Kconfig texts a bit
URL : https://patchwork.freedesktop.org/series/92161/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
770403e058ed drm/i915: Improve debug Kconfig texts a bit
-:11: ERROR:GIT_COMMIT_ID: Please use git commit
== Series Details ==
Series: drm/i915: Improve debug Kconfig texts a bit
URL : https://patchwork.freedesktop.org/series/92161/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10304 -> Patchwork_20522
Summary
---
**SUCC
== Series Details ==
Series: drm/i915/fbc: Rework CFB stride/size calculations
URL : https://patchwork.freedesktop.org/series/92163/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/d
== Series Details ==
Series: drm/i915/fbc: Rework CFB stride/size calculations
URL : https://patchwork.freedesktop.org/series/92163/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10304 -> Patchwork_20523
Summary
---
== Series Details ==
Series: drm/i915: Improve debug Kconfig texts a bit
URL : https://patchwork.freedesktop.org/series/92161/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10304_full -> Patchwork_20522_full
Summary
---
== Series Details ==
Series: drm/i915/fbc: Rework CFB stride/size calculations
URL : https://patchwork.freedesktop.org/series/92163/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10304_full -> Patchwork_20523_full
Summary
-
72 matches
Mail list logo
