On Thu, 27 May 2021 at 20:04, Daniel Vetter wrote:
>
> On Wed, May 26, 2021 at 10:35:49AM +1000, Dave Airlie wrote:
> > On Wed, 12 May 2021 at 03:05, Daniel Vetter wrote:
> > > On Tue, May 11, 2021 at 10:31:39AM +0200, Zbigniew Kempczyński wrote:
> > > > We have established previously we stop usi
On Tue, Jun 1, 2021 at 9:19 AM Dave Airlie wrote:
> On Thu, 27 May 2021 at 20:04, Daniel Vetter wrote:
> > On Wed, May 26, 2021 at 10:35:49AM +1000, Dave Airlie wrote:
> > > On Wed, 12 May 2021 at 03:05, Daniel Vetter wrote:
> > > > On Tue, May 11, 2021 at 10:31:39AM +0200, Zbigniew Kempczyński
Any sleeping dma_resv lock taken while the vma pages_mutex is held
will cause a lockdep splat.
Move the i915_gem_object_pin_pages() call out of the pages_mutex
critical section.
Signed-off-by: Thomas Hellström
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/i915_vma.c | 29 +
This is an initial patch series to move discrete memory management over to
TTM. It will be followed up shortly with adding more functionality.
The buddy allocator is temporarily removed along with its selftests and
It is replaced with the TTM range manager and some selftests are adjusted
to accoun
We are currently sharing the VM reservation locks across a number of
gem objects with page-table memory. Since TTM will individiualize the
reservation locks when freeing objects, including accessing the shared
locks, make sure that the shared locks are not freed until that is done.
For PPGTT we add
Embed a struct ttm_buffer_object into the i915 gem object, making sure
we alias the gem object part. It's a bit unfortunate that the
struct ttm_buffer_ojbect embeds a gem object since we otherwise could
make the TTM part private to the TTM backend, and use the usual
i915 gem object for the other ba
All users of this function actually want the dma segment sizes, but that's
not what's calculated. Fix that and rename the function to
i915_sg_dma_sizes to reflect what's calculated.
Signed-off-by: Thomas Hellström
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 2 +-
Temporarily remove the buddy allocator and related selftests
and hook up the TTM range manager for i915 regions.
Also modify the mock region selftests somewhat to account for a
fragmenting manager.
Signed-off-by: Thomas Hellström
Reviewed-by: Matthew Auld #v2
---
v2:
- Fix an error unwind in lm
The internal ttm_bo_util memcpy uses ioremap functionality, and while it
probably might be possible to use it for copying in- and out of
sglist represented io memory, using io_mem_reserve() / io_mem_free()
callbacks, that would cause problems with fault().
Instead, implement a method mapping page-b
If the bo is idle when calling ttm_bo_pipeline_gutting(), we unnecessarily
create a ghost object and push it out to delayed destroy.
Fix this by adding a path for idle, and document the function.
Also avoid having the bo end up in a bad state vulnerable to user-space
triggered kernel BUGs if the c
Use fast wc memcpy for reading out of wc memory for TTM bo moves.
Cc: Dave Airlie
Cc: Christian König
Cc: Daniel Vetter
Signed-off-by: Thomas Hellström
Reviewed-by: Christian König #v4
--
v4:
- Clarify when we try drm_memcpy_from_wc_dbm (Reported by Matthew Auld)
- Be paranoid about when drm_
Reading out of write-combining mapped memory is typically very slow
since the CPU doesn't prefetch. However some archs have special
instructions to do this.
So add a best-effort memcpy_from_wc taking dma-buf-map pointer
arguments that attempts to use a fast prefetching memcpy and
otherwise falls b
We are calling the eviction_valuable driver callback at eviction time to
determine whether we actually can evict a buffer object.
The upcoming i915 TTM backend needs the same functionality for swapout,
and that might actually be beneficial to other drivers as well.
Add an eviction_valuable call al
Most logical place to introduce TTM buffer objects is as an i915
gem object backend. We need to add some ops to account for added
functionality like delayed delete and LRU list manipulation.
Initially we support only LMEM and SYSTEM memory, but SYSTEM
(which in this case means evicted LMEM objects
Since objects can be migrated or evicted when not pinned or locked,
update the checks for lmem residency or future residency so that
the value returned is not immediately stale.
Signed-off-by: Thomas Hellström
Reviewed-by: Matthew Auld
---
v2: Simplify i915_gem_object_migratable() (Reported by M
From: Maarten Lankhorst
The platform should exclusively use mmap_offset, one less path to worry
about for discrete.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gp
From: Maarten Lankhorst
This allows drivers to distinguish between different types of vma_node's.
The readonly flag was unused and is thus removed.
This is a temporary solution, until i915 is converted completely to
use ttm for bo's.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellstr
From: Maarten Lankhorst
Use the ttm handlers for servicing page faults, and vm_access.
We do our own validation of read-only access, otherwise use the
ttm handlers as much as possible.
Because the ttm handlers expect the vma_node at vma->base, we slightly
need to massage the mmap handlers to lo
== Series Details ==
Series: Move LMEM (VRAM) management over to TTM (rev5)
URL : https://patchwork.freedesktop.org/series/90681/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
325ee27eefe0 drm/i915: Untangle the vma pages_mutex
b8ec60cc312c drm/i915: Don't free shared locks whi
== Series Details ==
Series: Move LMEM (VRAM) management over to TTM (rev5)
URL : https://patchwork.freedesktop.org/series/90681/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./drivers/gpu/drm/
We have established previously we stop using relocations starting
from gen12 platforms with Tigerlake as an exception. We keep this
statement but we want to enable relocations conditionally for
Rocketlake and Alderlake under require_force_probe flag set.
Keeping relocations under require_force_pro
== Series Details ==
Series: Move LMEM (VRAM) management over to TTM (rev5)
URL : https://patchwork.freedesktop.org/series/90681/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10153 -> Patchwork_20243
Summary
---
**S
== Series Details ==
Series: drm/i915: Add relocation exceptions for two other platforms (rev3)
URL : https://patchwork.freedesktop.org/series/89594/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
07cc51d80ac1 drm/i915: Add relocation exceptions for two other platforms
-:44: CHE
On 2021.05.23 10:23:04 -0700, Guenter Roeck wrote:
> Use list_entry() instead of container_of() to access list members.
> Also drop unnecessary and misleading NULL checks on the result of
> list_entry().
>
> Signed-off-by: Guenter Roeck
> ---
> v2: Checkpatch fixes:
> - Fix alignment
> -
Hi Stephen,
> After merging the i2c tree, today's linux-next build (x86_64 allmodconfig)
> failed like this:
>
> In file included from drivers/gpu/drm/i915/i915_gem.c:1250:
> drivers/gpu/drm/i915/selftests/i915_gem.c:97:13: error: conflicting types for
> 'pm_suspend'
>97 | static void pm_sus
On Tue, Jun 1, 2021 at 4:55 PM Wolfram Sang wrote:
>
> Hi Stephen,
>
> > After merging the i2c tree, today's linux-next build (x86_64 allmodconfig)
> > failed like this:
> >
> > In file included from drivers/gpu/drm/i915/i915_gem.c:1250:
> > drivers/gpu/drm/i915/selftests/i915_gem.c:97:13: error:
On 28/05/2021 11:04, YueHaibing wrote:
Use DEVICE_ATTR_RO() helper instead of plain DEVICE_ATTR(),
which makes the code a bit shorter and easier to read.
Signed-off-by: YueHaibing
---
drivers/gpu/drm/i915/i915_pmu.c | 8 +++-
drivers/gpu/drm/i915/i915_sysfs.c | 30 +++---
== Series Details ==
Series: drm/i915: Add relocation exceptions for two other platforms (rev3)
URL : https://patchwork.freedesktop.org/series/89594/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10153 -> Patchwork_20244
Su
[Don't see this on intel-gfx so I have to reply with top post.]
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
-Original Message-
From: Zhihao Cheng
Sent: Saturday, May 29, 2021 5:33 AM
To: jani.nik...@linux.intel.com; joonas.lahti...@linux.intel.com; Vivi, Rodrigo
; airl...@linux.ie
> Hi, this issue is fixed in
> https://cgit.freedesktop.org/drm-intel/commit/?h=drm-intel-gt-next&id=5b11705608898c31a1cae5340555ee60d5a4fa45
>
> And I think the pull request is in
> https://lists.freedesktop.org/archives/intel-gfx/2021-May/267588.html
Thanks for the heads up. So, I'll wait with
We need to make the BSW workaround actually work. We correctly fixed
the mutex nesting, but forgot to kill the worker.
The worker is killed by clearing async_flags, and just running bind_vma
synchronously. This still needs the stash, because we cannot allocate
and pin with vm->mutex already held.
On 27/05/2021 18:01, John Harrison wrote:
On 5/27/2021 01:53, Tvrtko Ursulin wrote:
On 26/05/2021 19:45, John Harrison wrote:
On 5/26/2021 01:40, Tvrtko Ursulin wrote:
On 25/05/2021 18:52, Matthew Brost wrote:
On Tue, May 25, 2021 at 11:16:12AM +0100, Tvrtko Ursulin wrote:
On 06/05/2021 2
This introduces the following function that can exit and activate a psr
source when intel_psr is already enabled.
- intel_psr_pause(): Pause current PSR. It deactivates current psr state.
- intel_psr_resume(): Resume paused PSR. It activates paused psr state.
v2: Address Jose's review comment.
XE_LPD hardware introduced a new gamma mode i.e, Logarithmic
gamma mode. Added support for the same.
Signed-off-by: Uma Shankar
Signed-off-by: Bhanuprakash Modem
---
drivers/gpu/drm/i915/display/intel_color.c | 111 -
drivers/gpu/drm/i915/i915_reg.h| 1 +
inclu
This defines the color lut ranges for logarithmic gamma which
is being introduced from XE_LPD onwards.
Signed-off-by: Uma Shankar
Signed-off-by: Bhanuprakash Modem
---
drivers/gpu/drm/i915/display/intel_color.c | 250 -
1 file changed, 246 insertions(+), 4 deletions(-)
diff
Only Enable Logarithmic Gamma if client caps for advance gamma mode
is enabled. Fallback to 10bit gamma in case its not supported.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/
Attach the gamma mode property to allow userspace set the gamma mode
and provide the luts for the same.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915
Add a gamma mode property to enable various kind of
gamma modes supported by platforms like: Interpolated, Split,
Multi Segmented, Logarithmic etc. Userspace can get this property
and should be able to get the platform capabilities wrt various
gamma modes possible and the possible ranges.
It can s
Modern hardwares have multi segmented lut approach to prioritize
the darker regions of the spectrum. This series introduces a new
UAPI to define the lut ranges supported by the respective hardware.
This also enables Pipe Color Management Support for Intel's XE_LPD hw.
Enable Support for Pipe Degam
Enable Pipe Degamma for XE_LPD. Extend the legacy implementation
to incorparate the extended lut size for XE_LPD.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/displa
Introduced a client cap for advance cap mode capability. Userspace
should set this to get to be able to use the new gamma_mode property.
If this is not set, driver will work in legacy mode.
Note: This is suggested by Ville and based on his idea, the new
gamma mode handling is designed.
Signed-of
XE_LPD has 128 Lut entries for Degamma, with additional 3 entries for
extended range. It has 511 entries for gamma with additional 2 entries
for extended range.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/dr
Enable support for Logarithmic gamma readout for XE_LPD.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 72 ++
drivers/gpu/drm/i915/i915_reg.h| 6 ++
2 files changed, 78 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_c
On 27/05/2021 11:27, Daniel Vetter wrote:
On Thu, May 27, 2021 at 11:22:16AM +0100, Tvrtko Ursulin wrote:
On 27/05/2021 11:13, Daniel Vetter wrote:
On Wed, May 26, 2021 at 11:20:13AM +0100, Tvrtko Ursulin wrote:
On 25/05/2021 15:47, Daniel Vetter wrote:
On Tue, May 25, 2021 at 03:19:47PM
This is how a typical display color hardware pipeline looks like:
+---+
|RAM|
| +--++-++-+ |
| | FB 1 || FB 2 || FB N| |
| +--++-++-+
Existing LUT precision structure is having only 16 bit
precision. This is not enough for upcoming enhanced hardwares
and advance usecases like HDR processing. Hence added a new
structure with 32 bit precision values.
This also defines a new structure to define color lut ranges,
along with related
Add Plane Degamma Lut as a blob property. User will calculate
the lut values, create the blob and send it to driver using
this property. Lut calculation will be based on the gamma mode
chosen out of the gamma mode exposed.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_atomic_state_helper.c
Add Plane Degamma Mode as an enum property. Create a helper
function for all plane color management features.
This is an enum property with values as blob_id's and exposes
the various gamma modes supported and the lut ranges. Getting
the blob id in userspace, user can get the mode supported and
al
Define the structure with XE_LPD degamma lut ranges. HDR and SDR
planes have different capabilities, implemented respective
structure for the HDR planes.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 52 ++
1 file changed, 52 insertions(+)
diff
Add macros to define Plane Degamma registers
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 52 +
1 file changed, 52 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 24307c49085f..9431913969f3 10
Enable and initialize plane color features.
Also initialize the color features of HDR planes.
Signed-off-by: Uma Shankar
Signed-off-by: Bhanuprakash Modem
---
drivers/gpu/drm/i915/display/intel_color.c | 22 +-
drivers/gpu/drm/i915/display/intel_color.h | 2 ++
drivers/gpu/
Add the Color capabilities of SDR planes.
Signed-off-by: Uma Shankar
Signed-off-by: Bhanuprakash Modem
---
drivers/gpu/drm/i915/display/intel_color.c | 67 --
1 file changed, 63 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers
Extract the LUT and program plane degamma registers.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 116 +
drivers/gpu/drm/i915/i915_reg.h| 2 +
2 files changed, 118 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_colo
Extended glk_plane_color_ctl to have plane color checks. This helps
enabling the degamma or gamma block based on user inputs.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/sk
Initialize plane color features for XE_LPD.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_atomic_plane.h | 1 +
drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
b/driv
Load plane color luts as part of atomic plane updates.
This will be done only if the plane color luts are changed.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 3 +++
drivers/gpu/drm/i915/display/intel_atomic_plane.h | 1 +
drivers/gpu/drm/i915/display/intel
Add a blob property for plane CSC usage.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_atomic_state_helper.c | 3 +++
drivers/gpu/drm/drm_atomic_uapi.c | 10 ++
drivers/gpu/drm/drm_color_mgmt.c | 11 +++
include/drm/drm_plane.h | 15 ++
Add a DRM helper to attach ctm property.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_color_mgmt.c | 10 ++
include/drm/drm_plane.h | 1 +
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
index 83832adf3ad
Define Register macros for plane CSC.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 43 +
1 file changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ede7dca440e2..df8500a86e9d 100644
--
Implement plane CSC for ICL+
Signed-off-by: Uma Shankar
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 5 +-
drivers/gpu/drm/i915/display/intel_color.c| 82 +++
.../drm/i915/display/skl_universal_plane.c| 4 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
4
Add Plane Gamma Mode as a blob property. This is an enum property
with values as blob_id's and exposes the various gamma modes
supported and the lut ranges. Getting the blob id in userspace,
user can get the mode supported and also the range of gamma mode
supported with number of lut coefficients.
Add Plane Gamma Lut as a blob property.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_atomic_state_helper.c | 3 +++
drivers/gpu/drm/drm_atomic_uapi.c | 10 ++
drivers/gpu/drm/drm_color_mgmt.c | 18 ++
include/drm/drm_plane.h | 14
Define the structure with XE_LPD gamma lut ranges. HDR and SDR planes
have different capabilities, implemented respective structure for
the HDR planes. Degamma and GAMMA has same Lut caps for SDR planes,
extended the same.
Initialize the mode range caps as well.
Signed-off-by: Uma Shankar
Signed
Add macros to define Plane Gamma registers
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 73 +
1 file changed, 73 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a8e35357aea0..2ebc92104f64 1006
Extract the LUT and program plane gamma registers.
Enabled multi segmented lut as well.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 89 ++
drivers/gpu/drm/i915/i915_reg.h| 9 ++-
2 files changed, 94 insertions(+), 4 deletions(-)
d
Enable plane gamma feature in check callbacks. Decide
based on the user input.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gp
v2 link: https://patchwork.freedesktop.org/series/77866/
Anshuman Gupta (2):
drm/i915/dg1: Adjust the AUDIO power domain
drm/i915/display: Use AUDIO_VERBS for crtc power domain mask
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
Use POWER_DOMAIN_AUDIO_VERBS power domain instead of
POWER_DOMAIN_AUDIO in crtc power domain mask.
It will save the power in use cases when DP/HDMI connectors
configured with PIPE_A without any audio playback.
Cc: Ville Syrjälä
Cc: Kai Vehmanen
Cc: Uma Shankar
Cc: Imre Deak
Signed-off-by: Ans
DG1 and XE_PLD platforms has Audio MMIO/VERBS lies in PG0 power
well. Adjusting the power domain accordingly to
POWER_DOMAIN_AUDIO_VERBS for audio detection and POWER_DOMAIN_AUDIO
for audio playback.
Cc: Ville Syrjälä
Cc: Kai Vehmanen
Cc: Uma Shankar
Cc: Imre Deak
Signed-off-by: Anshuman Gupta
== Series Details ==
Series: Move LMEM (VRAM) management over to TTM (rev5)
URL : https://patchwork.freedesktop.org/series/90681/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10153_full -> Patchwork_20243_full
Summary
The v2 patch which addressed Jose's comments was floated to
https://patchwork.freedesktop.org/series/90819/
On Fri, 2021-05-21 at 14:52 -0700, Souza, Jose wrote:
> On Fri, 2021-05-21 at 11:58 +0100, Mun, Gwan-gyeong wrote:
> > On Tue, 2021-05-18 at 14:06 +0300, Ville Syrjälä wrote:
> > > On Tue, Ma
== Series Details ==
Series: drm/i915/selftests: Fix return value check in
live_breadcrumbs_smoketest()
URL : https://patchwork.freedesktop.org/series/90817/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9f93f64b2ec8 drm/i915/selftests: Fix return value check in
live_breadcru
== Series Details ==
Series: drm/i915/selftests: Fix return value check in
live_breadcrumbs_smoketest()
URL : https://patchwork.freedesktop.org/series/90817/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10154 -> Patchwork_20245
===
On 31/05/2021 08:53, Daniel Vetter wrote:
On Thu, May 20, 2021 at 4:28 PM Daniel Vetter wrote:
On Thu, May 20, 2021 at 08:35:14AM +0100, Matthew Auld wrote:
From: Chris Wilson
The first tracepoint for a request is trace_dma_fence_init called before
we have associated the request with a devi
== Series Details ==
Series: drm/i915: Only set bind_async_flags when concurrent access wa is not
active, v3.
URL : https://patchwork.freedesktop.org/series/90818/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
48e0a3099384 drm/i915: Only set bind_async_flags when concurrent ac
== Series Details ==
Series: drm/i915: Add relocation exceptions for two other platforms (rev3)
URL : https://patchwork.freedesktop.org/series/89594/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10153_full -> Patchwork_20244_full
==
Few Gen11 systems show CRC mismatch. Make coverage-vs-premult-vs-constant
code similar to constant_alpha_min or basic_alpha
Signed-off-by: Vidya Srinivas
---
tests/kms_plane_alpha_blend.c | 4
1 file changed, 4 deletions(-)
diff --git a/tests/kms_plane_alpha_blend.c b/tests/kms_plane_alpha
== Series Details ==
Series: drm/i915: Only set bind_async_flags when concurrent access wa is not
active, v3.
URL : https://patchwork.freedesktop.org/series/90818/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10154 -> Patchwork_20246
=
-Original Message-
From: Modem, Bhanuprakash
Sent: Wednesday, May 26, 2021 9:29 PM
To: Jani Nikula ; intel-gfx@lists.freedesktop.org;
Varide, Nischal ; Shankar, Uma
; Gupta, Anshuman
Subject: RE: [Intel-gfx] [PATCH 1/2] drm/i915/xelpd: Enabling dithering after
the CC1
> From: Jani
On Tue, Jun 1, 2021 at 1:13 PM Matthew Auld wrote:
> On 31/05/2021 08:53, Daniel Vetter wrote:
> > On Thu, May 20, 2021 at 4:28 PM Daniel Vetter wrote:
> >>
> >> On Thu, May 20, 2021 at 08:35:14AM +0100, Matthew Auld wrote:
> >>> From: Chris Wilson
> >>>
> >>> The first tracepoint for a request
On Tue, 01 Jun 2021, Zbigniew Kempczyński
wrote:
> We have established previously we stop using relocations starting
> from gen12 platforms with Tigerlake as an exception. We keep this
> statement but we want to enable relocations conditionally for
> Rocketlake and Alderlake under require_force_p
On Tue, 01 Jun 2021, Thomas Hellström wrote:
> Reading out of write-combining mapped memory is typically very slow
> since the CPU doesn't prefetch. However some archs have special
> instructions to do this.
>
> So add a best-effort memcpy_from_wc taking dma-buf-map pointer
> arguments that attemp
On Tue, Jun 01, 2021 at 11:36:54AM +, Patchwork wrote:
>Patch Details
>
>Series: drm/i915: Add relocation exceptions for two other platforms
> (rev3)
>URL: https://patchwork.freedesktop.org/series/89594/
>
>State: failure
== Series Details ==
Series: drm/i915/display: Introduce new intel_psr_pause/resume function
URL : https://patchwork.freedesktop.org/series/90819/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10154 -> Patchwork_20247
Summa
== Series Details ==
Series: Enhance pipe color support for multi segmented luts
URL : https://patchwork.freedesktop.org/series/90821/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./drivers/gpu
This introduces the following function that can exit and activate a psr
source when intel_psr is already enabled.
- intel_psr_pause(): Pause current PSR. It deactivates current psr state.
- intel_psr_resume(): Resume paused PSR. It activates paused psr state.
v2: Address Jose's review comment.
From: Ville Syrjälä
AUX logic is often clocked from cdclk. Disable PSR to make sure
there are no hw initiated AUX transactions in flight while we
change the cdclk frequency.
Cc: Mika Kahola
Signed-off-by: Ville Syrjälä
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_cdc
Another patchset has been uploaded. Please ignore this patch.
On Tue, 2021-06-01 at 12:53 +0300, Gwan-gyeong Mun wrote:
> This introduces the following function that can exit and activate a
> psr
> source when intel_psr is already enabled.
>
> - intel_psr_pause(): Pause current PSR. It deactivate
On Thu, May 27, 2021 at 07:29:20PM +0800, Claire Chang wrote:
> On Wed, May 26, 2021 at 11:53 PM Will Deacon wrote:
> >
> > On Wed, May 26, 2021 at 01:13:22PM +0100, Will Deacon wrote:
> > > On Tue, May 18, 2021 at 02:42:14PM +0800, Claire Chang wrote:
> > > > @@ -138,4 +160,9 @@ one for multimedi
The error code returned from intel_context_create() should be propagated
instead of 0, as done elsewhere in this function.
Fixes: 50d16d44cce4 ("drm/i915/selftests: Exercise context switching in
parallel")
Reported-by: Hulk Robot
Signed-off-by: Zhen Lei
---
drivers/gpu/drm/i915/gem/selftests/i
On 2021/5/27 18:04, Jani Nikula wrote:
> On Thu, 27 May 2021, Zhen Lei wrote:
>> If intel_hdcp_validate_v_prime() has been successful within the allowed
>> number of tries, we can directly call drm_dbg_kms() and "goto out" without
>> jumping out of the loop and repeatedly judging whether the op
On Mon, 2021-05-24 at 14:38 +0100, Matthew Auld wrote:
> On Mon, 24 May 2021 at 13:05, Hillf Danton wrote:
> >
> > On Sun, 23 May 2021 12:47:34 -0700 Philippe Troin wrote:
> > > Found the following bug on a FUJITSU LIFEBOOK S6520.
> > >
> > > The kernel crash happens when selecting a user from t
Function 'i915_gem_object_truncate' is declared twice, so remove the
repeated declaration.
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Signed-off-by: Shaokun Zhang
---
drivers/gpu/drm/i915/gem/i915_gem_object.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/g
On Thu, May 27, 2021 at 08:48:59PM +0800, Claire Chang wrote:
> On Thu, May 27, 2021 at 7:35 PM Will Deacon wrote:
> >
> > On Thu, May 27, 2021 at 07:29:20PM +0800, Claire Chang wrote:
> > > On Wed, May 26, 2021 at 11:53 PM Will Deacon wrote:
> > > >
> > > > On Wed, May 26, 2021 at 01:13:22PM +01
On Wed, May 26, 2021 at 01:13:22PM +0100, Will Deacon wrote:
> On Tue, May 18, 2021 at 02:42:14PM +0800, Claire Chang wrote:
> > @@ -138,4 +160,9 @@ one for multimedia processing (named
> > multimedia-memory@7700, 64MiB).
> > memory-region = <&multimedia_reserved>;
> >
In case of error, the function live_context() returns ERR_PTR()
and never returns NULL. The NULL test in the return value check
should be replaced with IS_ERR().
Fixes: 52c0fdb25c7c9 ("drm/i915: Replace global breadcrumbs ...")
Reported-by: Hulk Robot
Signed-off-by: Zhihao Cheng
---
drivers/gpu
We currently treat same slice mask as a same DBuf state and skip
updating the Dbuf slices, if we detect that.
This is wrong as if we have a multi to single pipe change or
vice versa, that would be treated as a same Dbuf state and thus
no changes required, so we don't get Mbus updated, causing issue
If intel_hdcp_validate_v_prime() has been successful within the allowed
number of tries, we can directly call drm_dbg_kms() and "goto out" without
jumping out of the loop and repeatedly judging whether the operation is
successful. This can help us reduce an unnecessary if judgment. And it's
a littl
== Series Details ==
Series: Enhance pipe color support for multi segmented luts
URL : https://patchwork.freedesktop.org/series/90821/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10154 -> Patchwork_20248
Summary
---
== Series Details ==
Series: Add Support for Plane Color Lut and CSC features
URL : https://patchwork.freedesktop.org/series/90825/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
68c5484bfdad drm: Add Enhanced Gamma and color lut range attributes
a1e53948f9d0 drm: Add Plane Dega
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